TWI747931B - Method for forming film - Google Patents
Method for forming film Download PDFInfo
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- TWI747931B TWI747931B TW106126805A TW106126805A TWI747931B TW I747931 B TWI747931 B TW I747931B TW 106126805 A TW106126805 A TW 106126805A TW 106126805 A TW106126805 A TW 106126805A TW I747931 B TWI747931 B TW I747931B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Abstract
Description
本發明涉及成膜方法及成膜裝置。 The present invention relates to a film forming method and a film forming device.
伴隨著近年的微細化工藝的進展,有在元件分離區域中使用的高長寬比的溝槽或孔(以下,溝槽等)內不產生空隙地以絕緣膜進行埋設這樣的要求。此時,有時在形成於溝槽等內的膜中形成空隙。在這樣的狀況下,有將形成於膜中的空隙暫且通過蝕刻開放並在開放後的空隙內再次埋入膜的技術(例如,參照專利文獻1)。 With the progress of the miniaturization process in recent years, there is a demand for embedding with an insulating film without voids in trenches or holes (hereinafter, trenches, etc.) with a high aspect ratio used in the element isolation region. At this time, a void may be formed in the film formed in the trench or the like. Under such a situation, there is a technique of temporarily opening the voids formed in the film by etching and burying the film again in the opened voids (for example, refer to Patent Document 1).
現有技術文獻 Prior art literature
專利文獻 Patent literature
專利文獻1:日本特開2012-134288號公報 Patent Document 1: Japanese Patent Application Publication No. 2012-134288
但是,在暫且將所形成的空隙開放並在開放後的空隙內埋入膜的技術中,成膜工藝變得複雜。由此,需要一種不形成空隙地在溝槽等中埋入膜的技術。 However, in the technique of temporarily opening the formed void and burying the film in the opened void, the film forming process becomes complicated. Therefore, a technique of burying a film in a trench or the like without forming a void is required.
鑒於以上那樣的情況,本發明的目的在於,提供對於形成於溝槽等內的膜而言不形成空隙地在溝槽等內埋入膜的成膜方法及成膜裝置。 In view of the above-mentioned circumstances, an object of the present invention is to provide a film forming method and a film forming apparatus for embedding a film in a trench or the like without forming a gap in a film formed in a trench or the like.
為了達成上述目的,本發明的一方式的成膜方法包含以下工序:通過在設置有具有底部和側壁的溝槽或孔的基板的表面產生包含矽的成膜氣體的第1等離子體,從而在上述底部及上述側壁形成包含矽的第1半導體膜。 In order to achieve the above-mentioned object, a film forming method according to an aspect of the present invention includes the following steps: a first plasma containing a film forming gas containing silicon is generated on the surface of a substrate provided with trenches or holes having a bottom and sidewalls, thereby The bottom and the sidewalls form a first semiconductor film containing silicon.
形成於上述側壁的上述第1半導體膜通過在上述基板的上述表面產生包含鹵素的蝕刻氣體的第2等離子體而被選擇性除去。 The first semiconductor film formed on the side wall is selectively removed by generating a second plasma of an etching gas containing halogen on the surface of the substrate.
通過在上述基板的上述表面產生上述第1等離子體,從而在上述底部及上述側壁形成包含矽的第2半導體膜。 By generating the first plasma on the surface of the substrate, a second semiconductor film containing silicon is formed on the bottom and the sidewalls.
由此,對於形成於溝槽等內的半導體膜而言,不形成空隙地在溝槽等內形成膜。 Thus, for the semiconductor film formed in the trench or the like, the film is formed in the trench or the like without forming a void.
在上述的成膜方法中,形成於上述側壁的上述第1半導體膜被選擇性除去、在上述底部及上述側壁形成上述第2半導體膜的處理也可以重複2次以上。 In the above-mentioned film forming method, the process of selectively removing the first semiconductor film formed on the sidewall and forming the second semiconductor film on the bottom and the sidewall may be repeated twice or more.
由此,在溝槽等內可靠地形成半導體膜。 As a result, the semiconductor film is reliably formed in the trench or the like.
在上述的成膜方法中,產生上述第1等離子體的時間也可以為5分鐘以內。 In the above-mentioned film forming method, the time for generating the above-mentioned first plasma may be within 5 minutes.
由此,溝槽等不會被半導體膜閉塞。 As a result, trenches and the like are not blocked by the semiconductor film.
在上述的成膜方法中,產生上述第2等離子體的時間也可以為5分鐘以內。 In the above-mentioned film forming method, the time for generating the above-mentioned second plasma may be within 5 minutes.
由此,形成於溝槽等的側壁的半導體膜被選擇性除去。 As a result, the semiconductor film formed on the sidewall of the trench or the like is selectively removed.
在上述的成膜方法中,上述蝕刻氣體也可以包含NF3、NCl3、Cl2及H2中的至少1者。 In the above-mentioned film forming method, the above-mentioned etching gas may contain at least one of NF 3 , NCl 3 , Cl 2 and H 2.
由此,形成於溝槽等的側壁的半導體膜通過NF3、NCl3、Cl2及H2中的任一者被化學性地除去。 As a result, the semiconductor film formed on the sidewall of the trench or the like is chemically removed by any one of NF 3 , NCl 3 , Cl 2, and H 2.
在上述的成膜方法中,作為上述第1半導體膜及上述第2半導體膜,形成包含矽的膜及包含磷、砷、銻、硼、鋁、鎵、銦、鍺中的至少1者作為摻雜劑的矽膜中的至少任一者。 In the above-mentioned film forming method, as the first semiconductor film and the second semiconductor film, a film containing silicon and at least one of phosphorus, arsenic, antimony, boron, aluminum, gallium, indium, and germanium is formed as a dopant. At least any one of the silicon film of the miscellaneous agent.
由此,形成於溝槽等內的上述第1半導體膜及第2半導體膜成為包含矽的膜及包含磷、砷、銻、硼、鋁、鎵、銦、鍺中的至少1者作為摻雜劑的矽膜中的至少任一種膜。 Thereby, the first semiconductor film and the second semiconductor film formed in the trench etc. become a film containing silicon and containing at least one of phosphorus, arsenic, antimony, boron, aluminum, gallium, indium, and germanium as a dopant At least any one of the silicon films of the agent.
在上述的成膜方法中,在上述第1半導體膜與上述第2半導體膜的介面包含鹵素,所述鹵素是上述蝕刻氣體中包含的鹵素。 In the above-mentioned film forming method, the interface between the first semiconductor film and the second semiconductor film contains a halogen, and the halogen is a halogen contained in the etching gas.
由此,在形成於溝槽等內的上述第1半導體膜及上述第2半導體膜的介面包含鹵素,所述鹵素是上述蝕刻氣體中包含的鹵素。 Thus, the interface between the first semiconductor film and the second semiconductor film formed in a trench or the like contains halogen, and the halogen is a halogen contained in the etching gas.
此外,本發明的一方式的成膜裝置具備真空槽、支撐台、等離子體產生源和控制部。 In addition, a film forming apparatus according to an aspect of the present invention includes a vacuum chamber, a support table, a plasma generation source, and a control unit.
上述真空槽能夠維持減壓狀態地構成。 The above-mentioned vacuum chamber can be configured to maintain a reduced pressure state.
上述支撐台可以載置基板。在基板上設置有溝槽或孔。溝槽或孔各自具有底部和側壁。 The above-mentioned support table can place a substrate. Grooves or holes are provided on the substrate. The trenches or holes each have a bottom and sidewalls.
上述等離子體產生源可以通過產生被導入上述真空槽內的包含矽的成膜氣體的第1等離子體而在上述底部及上述側壁形成包含矽的半導體膜。此外,等離子體產生源可以通過產生被導入上述真空槽內的包含鹵素的蝕刻氣體的第2等離子體,將形成於上述側壁的上述半導體膜選擇性除去。 The plasma generating source may generate a first plasma of a film forming gas including silicon introduced into the vacuum chamber to form a semiconductor film including silicon on the bottom and sidewalls. In addition, the plasma generation source may selectively remove the semiconductor film formed on the side wall by generating a second plasma of the halogen-containing etching gas introduced into the vacuum chamber.
上述控制部可以對上述第1等離子體的產生與上述第2等離子體的產生進行切換。 The control unit may switch the generation of the first plasma and the generation of the second plasma.
由此,對於形成於溝槽等內的半導體膜而言,不形成空隙地在溝槽等內形成膜。 Thus, for the semiconductor film formed in the trench or the like, the film is formed in the trench or the like without forming a void.
在上述的成膜裝置中,上述等離子體產生源也可以通過電感耦合方式的等離子體產生源而構成。 In the above-mentioned film forming apparatus, the above-mentioned plasma generation source may be constituted by an inductively coupled plasma generation source.
由此,在溝槽等的底部及側壁分別形成膜質不同的半導體膜。 As a result, semiconductor films with different film qualities are formed on the bottom and sidewalls of trenches, etc., respectively.
上述的成膜裝置也可以進一步具備第1氣體供給源和第2氣體供給源。上述第1氣體供給源也可以向上述真空槽內供給上述成膜氣體,並具有將上述成膜氣體噴出的第1供給口。上述第2氣體供給源也可以向上述真空槽內供給上述蝕刻氣體,並具有將上述蝕刻氣體噴出的第2供給口。上述第2供給口的位置也可以與上述第1供給口的位置不同。 The above-mentioned film forming apparatus may further include a first gas supply source and a second gas supply source. The first gas supply source may supply the film forming gas into the vacuum chamber, and may have a first supply port through which the film forming gas is ejected. The second gas supply source may supply the etching gas into the vacuum chamber, and may have a second supply port through which the etching gas is ejected. The position of the second supply port may be different from the position of the first supply port.
由此,在基板內均勻地形成半導體膜的膜厚。 As a result, the thickness of the semiconductor film is uniformly formed in the substrate.
根據本發明,對於形成於溝槽等內的膜而言,能夠不形成空隙地在溝槽等內埋入膜。 According to the present invention, for a film formed in a trench or the like, the film can be buried in the trench or the like without forming a void.
1:基板 1: substrate
1a:矽基板 1a: Silicon substrate
1b:矽氧化膜 1b: Silicon oxide film
1u:上表面 1u: upper surface
5:溝槽 5: groove
5c:角部 5c: corner
5b:底部 5b: bottom
5w:側壁 5w: side wall
10:真空槽 10: Vacuum tank
10p:等離子體形成空間 10p: Plasma formation space
11:底部 11: bottom
12:筒狀壁 12: Cylindrical wall
13:蓋板 13: cover
20:支撐台 20: Support table
21:容量 21: Capacity
30:等離子體產生源 30: Plasma generation source
31:高頻線圈 31: High frequency coil
32:高頻電源 32: High frequency power supply
33:整合電路 33: Integrated circuit
40、45:氣體供給源 40, 45: gas supply source
41、46:噴嘴 41, 46: nozzle
41h、46h:供給口 41h, 46h: supply port
42、47:氣體導入管 42, 47: gas inlet pipe
43、48:流量計 43, 48: Flowmeter
50:控制部 50: Control Department
70、70a、70b:半導體膜 70, 70a, 70b: semiconductor film
71a、71b、71c、71d、71e、72a、72b、73a、73b:膜 71a, 71b, 71c, 71d, 71e, 72a, 72b, 73a, 73b: film
100:成膜裝置 100: Film forming device
S10:步驟S10 S10: Step S10
S20:步驟S20 S20: Step S20
S30:步驟S30 S30: Step S30
α:長度 α: length
β:長度 β: length
圖1是適用於本實施方式的成膜方法的成膜裝置的概略構成圖。 FIG. 1 is a schematic configuration diagram of a film forming apparatus applied to the film forming method of this embodiment.
圖2是本實施方式的成膜方法的概略的流程圖。 Fig. 2 is a schematic flow chart of the film forming method of the present embodiment.
圖3的圖A及圖B是表示本實施方式的成膜方法的概略截面圖。 FIGS. A and B of FIG. 3 are schematic cross-sectional views showing the film forming method of the present embodiment.
圖4的圖A及圖B是表示本實施方式的成膜方法的概略截面圖。 FIGS. A and B of FIG. 4 are schematic cross-sectional views showing the film forming method of this embodiment.
圖5的圖A及圖B是表示本實施方式的成膜方法的概略截面圖。 FIGS. A and B of FIG. 5 are schematic cross-sectional views showing the film forming method of this embodiment.
圖6的圖A是表示在成膜工序後不進行乾式洗滌就轉移至利用氫等離子體的蝕刻工序時的蝕刻時間與膜厚的關係的概略座標圖。圖B是表示在成膜工序後進行乾式洗滌後轉移至利用氫等離子體的蝕刻工序時的蝕刻時間與膜厚的關係的概略座標圖。 Fig. 6A is a schematic graph showing the relationship between the etching time and the film thickness when shifting to the etching process using hydrogen plasma without performing dry cleaning after the film forming process. Fig. B is a schematic graph showing the relationship between the etching time and the film thickness when the film forming process is dry-washed and then transferred to the etching process using hydrogen plasma.
以下,參照附圖,對本發明的實施方式進行說明。各附圖中,有時導入XYZ軸座標。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, XYZ axis coordinates may be imported.
[成膜裝置] [Film Forming Device]
圖1是適用於本實施方式的成膜方法的成膜裝置的概略構成圖。 FIG. 1 is a schematic configuration diagram of a film forming apparatus applied to the film forming method of this embodiment.
圖1中所示的成膜裝置100具備真空槽10、支撐台20、等離子體產生源30、氣體供給源40、45和控制部50。成膜裝置100兼備通過等離子體CVD(Chemical Vapor Deposition)法在基板1形成膜(例如,半導體膜)的成膜單元、和通過乾式蝕刻將形成於基板1的膜除去的蝕刻單元。作為等離子體產生源30,作為一個例子示出電感耦合方式的等離子體源。作為本實施方式的等離子體源,不限於電感耦合方式的等離子體源。
The
真空槽10是能夠維持減壓狀態的容器。真空槽10具有底部11、筒狀壁12和蓋板(蓋)13。在真空槽10上,例如連接有渦輪分子泵等真空泵(未圖示)。真空槽10內的氣氛通過該真空泵被維持在規定的壓力。底部11例如將支撐台20包圍。筒狀壁12被設置在底部11上,例如將噴嘴41、46包圍。蓋板13被設置在筒狀壁12上,與支撐台20相對。底部11及蓋板13例如具有包含導電體的構成。筒狀壁12具有石英等透明絕緣材料。此外,在真空槽10中,設置有計測真空槽10內的壓力的壓力計(未圖示)。
The
在真空槽10的內部,設置有支撐基板1的支撐台20。基板1為例如半導體基板、絕緣基板、金屬基板等中的任一者。半導體基板為矽晶圓、表面形成有絕緣膜的矽晶圓等。絕緣膜為例如矽氧化物、矽氮化物、鋁氧化物等。晶圓直徑為例如150mm以上且300mm以下,例如設定為300mm。但是,晶圓直徑不限於該例子。此外,絕緣基板為玻璃基板、石英基板等。
Inside the
支撐台20例如具有包含導電體的構成。在支撐台20中,載置基板1的面可以是導電體,也可以是絕緣體。例如,在支撐台20中,也可以在載置基板1的面上設置靜電卡盤。當支撐台20包含絕緣體或靜電卡盤時,即使支撐台20被接地,也會在基板1與地面之間產生寄生電容21。此外,在支撐台20上,也可以按照能夠對基板1施加偏置電位的方式,連接直流電源或交流電源(高頻電源)。進而,在支撐台20中,也可以內置將基板1加熱至規定溫度的加熱源。
The support stand 20 has a structure including a conductor, for example. In the support table 20, the surface on which the
等離子體產生源30具有等離子體產生用的高頻線圈(天線)31、與高頻線圈31連接的高頻電源32和整合電路33。整合電路33被設置在高頻線圈31與高頻電源32之間。高頻線圈31例如在筒狀壁12的外周纏繞。高頻線圈31在筒狀壁12的外周纏繞的圈數並不限於圖示的數目。高頻電源32例如為RF電源。高頻電源32也可以為VHF電源。
The
等離子體產生源30不限於電感耦合方式的等離子體源,也可以是電子迴旋共振等離子體(Electron Cyclotron resonance Plasma)源、螺旋波激發等離子體(Helicon Wave Plasma)源等。
The
若向真空槽10內導入氣體,並向高頻線圈31輸入規定的電力,則在真空槽10內的等離子體形成空間10p中產生等離子體。該等離子體通過電感耦合方式而形成。由此,在等離子體形成空間10p中,產生雖為低壓但高密度的等離子體(以下,低壓高密度等離子體)。此外,通過在等離子體形成空間10p中產生高密度的等離子體,變得容易對基板1施加自偏置電位。進而,高頻線圈31由於設置在真空槽10的外側,所以不會與真空槽10內產生的等離子體直接接觸。因此,高頻線圈31的成分(例如,金屬)也不會由於被等離子體濺射而向基板1飛去。
When a gas is introduced into the
若向真空槽10內導入成膜氣體,並通過等離子體產生源30在等離子體形成空間10p中產生等離子體,則在基板1形成膜。該情況下,成膜裝置100作為在基板1形成膜的成膜裝置發揮功能。此外,由於該等離子體為低壓高密度等離子體,所以例如在基板1上設置有溝槽或孔(溝槽等)時,變得容易在其底部及側壁各自形成膜質不同的半導體膜。對於該理由,將在後面敘述。此外,溝槽等的長寬比例如為4以上。
When a film forming gas is introduced into the
另一方面,若向真空槽10內導入蝕刻氣體,並通過等離子體產生源30在等離子體形成空間10p中產生等離子體,則形成於基板1的膜被除去。該情況下,成膜裝置100作為將形成於基板1上的半導體膜除去的蝕刻裝置發揮功能。
On the other hand, if an etching gas is introduced into the
氣體供給源40向真空槽10內供給成膜氣體。氣體供給源40具有環狀的噴嘴41、氣體導入管42和流量計43。噴嘴41與支撐台20相對。在噴嘴41上,設置有將工藝氣體噴出的供給口41h。供給口41h例如與支撐台20相對。例如為了得到所期望的膜厚分佈,噴嘴41的直徑或供給口41h朝向支撐台20的角度可適當調整。氣體導入管42與噴嘴41連接。氣體導入管42例如設置於蓋板13。在氣體導入管42上,設置有調整工藝氣體的流量的流量計43。
The
作為成膜氣體,使用包含矽的氣體。由此,在基板1上例如形成包含矽的半導體膜。例如,作為成膜氣體,使用SiH4或Si2H6中的至少任一者。此外,也可以在SiH4或Si2H6中的至少任一者中混合不活潑氣體(Ar、He等)。此外,在SiH4或Si2H6中的至少任一者中也可以添加包含P(磷)或B(硼)的氣體。
As the film forming gas, a gas containing silicon is used. As a result, a semiconductor film containing silicon, for example, is formed on the
氣體供給源45向真空槽10內供給蝕刻氣體。氣體供給源40具有環狀的噴嘴46、氣體導入管47和流量計48。噴嘴46與支撐台20相對。在噴嘴46上,設置有將工藝氣體噴出的供給口46h。供給口46h例如與支撐台20相對。例
如為了得到所期望的蝕刻分佈,噴嘴46的直徑或供給口46h朝向支撐台20的角度可適當調整。
The
氣體導入管47與噴嘴46連接。氣體導入管47例如設置於蓋板13。在氣體導入管47上,設置有調整工藝氣體的流量的流量計48。
The
其中,噴嘴46的直徑小於噴嘴41的直徑。由此,供給口46h的位置與供給口41h的位置不同。例如,當與成膜氣體相比蝕刻氣體更容易吸附於真空槽10上時,優選噴嘴46的直徑小於噴嘴41的直徑地構成。由此,噴嘴46與噴嘴41相比遠離真空槽10,蝕刻氣體變得難以吸附於真空槽10。其結果是,可得到所期望的蝕刻分佈。
Among them, the diameter of the
作為蝕刻氣體,使用包含鹵素的氣體。例如,作為蝕刻氣體,使用包含氟的氣體或包含氯的氣體。由此,例如可以將形成於基板1上的包含矽的半導體膜進行蝕刻。例如,作為蝕刻氣體,使用NF3、NCl3及Cl2中的至少1者。此外,NF3、NCl3及Cl2的至少任一者也可以混合不活潑氣體(Ar、He等)。除此以外,作為蝕刻氣體,也可以使用CF4及SF6中的至少任一者。此外,NF3、NCl3及Cl2中的至少任一者中也可以添加CF4及SF6中的至少任一者。
As the etching gas, a gas containing halogen is used. For example, as the etching gas, a gas containing fluorine or a gas containing chlorine is used. Thereby, for example, the semiconductor film containing silicon formed on the
另外,氣體供給源並不限於兩個氣體供給源40、45,也可以進一步設置別的氣體供給源。此外,氣體供給源40、45也可以是噴淋板型的氣體供給源。此外,噴淋板也可以與氣體供給源40、45分開設置,例如也可以設置在筒狀壁12與底部11之間。進而,該噴淋板例如具有多個樹形排狀(日語: )結構的孔,能夠對基板1均勻地供給氣體。
In addition, the gas supply source is not limited to the two
控制部50能夠對使用成膜氣體的等離子體的產生與使用蝕刻氣體的等離子體的產生進行切換。控制部50通過CPU(Central Processing Unit,中央處理器)、RAM(Random Access Memory,隨機存取記憶體)、ROM(Read Only Memory,唯讀記憶體)等電腦中使用的硬體要素及必要的軟體來
實現。代替CPU或在其基礎上,也可以使用FPGA(Field Programmable Gate Array,現場可程式設計閘陣列)等PLD(Programmable Logic Device,可程式設計邏輯器件)、或者DSP(Digital Signal Processor,數位訊號處理器)等。
The
例如,控制部50在產生使用了成膜氣體的等離子體時將流量計43設定為接通狀態(此時,流量計48為斷開狀態)。由此,成膜氣體從噴嘴41被導入真空槽10內。然後,控制部50驅動高頻電源32,在真空槽10內產生使用了成膜氣體的等離子體(第1等離子體)。控制部50控制整合電路33,使等離子體穩定。此外,控制部50在產生使用了蝕刻氣體的等離子體時將流量計48設定為接通狀態(此時,流量計43為斷開狀態)。由此,蝕刻氣體從噴嘴46被導入真空槽10內。然後,控制部50驅動高頻電源32,在真空槽10內產生使用了蝕刻氣體的等離子體(第2等離子體)。
For example, the
在成膜裝置100中,通過對基板1交替地重複進行成膜工序和蝕刻工序,在形成於基板1的高長寬比的溝槽等內不形成空隙地形成半導體膜。
In the
由於近年的光刻技術中的微細化工藝的困難性、因微細化而產生漏電流的增大的半導體裝置的結構上的問題,如FinFET(Fin Field Effect transistor,鰭式場效應電晶體)那樣,嘗試半導體裝置的結構的重新研討。在這樣的狀況下,在半導體裝置的三維加工中,要求在微細化的溝槽等中埋入膜的技術。但是,對於被埋入微細化的溝槽等中的膜,由於升溫時的回流特性、蝕刻特性等的不同,狀況是難以與絕緣膜同樣地不產生空隙地形成。 Due to the difficulty of the miniaturization process in the recent photolithography technology and the structural problems of the semiconductor device that increase the leakage current due to miniaturization, such as FinFET (Fin Field Effect Transistor, fin field effect transistor), Attempt to re-examine the structure of the semiconductor device. Under such circumstances, in the three-dimensional processing of semiconductor devices, a technique of embedding a film in a miniaturized trench or the like is required. However, for the film buried in the miniaturized trench or the like, it is difficult to form without voids in the same way as the insulating film due to differences in reflow characteristics and etching characteristics at the time of temperature rise.
針對於此,本實施方式解決上述的狀況。以下說明本實施方式的成膜方法。 In response to this, the present embodiment solves the above-mentioned situation. Hereinafter, the film forming method of the present embodiment will be described.
[成膜方法] [Film forming method]
圖2是本實施方式的成膜方法的概略的流程圖。 Fig. 2 is a schematic flow chart of the film forming method of the present embodiment.
例如,在基板1中設置有高長寬比的溝槽或孔(溝槽等),通過在基板1的表面產生成膜氣體的高密度等離子體,從而在溝槽等的底部及側壁形成包含矽的半導體膜(第1半導體膜)(步驟S10)。
For example, the
接著,通過在基板1的表面產生蝕刻氣體的等離子體,形成於側壁的半導體膜被選擇性除去(步驟S20)。
Next, by generating plasma of an etching gas on the surface of the
接著,重複進行步驟S10和步驟S20。例如,重複在設置於基板1中的溝槽等的底部及側壁形成包含矽的半導體膜的工序、和形成於側壁的半導體膜被選擇性除去的工序(步驟S30)。例如,形成於溝槽等的側壁的半導體膜被選擇性除去,進而在下一成膜工序中在溝槽等的底部及側壁形成包含矽的半導體膜(第2半導體膜)的處理被重複2次以上。
Then, step S10 and step S20 are repeated. For example, the process of forming a semiconductor film containing silicon on the bottom and sidewalls of trenches etc. provided in the
根據這樣的成膜方法,不形成空隙地在溝槽等內形成半導體膜。以下,對圖2的流程更具體地進行說明。 According to such a film forming method, a semiconductor film is formed in a trench or the like without forming a void. Hereinafter, the flow of FIG. 2 will be described in more detail.
圖3的A~圖5的B是表示本實施方式的成膜方法的概略截面圖。 3A to 5B are schematic cross-sectional views showing the film forming method of this embodiment.
例如,以在設置於基板1中的溝槽內形成半導體膜的成膜工藝為例,對本實施方式的成膜方法進行說明。
For example, a film forming process of forming a semiconductor film in a trench provided in the
如圖3的A中所示的那樣,在基板1中設置有高長寬比的溝槽5。其中,“β”的長度(溝槽5的深度)設定為“α”的長度(溝槽5的底部5b的寬度)的4倍以上。此外,“α”的長度設定為數nm~數10nm。此外,作為一個例子,基板1設定為在矽基板1a形成有矽氧化膜(SiO2)1b的基板。
As shown in A of FIG. 3, a
接著,如圖3的B中所示的那樣,通過等離子體CVD在溝槽5內及基板1的上表面1u形成包含矽的半導體膜70a。例如,以Ar稀釋的SiH4氣體從噴嘴41被導入。作為成膜氣體,也可以使用Si2H6被Ar稀釋而得到的氣體。接著,通過高頻電源32向高頻線圈31輸入電力。在真空槽10內,在基板1的上表
面1u產生SiH4/Ar氣體的高密度等離子體(第1等離子體)。由此,在溝槽5的底部5b、溝槽5的側壁5w及基板1的上表面1u形成半導體膜70a(步驟S10)。
Next, as shown in B of FIG. 3, a
成膜條件的一個例子如下所述。 An example of film formation conditions is as follows.
基板直徑:300mm Substrate diameter: 300mm
成膜氣體:SiH4/Ar Film forming gas: SiH 4 /Ar
成膜時間:5分鐘以內 Film formation time: within 5 minutes
放電功率:300W以上且600W以下(13.56MHz) Discharge power: above 300W and below 600W (13.56MHz)
壓力:0.05Pa以上且1.0Pa以下 Pressure: 0.05Pa or more and 1.0Pa or less
基板溫度:室溫 Substrate temperature: room temperature
半導體膜70a例如具有形成於溝槽5的底部5b上的膜71a、形成於溝槽5的側壁5w的膜72a和形成於基板1的上表面1u上的膜73a。膜72a也形成於溝槽5的角部5c附近。即,膜72a包含與側壁5w相接的部分、和形成於與側壁5w相接的部分上且與膜73a相接的部分。此外,圖3的B中例示出在溝槽5內、膜72a不與膜71a相接的構成,但膜72a也可以在溝槽5內與膜71a相接。
The
在成膜工序中,按照溝槽5的上部不被半導體膜70a閉塞的方式調整成膜條件。例如,若成膜時間變得長於5分鐘,則有時從兩側壁5w的角部5c生長的膜72a彼此接觸,溝槽5的上部被膜72a被閉塞。由此,成膜時間被調整為5分鐘以內,優選設定為2分鐘。
In the film forming step, the film forming conditions are adjusted so that the upper portion of the
若通過低壓高密度等離子體在溝槽5內及基板1形成半導體膜70a,則半導體膜70a邊接受等離子體中的離子照射邊進行生長。該離子通過等離子體電勢與基板1的自偏置電位的電位差,例如相對於基板1垂直地入射。此時,成為膜71a的基底的底部5b及成為膜73a的基底的上表面1u與離子的入射方向正交。由此,膜71a及膜73a在底部5b上及上表面1u上邊接受離子的動能邊逐
漸生長。其結果是,膜71a及膜73a成為結晶性較好的膜。例如,膜71a及膜73a與膜72a相比,成為密度高、且緻密的膜。
If the
其中,上述的電位差越高則照射膜71a及膜73a的離子的能量越增加。例如,若放電功率變得小於300W,則有時離子的照射能量減少,膜71a及膜73a的結晶性下降。此外,若放電功率變得大於600W,則該能量變得過大,膜71a及膜73a變得容易被物理性蝕刻。由此,放電功率優選為300W以上且600W以下,優選為500W。
However, the higher the above-mentioned potential difference, the more the energy of the ions irradiating the
此外,若成膜中的壓力也小於0.05Pa,則有可能成膜氣體的量減少而放電變得不穩定。此外,若成膜中的壓力大於1.0Pa,則膜71a及膜73a的高低差被覆性變差。由此,壓力優選為0.05Pa以上且1.0Pa以下,優選0.1Pa。
In addition, if the pressure during film formation is also less than 0.05 Pa, the amount of film formation gas may decrease and discharge may become unstable. In addition, if the pressure during the film formation is greater than 1.0 Pa, the
另一方面,形成於溝槽5的側壁5w的膜72a在成膜中不具有基底。由此,膜72a與膜71a及膜73a相比難以接受離子的動能、或膜72a的一部分通過入射來的離子濺射膜71a等而形成,所以與膜71a、膜73a相比,膜72a的結晶性不好。由此,例如,膜72a與膜71a及膜73a相比,成為密度低、且不緻密的膜。例如,膜72a與膜71a及膜73a相比,成為不耐受氟的蝕刻的膜。例如,在使用包含氟的蝕刻氣體的情況下,膜72a的蝕刻速度與膜71a及膜73a的蝕刻速度相比快。
On the other hand, the
像這樣,在成膜工序中,形成膜71a、膜73a以及膜質與膜71a和膜73a不同的膜72a。
In this manner, in the film forming step, the
接著,如圖4的A中所示的那樣,通過反應性的乾式蝕刻(化學蝕刻),形成於溝槽5的側壁5w的膜72a被選擇性除去(步驟S20)。例如,NF3氣體從噴嘴46被導入。關於蝕刻氣體,也可以使用包含NF3、NCl3及Cl2中的至少1者的氣體。接著,通過高頻電源32向高頻線圈31輸入電力。在真空槽10內,在基板1的上表面1u產生NF3氣體的高密度等離子體(第2等離子體)。由
此,不耐受蝕刻用等離子體的蝕刻的膜72a被選擇性除去。例如,若膜72a中的矽與等離子體中的氟反應,則生成SiFx等,SiFx等通過真空泵從真空槽10被排氣。
Next, as shown in A of FIG. 4, the
蝕刻條件的一個例子如下所述。 An example of etching conditions is as follows.
基板直徑:300mm Substrate diameter: 300mm
蝕刻氣體:NF3 Etching gas: NF 3
蝕刻時間:5分鐘以內 Etching time: within 5 minutes
放電功率:500W(13.56MHz) Discharge power: 500W (13.56MHz)
壓力:1Pa Pressure: 1Pa
基板溫度:室溫 Substrate temperature: room temperature
在蝕刻工序中,按照膜72a被選擇性除去的方式調整蝕刻條件。例如,若蝕刻時間變得長於5分鐘,則有時膜71a及膜73a與氟進行反應而膜71a及膜73a也被除去。由此,蝕刻時間優選被調整為5分鐘以內,優選為20秒鐘。
In the etching process, the etching conditions are adjusted so that the
另外,在蝕刻工序中,例如,若使用利用Ar等離子體的物理蝕刻,則有可能膜71a也與膜72a同時被蝕刻,不優選。
In addition, in the etching process, if physical etching using Ar plasma is used, for example, the
接著,如圖4的B中所示的那樣,通過等離子體CVD在溝槽5內及膜73a形成包含矽的半導體膜70b。例如,在與半導體膜70a相同的條件下,在溝槽5內及膜73a形成半導體膜70b。
Next, as shown in B of FIG. 4, a
半導體膜70b例如具有形成於溝槽5內的膜71a上的膜71b、形成於溝槽5的側壁5w的膜72b、和形成於基板1的上表面1u的膜73b。膜72b包含與側壁5w相接的部分、和形成於與側壁5w相接的部分上且與膜73b相接的部分。此外,在溝槽5內,膜72b也可以與膜71b相接。此外,由於對膜71a進行了蝕刻處理,所以在膜71a與膜71b的介面有時殘存微量的氟。
The
在半導體膜70b中,膜72b與膜71b及膜73b相比,也成為密度低、且不緻密的膜。例如,膜72b成為與膜71b及膜73b相比不耐受氟的蝕刻的膜。
In the
接著,如圖5的A中所示的那樣,通過反應性的乾式蝕刻而形成於溝槽5的側壁5w的膜72b被選擇性除去。例如,膜72b在與除去膜72a的條件相同的條件下被選擇性除去。
Next, as shown in A of FIG. 5, the
接著,如圖5的B中所示的那樣,重複成膜工序(步驟S10)和蝕刻工序(步驟S20)(步驟S30)。重複的次數(本實施方式中,作為一個例子為5次)例如設定為2次以上。由此,在溝槽5內,形成膜71a、形成於膜71a上的膜71b、形成於膜71b上的膜71c、形成於膜71c上的膜71d和形成於膜71d上的膜71e。形成於基板1的上表面1u上的膜例如通過CMP(Chemical Mechanical Polishing,化學機械拋光)被除去。此外,在膜71a、膜71b、膜71c、膜71d及膜71e各自的介面有時殘存微量的氟。
Next, as shown in B of FIG. 5, the film forming process (step S10) and the etching process (step S20) are repeated (step S30). The number of repetitions (5 times as an example in this embodiment) is set to, for example, 2 times or more. Thus, in the
像這樣,重複進行在溝槽5的底部5b及側壁5w形成包含矽的半導體膜的工序、和形成於側壁5w上的半導體膜被選擇性除去的工序,在溝槽5內形成包含矽的半導體膜70(膜71a、71b、71c、71d、71e)。根據這樣的成膜方法,不形成空隙地在溝槽5內形成半導體膜70。此外,不限於溝槽5,在具有與溝槽5相同的長寬比的孔中,也不形成空隙地在孔內形成半導體膜70。
In this manner, the step of forming a semiconductor film containing silicon on the bottom 5b and sidewalls 5w of the
此外,也可以在成膜氣體中添加包含磷(P)、硼(B)、鍺(Ge)等的氣體而形成半導體膜70。例如,形成於溝槽5內的半導體膜70中的矽的組成比為50atom%以上,優選為90atom%以上,進一步優選為99atom%以上。即,作為半導體膜70,形成包含不可避免的雜質的矽膜(包含矽的膜)及包含磷(P)、砷(As)、銻(Sb)、硼(B)、鋁(Al)、鎵(Ga)、銦(In)、鍺(Ge)中的至少1者作為摻雜劑的矽膜中的至少任一者。其中,
“不可避免的雜質”是指不是有意導入的雜質,而是在原料氣體或製造工藝中必然地導入的雜質。
In addition, a gas containing phosphorus (P), boron (B), germanium (Ge), or the like may be added to the film forming gas to form the
此外,在蝕刻工序中,蝕刻等離子體的反應性越高,則圖3的B中所示的膜71a、73a例如越有可能容易受到來自蝕刻等離子體的損傷,或者膜72a的選擇比越無法充分取得。關於圖4的B中所示的膜71b、73b及膜72b也可以引起同樣的現象。
In addition, in the etching process, the higher the reactivity of the etching plasma, the more likely the
在引起這樣的現象的情況下,在蝕刻工序中,也可以使用H2(氫)氣來代替鹵素系氣體。使用H2氣體的蝕刻條件的一個例子如下所述。 When such a phenomenon occurs, H 2 (hydrogen) gas may be used in place of the halogen-based gas in the etching process. An example of etching conditions using H 2 gas is as follows.
基板直徑:300mm Substrate diameter: 300mm
蝕刻時間:7分鐘以內 Etching time: within 7 minutes
放電功率:1000W(13.56MHz)以下 Discharge power: below 1000W (13.56MHz)
壓力:5Pa Pressure: 5Pa
基板溫度:室溫 Substrate temperature: room temperature
例如,若在基板1的上表面1u上產生H2氣體的等離子體,則與膜71a、73a相比不耐蝕刻的膜72a與氫等離子體反應,膜72a被選擇性除去。該情況下,膜72a中包含的Si變化成SiHx等,SiHx通過真空泵從真空槽10等被排氣。之後,重複成膜工序和利用H2氣體的蝕刻工序,在溝槽5內形成半導體膜70。
For example, if plasma of H 2 gas is generated on the
進而,在本實施方式中,也可以導入乾式洗滌工序,其在成膜工序後對真空槽10內進行乾式洗滌。
Furthermore, in the present embodiment, a dry washing step may be introduced in which the inside of the
例如,在成膜工序中,除了基板1以外,半導體膜還附著在真空槽10的底部11、筒狀壁12、蓋板13、支撐台20及噴嘴41、46等。之後,若在蝕刻工序中氫等離子體被暴露在附著於真空槽10的底部11、筒狀壁12、蓋板13、支撐台20及噴嘴41、46等的半導體膜,則有時半導體膜與氫等離子體發生反
應,SiHx等從真空槽10的底部11、筒狀壁12、蓋板13、支撐台20及噴嘴41、46等放出。
For example, in the film forming process, in addition to the
例如,若該SiHx在等離子體形成空間10p中飛行,通過蝕刻等離子體而發生分解,則SiHx其自身成為膜形成用的氣體,再次在基板1形成半導體膜。但是,在成膜工序後,通過將附著於真空槽10的底部11、筒狀壁12、蓋板13、支撐台20及噴嘴41、46等的半導體膜以乾式洗滌工序除去,半導體膜向基板1上的再附著得到抑制。
For example, if the SiH x flies in the
以下,對在成膜工序後不進行乾式洗滌就轉移至利用氫等離子體的蝕刻工序時和在成膜工序後進行乾式洗滌後轉移至利用氫等離子體的蝕刻工序時的蝕刻後的狀態進行說明。 Hereinafter, the state after the etching when the film formation process is transferred to the etching process using hydrogen plasma without dry cleaning and the dry cleaning process after the film formation process is transferred to the etching process using hydrogen plasma will be described. .
圖6的A是表示在成膜工序後不進行乾式洗滌就轉移至利用氫等離子體的蝕刻工序時的蝕刻時間與膜厚的關係的概略座標圖。圖6的B是表示在成膜工序後進行乾式洗滌後轉移至利用氫等離子體的蝕刻工序時的蝕刻時間與膜厚的關係的概略座標圖。 A of FIG. 6 is a schematic graph showing the relationship between the etching time and the film thickness when shifting to the etching process using hydrogen plasma without performing dry cleaning after the film forming process. B of FIG. 6 is a schematic graph showing the relationship between the etching time and the film thickness when dry cleaning is performed after the film forming process and then transferred to the etching process using hydrogen plasma.
在圖6的A、B中,橫軸為蝕刻時間,縱軸為半導體膜的膜厚。圖6的A、B中示出重複成膜工序和蝕刻工序的迴圈的每1個迴圈的結果。例如,蝕刻時間為0秒時的膜厚相當於在1次成膜工序結束後形成於基板1的上表面1u或溝槽5的底部5b的半導體膜的膜厚。該膜厚為約5nm。
In A and B of FIG. 6, the horizontal axis represents the etching time, and the vertical axis represents the film thickness of the semiconductor film. A and B of FIG. 6 show the results of repeating the film forming process and the etching process for each cycle. For example, the film thickness when the etching time is 0 seconds corresponds to the film thickness of the semiconductor film formed on the
乾式洗滌條件的一個例子如下所述。 An example of dry washing conditions is as follows.
乾式洗滌氣體:H2 Dry scrubbing gas: H 2
乾式洗滌時間:7分鐘以內 Dry washing time: within 7 minutes
放電功率:1000W(13.56MHz)以下 Discharge power: below 1000W (13.56MHz)
壓力:5Pa Pressure: 5Pa
在乾式洗滌工序中,可以在將結束成膜處理的基板1載置於支撐台20上的狀態下對真空槽10內進行洗滌,也可以將基板1移送至與真空槽10不同的真空槽中後對真空槽10內進行洗滌。但是,在乾式洗滌工序中將基板1載置於支撐台20上的情況下,基板1以百葉窗等覆蓋。乾式洗滌工序可以在每1次成膜工序結束時實施,也可以在多次成膜工序結束時每次實施。
In the dry cleaning process, the inside of the
首先,通過圖6的A,對在成膜工序後不進行乾式洗滌就轉移至利用氫等離子體的蝕刻工序時的例子進行說明。 First, referring to A of FIG. 6, an example in which the film formation step is followed by a dry cleaning and the transition to the etching step using hydrogen plasma will be described.
該情況下,若以100W的放電功率進行100秒鐘的蝕刻處理,則膜厚從約5nm減少至約4nm。接著,若以100W的放電功率進行300秒鐘的蝕刻處理,則膜厚變成約2.5nm。像這樣,在放電功率為100W的蝕刻處理中,蝕刻時間越增加,則膜厚越減少。即,在100W左右的放電功率時,蝕刻量可以通過蝕刻時間來控制。 In this case, if the etching process is performed for 100 seconds with a discharge power of 100 W, the film thickness is reduced from about 5 nm to about 4 nm. Next, if the etching process is performed for 300 seconds with a discharge power of 100 W, the film thickness becomes approximately 2.5 nm. In this way, in the etching process with a discharge power of 100 W, the more the etching time increases, the more the film thickness decreases. That is, at a discharge power of about 100W, the etching amount can be controlled by the etching time.
若使放電功率從100W增加至200W,則通過300秒鐘的蝕刻處理膜厚減少至約2nm。 If the discharge power is increased from 100W to 200W, the film thickness will be reduced to about 2nm by the etching treatment for 300 seconds.
但是,在400W的放電功率時,通過100秒鐘的蝕刻處理膜厚上升至約12nm,通過300秒鐘的蝕刻處理膜厚減少至約2nm。關於該膜厚暫且變厚的現象,放電功率越大則越顯著。此外,在1000W的放電功率時,通過100秒鐘的蝕刻處理膜厚上升至約28nm,通過300秒鐘的蝕刻處理,膜厚減少至約3.5nm。 However, at a discharge power of 400 W, the film thickness increased to about 12 nm by the etching treatment for 100 seconds, and the film thickness was reduced to about 2 nm by the etching treatment for 300 seconds. Regarding the temporary increase in the film thickness, the greater the discharge power, the more significant it is. In addition, at a discharge power of 1000 W, the film thickness increased to about 28 nm by the etching treatment for 100 seconds, and the film thickness was reduced to about 3.5 nm by the etching treatment for 300 seconds.
像這樣,若以放電功率大於200W的功率進行蝕刻處理,則存在在蝕刻時間為100秒左右時半導體膜的膜厚與當初的膜厚相比上升的傾向。認為這是由於,在成膜工序後不進行乾式洗滌就轉移至利用氫等離子體的蝕刻工序時,附著於真空槽10的底部11、筒狀壁12、蓋板13、支撐台20及噴嘴41、46等的半導體膜通過氫等離子體而發生分解,再次沉積在基板1上。
In this way, if the etching process is performed with a discharge power greater than 200 W, the film thickness of the semiconductor film tends to increase compared to the original film thickness when the etching time is about 100 seconds. It is considered that this is due to the adhesion to the bottom 11 of the
像這樣,在採用在成膜工序後不進行乾式洗滌就轉移至利用氫等離子體的蝕刻工序的工藝的情況下,放電功率為低功率(例如,200W以下)時,雖然可以通過成膜時間和蝕刻時間來控制半導體膜的膜厚,但是若增加放電功率(例如,大於200W),則從蝕刻開始,產生半導體膜的膜厚暫且增加的現象,變得難以通過成膜時間和蝕刻時間來控制半導體膜的膜厚。 In this way, in the case of adopting the process of shifting to the etching process using hydrogen plasma without performing dry cleaning after the film formation process, when the discharge power is low (for example, 200W or less), although the film formation time and The film thickness of the semiconductor film is controlled by the etching time, but if the discharge power is increased (for example, greater than 200W), the film thickness of the semiconductor film will temporarily increase from the beginning of the etching, and it becomes difficult to control the film formation time and the etching time The thickness of the semiconductor film.
另一方面,圖6的B中示出在成膜工序後進行乾式洗滌後轉移至蝕刻工序時的結果。在該情況下,在蝕刻工序前,附著於真空槽10的底部11、筒狀壁12、蓋板13、支撐台20及噴嘴41、46等上的半導體膜被除去。
On the other hand, B of FIG. 6 shows the result when the film formation process is followed by dry washing and then the etching process is transferred. In this case, before the etching process, the semiconductor film adhering to the bottom 11 of the
在該工藝中,在100W的放電功率下的蝕刻處理中,在蝕刻時間為30秒鐘時半導體膜的膜厚從約5nm減少至約4nm,在蝕刻時間為60秒後膜厚變成約3nm,在蝕刻時間為75秒後時,膜厚進一步減少。 In this process, in the etching process at a discharge power of 100W, the film thickness of the semiconductor film is reduced from about 5nm to about 4nm when the etching time is 30 seconds, and the film thickness becomes about 3nm after the etching time is 60 seconds. After the etching time was 75 seconds, the film thickness was further reduced.
進而,在200W的放電功率時,蝕刻時間為30秒時膜厚變成約2.5nm,蝕刻時間為60秒時膜厚變成約0.5nm。在400W的放電功率時,蝕刻時間為30秒時膜厚變成約2.5nm,蝕刻時間為60秒時膜厚變得薄於1nm。在1000W的放電功率時,蝕刻時間為30秒時膜厚變得薄於1nm。 Furthermore, at a discharge power of 200 W, the film thickness becomes about 2.5 nm when the etching time is 30 seconds, and the film thickness becomes about 0.5 nm when the etching time is 60 seconds. At a discharge power of 400 W, the film thickness becomes approximately 2.5 nm when the etching time is 30 seconds, and the film thickness becomes thinner than 1 nm when the etching time is 60 seconds. At a discharge power of 1000 W, the film thickness becomes thinner than 1 nm when the etching time is 30 seconds.
像這樣,通過在成膜工序後實施乾式洗滌,蝕刻工序中的半導體膜的膜厚暫且增加的現象得到抑制。即,認為由於在蝕刻處理前附著於真空槽10的底部11、筒狀壁12、蓋板13、支撐台20及噴嘴41、46等的半導體膜通過乾式洗滌被除去,所以半導體膜在基板1上再沉積的現象得到抑制。
In this way, by performing dry cleaning after the film formation process, the phenomenon that the film thickness of the semiconductor film in the etching process temporarily increases is suppressed. That is, it is considered that the semiconductor film attached to the bottom 11 of the
像這樣,通過採用在成膜工序後進行乾式洗滌後轉移至蝕刻工序的工藝,可通過成膜時間和蝕刻時間而高精度地控制半導體膜的膜厚。 In this way, by adopting a process of performing dry cleaning after the film forming process and then transferring to the etching process, the film thickness of the semiconductor film can be controlled with high accuracy based on the film forming time and the etching time.
此外,為了提高形成於基板1的上表面1u及溝槽5的底部5b的膜的表面的平坦性,在蝕刻工序中,也可以對支撐台20施加偏置電位。由此,在蝕刻時,例如相對於膜表面的離子轟擊效應起作用,膜表面的平坦性提高。但
是,若偏置電位變得過高,則離子轟擊效應變得過量,膜通過離子照射而從基板1的上表面1u及溝槽5的底部5b被除去。施加於支撐台20的偏置電位被調整為不易引起膜厚減少而膜表面的平坦性提高的程度。
In addition, in order to improve the surface flatness of the film formed on the
以上,對本發明的實施方式進行了說明,但本發明並不僅限定於上述的實施方式,當然可以加以各種變更。 As mentioned above, although the embodiment of this invention was described, this invention is not limited to the above-mentioned embodiment, of course, various changes can be added.
S10:步驟S10 S10: Step S10
S20:步驟S20 S20: Step S20
S30:步驟S30 S30: Step S30
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