JP2013243271A - Dry etching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dry etching method capable of forming a pattern with a coarse/dense difference of a predetermined setting value, in forming a pattern including a coarse pattern region and a dense pattern region using a hard mask.SOLUTION: A dry etching method for forming a pattern having a dense part and a coarse part in a film 205 to be treated comprises: a first step (B), (C), (D) of forming a pattern in which a size of the dense part is a predetermined size and a size of the coarse part is larger than a predetermined size, on a mask; and a second step (E) of reducing the size of the coarse part while maintaining the size of the dense part after the first step to form a coarse/dense difference of a predetermined setting value.

Description

  The present invention relates to a dry etching method using plasma.

  In recent years, with the progress of high integration accompanying the increase in processing speed of semiconductor devices, even finer control of density difference is required in gate wiring processing technology. In general, in order to manufacture a semiconductor device, an etching process for forming a fine pattern with a pattern dimension based on a predetermined design value is performed on several layers stacked on a semiconductor substrate.

  In this etching process, for example, when the patterned mask layer is a photoresist, the photoresist pattern is reduced by dry etching before the layer to be etched is processed, and the dense pattern is processed into a predetermined pattern dimension. In the case where the mask layer is a hard mask, for example, an etching process for forming a fine pattern is performed on a film laminated on the hard mask layer, and the film is used as a mask layer. Processing for selectively etching a mask to form a dense pattern with a predetermined pattern dimension is performed (Patent Document 2).

JP-A-9-237777 JP 2007-234870 A

  However, in recent years when pattern miniaturization has further progressed, the hard mask layer processing method is constituted by, for example, a memory cell region having a dense pattern with a fine interval such that the space width of the dense pattern is 20 nm or less and a sparse pattern. When processing the hard mask layer of a semiconductor device to be processed, the dimensional variation of the sparse pattern is large relative to the dimensional variation of the dense pattern only by adjusting the etching conditions of the hard mask layer, and the control of the sparse / dense difference by the predetermined sparse / dense pattern size This tendency becomes more pronounced as the space width of the dense pattern becomes narrower.

  An object of the present invention is to provide a dry etching method capable of forming a pattern with a predetermined set value sparse / dense difference when a pattern including a sparse pattern region and a dense pattern region is formed using a hard mask.

  As an embodiment for achieving the above object, in a dry etching method for plasma-etching a film to be processed using a mask to form a pattern having a dense portion and a sparse portion in the film to be processed, A first step of forming a pattern on the mask, the dimension of which is a predetermined dimension, and the dimension of the sparse portion is larger than the predetermined dimension, and the dimension of the dense portion after the first step is maintained. However, the second step of reducing the size of the sparse part and setting the density difference, which is the difference between the pattern size of the dense part and the pattern size of the sparse part, as a predetermined set value density difference, A dry etching method characterized by the above.

  Further, in the dry etching method for forming a pattern having a dense part and a sparse part in the film to be processed, the film to be processed and the film to be processed are formed on the film to be processed, and the dense part has a predetermined dimension, A step of preparing a substrate on which a mask having a pattern in which the dimension of the sparse part is larger than a predetermined dimension is prepared; and the dimension of the sparse part is reduced while maintaining the dimension of the dense part. And a step of setting a density difference, which is a difference between a pattern size of the dense portion and a pattern size of the sparse portion, to a predetermined set value density difference, and the film to be processed using the mask after the second step. A dry etching method comprising: a step of etching.

  Further, a film to be processed, a fourth film, a third film, and a second film formed by sequentially laminating on the film to be processed, and a dense portion and a sparse portion formed on the second film. A step of preparing a substrate including a first film having a pattern having a pattern, and using the first film as a mask, the dimension of the dense part is a predetermined dimension, and the dimension of the sparse part is larger than the predetermined dimension. Forming a pattern having a larger dimension on the second film, transferring the pattern formed on the second film to the third film, and transferring the pattern to the third film. The step of transferring the pattern to the fourth film, and then reducing the dimension of the sparse part while maintaining the dimension of the dense part transferred to the fourth film. A step of setting the density difference, which is a difference between the dimension and the pattern size of the sparse part, to a predetermined set value density difference, and then The fourth film as a mask, a dry etching method characterized by etching the target film.

  ADVANTAGE OF THE INVENTION According to this invention, when forming the pattern containing a sparse pattern area | region and a dense pattern area | region using a hard mask, the dry etching method which can form a pattern with a predetermined setting value sparse / dense difference can be provided.

1 is a schematic overall configuration cross-sectional view showing an example of a plasma etching apparatus used when performing a dry etching method according to an embodiment of the present invention. It is a schematic sectional drawing which shows the structure of the semiconductor substrate for demonstrating the dry etching method based on the Example of this invention, (A) is an initial state, (B) is the state after a SiON layer etching process, (C) is The state after the polysilicon layer etching process, (D) shows the state after the hard mask layer etching process, and (E) shows the state after the hard mask pattern reduction process. By O ₂ gas flow rate of SiON etching condition is a graph showing the relationship between the pattern dimensions and dimensional difference in density after the hard mask layer etching process. It is a graph which shows the relationship between the process time in a reduction process, the pattern dimension of a hard mask layer after a reduction process, and a dimensional density difference.

As a result of examining the above-mentioned problems, the inventors have found that a semiconductor device having a structure including a hard mask layer and a hard mask layer processing film on a semiconductor substrate has a structure including polysilicon, for processing a hard mask layer. Etching is performed while adjusting the size of the dense / dense pattern of the laminated mask layer, and further reduction processing is performed on the hard mask pattern formed on the hard mask layer processed using the mask layer as a mask. In addition, it has been thought that a fine hard mask pattern capable of processing an etching target film with a predetermined density difference can be formed.
Hereinafter, the embodiment will be described in detail.

  Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows an example of a plasma etching apparatus used when performing a dry etching method according to an embodiment of the present invention. By installing and sealing a shower plate 104 (for example, made of quartz) and a dielectric window 105 (for example, made of quartz) for introducing a processing gas into the vacuum container 101 on the upper part of the vacuum vessel 101 whose upper part is opened. A processing chamber 106 is formed. A gas supply device 107 for flowing a processing gas is connected to the shower plate 104. Further, a vacuum exhaust device (not shown) is connected to the vacuum container 101 via a vacuum exhaust port 108.

  In order to transmit power for generating plasma to the processing chamber 106, a waveguide 109 for transmitting electromagnetic waves is provided above the dielectric window 105. The electromagnetic wave (plasma generating high frequency) transmitted to the waveguide 109 is oscillated from the electromagnetic wave generating power source 103. The frequency of the electromagnetic wave is not particularly limited, but in this embodiment, a 2.45 GHz microwave (high frequency for plasma generation) is used. A magnetic field generating coil 110 that forms a magnetic field is provided on the outer periphery of the processing chamber 106, and power (microwave power) oscillated from the electromagnetic wave generating power source 103 is interacted with the formed magnetic field, High density plasma is generated in the processing chamber 106.

  A wafer mounting electrode 102 is provided below the vacuum vessel 101 so as to face the shower plate 104. The wafer mounting electrode 102 is coated with a sprayed film (not shown) on the electrode surface, and a DC power supply 115 is connected through a high frequency filter 114. Further, a high frequency power source 113 which is a high frequency power source for bias is connected to the wafer mounting electrode 102 via a matching circuit 112. A temperature controller (not shown) is also connected to the wafer mounting electrode 102.

  The wafer 111 which is a sample transported into the processing chamber 106 is adsorbed onto the wafer mounting electrode 102 and the temperature is adjusted by the electrostatic force of the DC voltage applied from the DC power supply 115. Next, after a predetermined processing gas is supplied by the gas supply device 107, the inside of the vacuum vessel 101 is set to a predetermined pressure, and then plasma is generated in the processing chamber 106 by supplying microwave power. By applying a high frequency power (RF bias power) from a high frequency power source 113 connected to the wafer mounting electrode 102, ions are attracted from the plasma to the wafer, and the wafer 111 is plasma processed.

  As the plasma etching apparatus, a microwave plasma etching apparatus, an inductively coupled plasma etching apparatus, a helicon wave plasma etching apparatus, a two-frequency excitation parallel plate plasma etching apparatus, or the like is employed.

  FIG. 2 is a diagram for explaining a method of manufacturing a semiconductor device including the dry etching method according to the present embodiment. 2A shows a partial cross-sectional structure of the semiconductor substrate used in this embodiment, and FIG. 2B shows a structure after the processing step of the SiON layer 202 by the patterned polysilicon mask 201. FIG. C) shows the structure after the processing step of the polysilicon layer 203 by the patterned SiON mask 202, and FIG. 2D shows the structure after the processing step of the hard mask layer 204 by the patterned polysilicon mask. FIG. 2E shows the structure after the processing step by the reduction processing of the hard mask pattern 204 after processing.

  The semiconductor substrate shown in FIG. 2A includes a polysilicon film 205 as a layer to be etched (film to be processed) and a hard mask layer 204 on a silicon substrate having a diameter of 12 inches, and further on the hard mask layer 204. A polysilicon layer 203 for processing the hard mask layer 204 and a SiON layer 202 are sequentially formed, and a patterned polysilicon mask 201 is provided. Here, the hard mask layer 204 is a silicon oxide film (TEOS film) formed using, for example, TEOS (Tetra Ethyl Ortho Silicate) as a raw material, and is processed by the mask 201 using the patterned polysilicon 201 as a mask. It is selectively processed using the SiON layer 202 and the polysilicon layer 203 as a mask. A layer to be etched located under the hard mask layer 204, for example, the polysilicon film 205 can be selectively processed using the patterned hard mask layer 204.

  First, a processing method for forming a hard mask pattern on a semiconductor substrate used in this embodiment will be described with reference to FIG. Table 1 shows the dry etching conditions during the initial processing.

FIG. 2B is a schematic cross-sectional view of the semiconductor substrate when the SiON layer 202 is etched. The SiON layer 202 forms a SiON mask pattern 202 by etching using the polysilicon 201 patterned in advance as a mask. As an etching process condition, for example, a gas mixture of CHF ₃ gas 180 ccm and O ₂ gas 20 ccm is used, the processing pressure is set to 0.8 Pa, and the RF bias power 130 W is applied to the plasma generated with the microwave power 600 W to perform the etching process. (Step 1 in Table 1). It is desirable that the etching process conditions of the SiON layer 202 used here have a pattern formed without excessive reduction of the SiON film 202. The etching process of the SiON layer 202 ends when the surface of the underlying polysilicon layer 203 is detected.

Next, as shown in FIG. 2C, the polysilicon layer 203 is selectively etched using the SiON patterned by the etching process of the SiON layer 202 as a mask. As an etching process condition, for example, a gas in which HBr gas is used as a main gas and mixed with O ₂ gas having a flow rate of about 2% of the HBr gas flow rate is used, the process pressure is set to 0.8 Pa, and the microwave power is 900 W. Etching is performed by applying an RF bias power of 60 W to the plasma (step 2 in Table 1). The etching conditions of the polysilicon layer 203 used here are desirably processed while suppressing the lateral etching of the polysilicon layer 203 and maintaining the pattern dimensions formed by the SiON mask 202. The etching process of the polysilicon layer 203 ends when the surface of the hard mask layer 204 underneath is detected.

Next, as shown in FIG. 2D, the hard mask layer 204 is processed by selectively etching the hard mask layer 204 using the polysilicon patterned by the etching process of the polysilicon layer 203 as a mask. To form a hard mask pattern. Etching conditions include, for example, C ₄ F ₈ gas and a mixed gas of Ar gas and He gas, a processing pressure of 1.4 Pa, and an RF bias power of 450 W applied to plasma generated at a microwave power of 400 W. Etching is performed (step 3 in Table 1). Note that the etching conditions of the hard mask layer 204 used here are the same as those for the mask in which the pattern is formed by the etching process of the SiON layer 202 and the polysilicon layer 203 shown in FIG. 2B and FIG. This is an optimized condition. The etching process of the hard mask layer 204 ends when the surface of the polysilicon layer 205, which is the material to be etched below, is detected.

  As described above, when the etching process shown in FIGS. 2B, 2C, and 2D results in a predetermined processing shape, the etching process is terminated. The mask pattern 204 was measured for sparse and dense pattern dimensions and sparse and dense differences (sparse pattern dimension−dense pattern dimension). As a result, for the dense pattern size of 22 nm and the density difference of 104 nm, the measured values after the etching process are the dense pattern size of 24 nm, the sparse pattern size of 137 nm, and the density difference of 113 nm. The difference from the set value was +2 nm for the dense pattern and +9 nm for the density difference.

  Here, in order to process into a predetermined set dimension, in the etching process of step 1 to step 3 in Table 1, first, with respect to the SiON layer 202 etching process which is step 1, the pattern dimension by adjusting the process condition and the density difference are adjusted. Adjustments were made.

The etching process conditions of the SiON layer 202 are composed of a mixed gas of CHF ₃ gas and O ₂ gas as shown in Step 1 of Table 1, and this etching process is performed between the oxygen gas flow rate and the pattern size and density difference. As can be seen from FIG. 3 showing the relationship, the dense pattern, the sparse pattern, and the sparse / dense difference are reduced as the O ₂ flow rate increases. When the O ₂ flow rate is increased from 20 ccm, which is the initial condition, to 30 ccm, the dense pattern size is reduced to 22 nm and 2 nm compared to 24 nm when processing is performed at the O ₂ flow rate of 20 ccm, and is narrowed to a predetermined set size. You can see that In addition, the density difference (sparse pattern dimension−dense pattern dimension) at this time is 109 nm by narrowing the dimension of the sparse pattern, and the difference is reduced to +5 nm with respect to the set density difference of 104 nm. According to the tendency of the O ₂ flow rate dependency of FIG 3, by a further increase in flow rate, although density difference is likely to be realized a predetermined setting value, a previously set value 22nm dimension of the dense pattern with O ₂ flow 30ccm It has been realized and no further increase is required. From the above, in the etching process of the SiON layer 202, the density difference is adjusted in the range shown in the graph of FIG. 3, and in particular, a processing method for finely adjusting the size of the dense pattern in the range of about 1 nm, In the present embodiment, this is the first step as one of the methods for forming a hard mask pattern with a predetermined pattern size and density difference. In the adjustment of the etching process of the SiON layer 202, the etching process conditions for the polysilicon layer 203 and the hard mask layer 204, which are formed in the lower layer, are not changed. Was used to form a hard mask pattern, and pattern dimensions were measured for the formed hard mask pattern.

  As the next method, there is an etching process (step 2 in Table 1) of the polysilicon layer 203 shown in FIG. 2C. The lateral direction of the polysilicon layer 203 with respect to the patterned SiON mask 202 is shown. It is desirable to process while maintaining the pattern dimensions formed by the SiON mask 202 with the etching conditions suppressed, and since the processing conditions have already been optimized, in this embodiment, the etching process for adjusting the density difference Is not adjusted. In addition, in the etching process (step 3 in Table 1) of the hard mask layer 204 in FIG. Since the dimensional variation is large and pattern formation at a predetermined set density difference is more difficult, the etching process conditions are not changed as in the etching process of the polysilicon layer 203 in Step 2 of Table 1, and the graph of FIG. As shown, the processing conditions used for pattern formation with a dense pattern size of 24 nm, a sparse pattern size of 137 nm, and a density difference of 113 nm were used.

  As described above, in the first step of the dry etching method according to the present embodiment, as can be seen from the graph of FIG. 3, by adjusting the etching process conditions of the SiON layer 202, the dimension of the dense pattern is a predetermined set dimension. Although it can be processed to 22 nm, for the difference in density, for example, a processing method by an etching process that reduces the size of the sparse pattern while maintaining the size of the dense pattern is required.

  Therefore, in addition to the hard mask 204 patterned in advance through the adjustment of the first step of the dry etching method according to the present embodiment, the above-described processing (second step) capable of adjusting the density difference is added. Thus, even if there is a deviation from each predetermined set value in the first step, an example of an etching processing method capable of correcting this deviation and forming a pattern according to the predetermined set value will be described. . Table 2 shows dry etching conditions including the first step and the second step.

Etching in which the polysilicon 201 patterned in advance is used as a mask, and the SiON layer 202 underneath the dense pattern size after the hard mask formation is 22 nm, which is a predetermined set size as shown in the graph of FIG. A SiON mask pattern is formed by processing with a mixed gas having a processing condition, for example, a CHF ₃ gas flow rate of 180 ccm and an O ₂ gas flow rate of 30 ccm (step 1 in Table 2). Further, the patterned SiON layer 202 is used as a mask, and the polysilicon layer 203 (Step 2 in Table 2) and the hard mask layer 204 are sequentially etched to form a pattern of the hard mask layer 204 ( Step 3) in Table 2.

Next, an etching process for reducing the sparse pattern is performed on the formed hard mask pattern 204 (step 4 in Table 2). As this etching processing condition, for example, a mixed gas of CHF ₃ gas 180 ccm and SF ₆ gas 30 ccm is used, the processing pressure is 1.6 Pa, and RF bias power 20 W is applied to plasma generated with microwave power 1000 W to perform etching. Process. Here, each dimension of the sparse / dense pattern and the sparse / dense difference depend on the reduction processing time, as can be seen from the graph of FIG. 4 showing the relationship between the pattern size and the sparse / difference difference with respect to the reduction processing time. By reducing the size of the sparse pattern formed by the above, the density difference (sparse pattern size−dense pattern size) is reduced. Further, it can be seen that in the reduction process, the size of the dense pattern is hardly reduced. The reduction of the sparse pattern size by the reduction process further reduces the sparse / dense difference by performing processing using the etching process conditions different from those in the first process after the pattern formation of the hard mask 204 in the first process. Therefore, it is used as one of processing methods for realizing a predetermined set value. Therefore, in order to adjust each of the sparse and dense pattern dimensions and the sparse / dense pattern to a predetermined set value, it is desirable to perform the process in at least two steps, and this step is performed as the second step.

  As a result, in this embodiment comprising the first step and the second step, in the adjustment of the first step, the process up to the formation of the hard mask pattern 204 under the processing conditions of a dense pattern size of 22 nm, a sparse pattern size of 131 nm, and a density difference of 109 nm. The processed hard mask 204 is subjected to the reduction process of the second step for 10 s, and the sparse pattern size is reduced to 126 nm while maintaining the dense pattern size of 22 nm. It was possible to realize a dense pattern size of 22 nm and a density difference of 104 nm, which were predetermined set values. After that, when the film to be processed was etched using this hard mask, a dense pattern having a predetermined set value density difference and a predetermined dimension could be formed on the film to be processed. The processed film to be processed can be used as a gate electrode, for example. This dry etching method is particularly effective for a fine pattern having a dense pattern dimension of 25 nm or less.

  In this embodiment, the control of the density difference is further improved by performing the processing in the first step and the second step, but when the predetermined pattern size and the density difference are reached in the processing in the first step, Processing may be terminated in the first step.

  The etching conditions in this example are conditions optimized for the structure of the semiconductor substrate shown in FIG. 2A. The etching process of the SiON layer 202, the polysilicon layer 203, and the hard mask layer 204, The method for reducing the size of the hard mask pattern 204, which is a two-step process, is not limited to the etching process conditions of the embodiment. Further, in this embodiment, the method of processing the fine pattern by forming the hard mask pattern to a predetermined set value using polysilicon as the etching layer has been described. For the material of the etching layer, for example, a silicon substrate, The present invention can also be applied to processing a fine pattern such as tungsten (W), tungsten silicide (WSi), titanium nitride (TiN), etc., and is not limited to the processing of polysilicon in this embodiment. In this case, since the etching speed and the processing speed by the reduction process are different depending on the material to be processed, it is desirable to obtain an appropriate value for the gas used and the processing conditions according to the material.

  In this embodiment, a sample that requires the pattern formation of the hard mask 204 by the processing in the first step is used. However, for example, a sample having a structure in which a hard mask, for example, a TEOS film is patterned on a film to be etched in advance. Also for the above, it is possible to adjust the pattern size and density difference as a mask by applying the second step of this embodiment before processing the film to be etched.

  In the second step of the present embodiment, a dense pattern having a fine L / S (line and space) has a feature that a reduction amount of a pattern dimension by a reduction process is small compared to a sparse pattern having a wide space interval. Therefore, in the adjustment of the first step, in the processing of the hard mask layer in which the dense pattern is adjusted to a predetermined size in the adjustment of the first step and the etching process is performed using the mask layer as a mask, the adjustment is performed in the first step. It is preferable to use processing conditions that can maintain the pattern size.

  Further, in the reduction process of the second step which is one of the embodiments, the sparse pattern can be selectively reduced, and therefore the SiON layer of the first step capable of adjusting the size of each sparse / dense pattern to some extent. In the etching process for forming the pattern 202, it is not necessary to perform an etching process that is excessive for the dense pattern, particularly in order to make the sparse pattern have a predetermined set value pattern dimension. As a result, for example, in a dense pattern when a sparse pattern dimension is adjusted, a mask defect of the dense pattern due to the etching process, a disconnection or bending of the pattern caused by the mask defect, an abnormality in the processing shape, etc. The problem can be reduced.

  According to this processing method, even when the patterned polysilicon mask has a deviation in the increasing direction with respect to the pattern size of the predetermined initial design value, the adjustment in the first step and the second step are performed. The deviation from the set value dimension can be reduced by processing the process. Further, even when the pattern dimension of the dense pattern is changed from a predetermined design value dimension, the pattern can be formed while maintaining a predetermined density difference by performing the first process and the second process. . The dry etching method according to the present embodiment is optimized for consistent processing from the first step to the second step in the same etching chamber, and includes the pattern dimension monitoring position. The processing method is not limited to the example.

  As described above, according to this embodiment, it is possible to provide a dry etching method capable of forming a pattern with a predetermined set value sparse / dense difference when a pattern including a sparse pattern region and a dense pattern region is formed using a hard mask. it can.

101 vacuum vessel,
102 Wafer mounting electrode,
103 Power supply for generating electromagnetic waves,
104 shower plate,
105 dielectric window,
106 treatment chamber,
107 gas supply device,
108 vacuum exhaust port,
109 waveguide,
110 Magnetic field generating coil,
111 wafers,
112 matching circuit,
113 high frequency power supply,
114 high frequency filter,
115 DC power supply,
201 polysilicon mask,
202 SiON layer,
203 polysilicon layer,
204 hard mask layer,
205 Material to be etched (film to be processed).

Claims (10)

In a dry etching method of forming a pattern having a dense portion and a sparse portion in a film to be processed by plasma etching using a mask,
A first step of forming, on the mask, a pattern in which the dimension of the dense part is a predetermined dimension and the dimension of the sparse part is larger than a predetermined dimension;
While maintaining the size of the dense portion after the first step, the size of the sparse portion is reduced to set a predetermined density difference which is the difference between the pattern size of the dense portion and the pattern size of the sparse portion. And a second step of making a value density difference. The dry etching method according to claim 1,
The dry etching method, wherein the film to be processed includes a polysilicon film, and the gate electrode is formed by plasma etching the film to be processed using the mask after the second step. The dry etching method according to claim 1,
The dry etching method according to claim 1, wherein a predetermined dimension of the pattern of the dense portion is 25 nm or less. The dry etching method according to claim 2, wherein
On the mask before the first step, a first polysilicon film in which a pattern having a dense portion and a sparse portion is patterned in advance is formed,
The dry etching method according to claim 1, wherein the mask before the first step includes a film in which an SiON film, a second polysilicon film, and a TEOS film are sequentially stacked. The dry etching method according to claim 4, wherein
The second step uses a mixed gas of CHF ₃ gas and SF ₆ gas in the dry etching method. The dry etching method according to claim 1,
The dry etching method according to claim 1, wherein the first step is performed so as to reduce a density difference which is a difference between a pattern size of the dense portion and a pattern size of the sparse portion. The dry etching method according to claim 1,
The dry etching method, wherein the first step and the second step are the same step. In a dry etching method for forming a pattern having a dense portion and a sparse portion in a film to be processed,
The film to be processed and a mask formed on the film to be processed, the mask having a pattern in which the dense portion has a predetermined size and the sparse portion has a size larger than the predetermined size are stacked. Preparing a prepared substrate; and
The step of reducing the size of the sparse part while maintaining the size of the dense part, and setting the density difference, which is the difference between the pattern size of the dense part and the pattern size of the sparse part, to a predetermined set value density difference When,
And a step of etching the film to be processed by using the mask after the second step. A pattern having a dense portion and a sparse portion formed on the film to be processed, fourth, third, and second films formed by sequentially laminating on the film to be processed, and the second film. Providing a substrate comprising a first film comprising:
Using the first film as a mask, forming a pattern on the second film in which the dense part has a predetermined dimension and the sparse part has a dimension larger than a predetermined dimension;
Transferring the pattern formed on the second film to the third film;
Transferring the pattern transferred to the third film to the fourth film;
Thereafter, while maintaining the size of the dense portion transferred to the fourth film, the size of the sparse portion is reduced to reduce the density of the dense portion and the pattern size of the sparse portion. A step of setting the difference to a predetermined set value density difference;
Thereafter, the process target film is etched using the fourth film as a mask. The dry etching method according to claim 9, wherein
The film to be processed, the fourth film, the third film, the second film, and the first film are a third polysilicon film, a TEOS film, a second polysilicon film, and a SiON film, respectively. , The first polysilicon film,
The step of forming a pattern in which the dense portion has a predetermined dimension and the sparse portion has a dimension larger than the predetermined dimension on the second film includes O ₂ gas and CHF ₃ gas as etching gases. Using a mixed gas of
While maintaining the size of the dense portion transferred to the fourth film, the size of the sparse portion is reduced to reduce the density difference between the pattern size of the dense portion and the pattern size of the sparse portion. The step of obtaining a predetermined set value density difference uses a mixed gas of CHF ₃ gas and SF ₆ gas as an etching gas.

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