JP2008251013A - Semiconductor integrated circuit and control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, capable of reducing the power consumption of a circuit laid in a standby state by shortening saving-restoration time of internal state. <P>SOLUTION: The semiconductor integrated circuit comprises an object circuit and a backup control circuit. The object circuit includes at least one scan chain which forms a shift register in a scan path test and serially inputting and outputting test data. The backup control circuit stores internal state data showing the internal state of the object circuit in a memory, and reads the internal state data from the memory. The scan chain is divided to a plurality of sub-scan chains. The plurality of sub-scan chains operate in parallel. The internal state data is output from the plurality of sub-scan chains and stored in the memory. The internal state data stored in the memory is reset to the plurality of sub-scan chains, and the object circuit returns to the original internal state and restarts operation. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a control method thereof, and more particularly to a semiconductor integrated circuit including a circuit that saves and recovers an internal state and a control method thereof.

  In recent years, a semiconductor integrated circuit having a low power consumption mode such as a standby function or a resume function has attracted attention. Normally, when the power supply is stopped, the internal state of the semiconductor integrated circuit is erased except for the nonvolatile memory. Therefore, when the power supply is resumed, the circuit operation starts from the state immediately before the circuit power supply is stopped. In order to resume, the internal state must be maintained.

  For example, Japanese Patent Laid-Open No. 6-52070 discloses an integrated circuit that saves and holds internal state data held in a register in an external memory when power supply is stopped. The integrated circuit includes a plurality of registers, a data saving unit, and a data restoring unit, and the plurality of registers are connected to form a scan chain, and the data saving unit responds to an external signal, and a data saving mode Sometimes, a scan chain is formed in a plurality of registers, and the data held in each register is read to the outside through the formed scan chain. At this time, the data saving unit serial / parallel converts the internal state data into data having a predetermined bit width, and stores the data in the data protection memory through the data input / output unit. In response to the external signal, the data restoration unit causes a plurality of registers to form a scan chain in the data restoration mode, and restores the data saved through the formed scan chain to the original register. At this time, the data restoration unit reads the internal state data from the data protection memory, inputs it from the data input / output means, converts the data of a predetermined bit width into serial internal state data, and restores it through the scan chain.

  Japanese Patent Application Laid-Open No. 2004-164647 discloses a technique related to a data processing apparatus including a circuit having one or a plurality of nodes, a memory, a system bus, and a state storage controller. A circuit having one or more nodes is a circuit used for processing data and stores one or more data values that collectively define the state of the circuit. The memory stores data. The system bus is a system bus that couples between the circuit and memory, and is often connected between the circuit and memory in response to a memory transfer request given to the system bus during normal processing operations of the circuit and memory. Transfer bit data words. A state save controller couples to the circuit and system bus and, in response to a save trigger, reads a data value defining the circuit state from one or more nodes and places a sequence of memory write requests on the system bus. One or more state-saving multi-bit data words that are generated and representing the data values are written to the memory so that the state of the circuit can be recovered using the one or more state-saving multi-bit data words. Further, as a related technique, there is a technique described in US Publication No. 2005/0149799.

JP-A-6-52070 JP 2004-164647 A US Publication No. 2005/0149799

  As described above, when the internal state is saved and restored using the scan chain, since the scan chain is composed of a large number of registers connected in series, all the data held in the register is serially stored. It takes time to evacuate / restore. In addition, in order to write internal node data to the memory via the system bus and read from the memory, it is necessary to start a memory write sequence and memory read sequence including securing the right to use the system bus.・ Recovery time becomes longer.

  An object of the present invention is to provide a semiconductor integrated circuit and a control method therefor that can shorten the save / recovery time of the internal state while putting the semiconductor integrated circuit in a standby state.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  In an aspect of the present invention, the semiconductor integrated circuit includes a target circuit (11) and a backup control circuit (12). The target circuit (11) includes at least one scan chain (15) that forms a shift register and inputs / outputs test data serially during a scan path test. The backup control circuit (12) stores internal state data indicating the internal state of the target circuit (11) in the memory (13), and reads the internal state data from the memory (13). The scan chain (15) is divided into a plurality of sub scan chains (21 to 24, 31 to 34). The plurality of sub-scan chains (21-24, 31-34) operate in parallel. The internal state data is output from the plurality of sub scan chains (21 to 24, 31 to 34) and stored in the memory (13). The internal state data stored in the memory (13) is set again in the plurality of sub scan chains (21 to 24, 31 to 34), and the target circuit (11) returns to the original internal state and resumes operation. To do.

  In another aspect of the present invention, the internal state save / recovery method includes an operation switching step, a save step, a recovery step, and a restart step. The target circuit (11) includes at least one scan chain (15) used for a scan path test. In the operation switching step, the scan chain (15) is divided into a plurality of sub scan chains (21 to 24, 31 to 34) that operate in parallel. In the saving step, internal state data indicating the internal state of the target circuit (11) output from each of the plurality of sub scan chains (21 to 24, 31 to 34) is stored in the memory (13). In the recovery step, the internal state data output from the memory (13) is set again in the plurality of sub scan chains (21 to 24, 31 to 34). In the restarting step, the plurality of sub-scan chains (21 to 24, 31 to 34) are released, and the operation of the target circuit (11) is restarted from the original state.

  According to the present invention, the scan chain is divided into a plurality of sub-scan chains, and the outputs of the sub-scan chains are stored in the memory in parallel, so that the internal state save / recovery time is shortened and the control thereof It becomes possible to provide a method.

  A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the semiconductor integrated circuit according to the first embodiment. The semiconductor integrated circuit includes a target circuit 11 whose internal state is saved to the outside, a backup memory 13 that stores the internal state of the target circuit 11, and a backup control circuit 12 that controls saving and recovery of the internal state of the target circuit 11. And a switch 14 for controlling the power supply of the target circuit 11. The internal state of the target circuit 11 is embodied by internal node data held in a flip-flop inherent in the target circuit 11.

  The backup control circuit 12 receives an instruction (WFI) from the target circuit 11, switches the operation mode (MD) of the target circuit 11, and saves data indicating the internal state of the target circuit 11, that is, internal node data, to the backup memory 13. . The backup control circuit 12 is activated by an external interrupt signal (INT), sets internal node data stored in the backup memory 13 to each node of the target circuit 11, and recovers the internal state of the target circuit 11. To do. In the internal state saving / restoring operation, the backup control circuit 12 controls the storage address (ADDR) and the write / read timing (CTR) of the backup memory 13.

  The power supply system of the target circuit 11 is separated from other circuits. Therefore, it is possible to cut off the power supply of only the target circuit 11. The switch 14 turns on and off the power based on the control (PWC) of the backup control circuit 12.

  The backup memory 13 holds internal node data indicating the internal state of the target circuit 11. The backup memory 13 only needs to have a capacity for storing the internal node data of the target circuit 11. The data width (word length) is widened in order to capture the internal node data TO efficiently. For example, if there are 32 scan chains and four internal node data TO are extracted from each scan chain, 128-bit data is output in parallel for each scan clock. Therefore, the backup memory 13 needs a word length of 128 bits or more. The write / read operation timing CTR and address ADDR of the backup memory 13 are given from the backup control circuit 12. This backup memory 13 is a memory having a low threshold voltage and a low leakage current. Therefore, the speed of the backup memory 13 is not so high, but the power consumption is small. Further, when a non-volatile memory such as a flash memory is used as the backup memory 13, the backup memory 13 can be powered off during standby, and power consumption can be further reduced.

  The internal node data indicating the internal state of the target circuit 11 is input / output via the scan chain 15. The scan chain 15 is used for a scan path test for testing the normality of the semiconductor integrated circuit. In the scan path test, the scan chain 15 serially inputs test data from the scan input SI and outputs a test result from the scan output SO. Although not described here, the backup control circuit 12 and the backup memory 13 may be scan path test targets.

  The target circuit 11 is a circuit portion having an internal state to be held during standby. The target circuit 11 incorporates a circuit for a scan path test that is performed in order to detect a manufacturing defect or the like of the target circuit 11. In this scan path test circuit, flip-flops inherent in the target circuit 11 are connected in a chain at the time of testing, and data is input / output as a shift register. This shift register is called a so-called scan chain. At least one scan chain 15 is set in the target circuit 11. In recent semiconductor integrated circuits, about 32 scan chains 15 are often set, but more scan chains may be set or only one. Each scan chain 15 receives scan path test serial data from an externally connected scan input SI (SI1 to SIn to SIN) and an externally connected scan output SO (SO1 to SOn to SON). Campus test result data is output serially. The input / output of each serial data need not be synchronized, and may operate independently for each scan chain. Hereinafter, the scan chain 15 will be described by taking a circuit of the scan input SIn and the scan output SOn (n = 1, 2,..., N) as an example.

  When the internal logic circuit operates, the target circuit 11 holds its operation state in a sequential circuit (flip-flop) included in the logic circuit. That is, the flip-flop holds the internal state of the target circuit 11. By saving the internal node data held in the flip-flop, the internal state of the target circuit 11 can be output to the outside, and by setting the data in each flip-flop, the internal state of the target circuit 11 can be set. On the other hand, the flip-flop can form the scan chain 15 and serially output the stored data during the scan path test. Further, the scan chain 15 can serially input data and set data for a scan path test in each flip-flop. Therefore, by using this scan chain 15, the state of the flip-flop can be read and written.

  Based on the control of the backup control circuit 12, the target circuit 11 outputs the output of the scan chain 15, that is, the scan output SO and the data TO extracted from a plurality of positions in the scan chain 15 to the backup memory 13. When data held in all flip-flops of the target circuit 11 is output, the internal state of the target circuit 11 is saved in the backup memory 13. The target circuit 11 takes in the data TI output from the backup memory 13 and sets it in the scan chain 15 based on the control of the backup control circuit 12. When data is set in the scan chain 15, the internal state of the target circuit 11 is recovered. When the target circuit 11 is switched from the recovery state to the normal operation state, the target circuit 11 returns to the normal operation.

  FIG. 2 shows the configuration of the scan chain 15 when the scan chain is enabled. The scan chain 15 is a single chain formed by connecting a plurality of registers during a scan test, and a sub-scan chain is obtained by dividing the single chain into a plurality of chains. The scan chain 15 includes a plurality of sub scan chains. Here, the scan chain 15 includes four sub scan chains 21, 22, 23, and 24. Each of the sub scan chains 21, 22, 23, and 24 includes the same number of flip-flops. The sub scan chains 21, 22, 23, and 24 are connected in cascade, and operate as one scan chain 15 during a scan path test. When inputting / outputting internal node data, the sub-scan chains 21, 22, 23, 24 operate in parallel, and input / output data simultaneously. The sub-scan chain 21 includes a selection circuit 210 and flip-flops 211 to 214 that are actual scan chains. Similarly, the sub-scan chain 22 includes a selection circuit 220 and flip-flops 221 to 224, the sub-scan chain 23 includes a selection circuit 230 and flip-flops 231 to 234, and the sub-scan chain 24 includes a selection circuit 240 and flip-flop 241. ˜244. The selection circuits 210, 220, 230, and 240 select and output one of the two input signals based on the selection signal TB.

  In the sub scan chain 21, the selection circuit 210 receives the scan input SIn and the internal node data TI1 stored in the backup memory 13. The selection circuit 210 selects and outputs data input from the scan input SIn during the scan path test based on the selection signal TB, and the internal node data TI1 stored in the memory 13 during the internal state saving / recovery. Select to output. The flip-flops 211 to 214 are connected in a chain to form a shift register, and an output signal of the selection circuit 210 is input thereto. The output of the flip-flop 214 is output as internal node data TO1, and is sent to the sub-scan chain 22 at the next stage.

  In the sub scan chain 22, the selection circuit 220 inputs the output data TO 1 of the previous sub scan chain 21 and the internal node data TI 2 stored in the backup memory 13. Based on the selection signal TB, the selection circuit 220 selects and outputs the previous stage output data TO1 during the scan path test, and selects the internal node data TI2 stored in the memory 13 during the internal state saving / recovery. Output. The flip-flops 221 to 224 are connected in a chain to form a shift register, and an output signal of the selection circuit 220 is input thereto. The output of the flip-flop 224 is output as internal node data TO2, and is sent to the sub-scan chain 23 at the next stage.

  Similarly, in the sub scan chain 23, the selection circuit 230 inputs the output data TO2 of the previous sub scan chain 22 and the internal node data TI3 stored in the backup memory 13. Based on the selection signal TB, the selection circuit 230 selects and outputs the previous-stage output data TO2 during the scan path test, and selects the internal node data TI3 stored in the memory 13 during the internal state saving / restoring. Output. The flip-flops 231 to 234 are connected in a chain to form a shift register, and an output signal of the selection circuit 230 is input thereto. The output of the flip-flop 234 is output as internal node data TO3 and sent to the sub-scan chain 24 at the next stage.

  Similarly, in the sub scan chain 24, the selection circuit 240 inputs the output data TO3 of the sub scan chain 23 in the previous stage and the internal node data TI4 stored in the backup memory 13. Based on the selection signal TB, the selection circuit 240 selects and outputs the previous stage output data TO3 during the scan path test, and selects the internal node data TI4 stored in the memory 13 during the internal state saving / restoring. Output. The flip-flops 241 to 244 are connected in a chain to form a shift register, and an output signal of the selection circuit 240 is input thereto. The output of the flip-flop 244 is output as internal node data TO4 and also output to the outside as the output SOn of the scan chain 15.

  Next, the operation of the scan chain 15 will be described. During the original functional operation of the target circuit 11, the flip-flops 211 to 214, the flip-flops 221 to 224, the flip-flops 231 to 234, and the flip-flops 241 to 244 serve as internal logic circuit registers. Node data).

  In the case of the scan path test, the flip-flops inherent in the target circuit 11 are connected so as to form the scan chain 15 as shown in FIG. Since the scan chain is well known, a detailed description is omitted. In practice, a selection circuit that is connected and wired and built in a flip-flop (not shown) is set to select a signal of the scan chain when forming the scan chain. The selection circuits 210, 220, 230, and 240 are set so as to select and output data on the scan data side according to the selection signal TB. Accordingly, the flip-flops included in the sub-scan chains 21 to 24 form one connected shift register. In synchronization with the scan clock, scan data is input from the scan input SIn, and sequentially moves through the flip-flops toward the scan output SOn. When the scan data is set in all the flip-flops, each flip-flop is once released from the configuration of the scan chain 15 and takes in the data of the target circuit 11 which is the original internal logic circuit. At this time, since each flip-flop outputs scan data, each flip-flop holds the result of the scan path test. Thereafter, the flip-flop returns to the configuration of the scan chain 15. The shift register that holds the scan path test result outputs the scan path test result data from the scan output SOn based on the scan clock.

  In the case of saving internal node data, the scan chain 15 is set so that the sub scan chains 21 to 24 function in parallel. The selection signal TB may be set to either one, but here is set to select the output (TI) of the backup memory 13. As in the scan path test, the internal node data held in the flip-flop is sequentially output to the backup memory 13 in parallel as sub-scan chain output data TO1 to TO4 in synchronization with the clock. The address ADDR of the backup memory 13 is updated in synchronization with the clock by the backup control circuit 12, and the output data TO <b> 1 to TO <b> 4 of the sub scan chain are sequentially stored in the backup memory 13. When data is output by the number of flip-flops included in the sub scan chain, all internal node data included in the scan chain 15 is output to the backup memory 13. Therefore, the output time can be shortened by connecting the output SOn of the scan chain 15 to the memory and storing the internal node data. As shown in FIG. 2, when the scan chain 15 is divided into four like the sub scan chains 21 to 24, the output time becomes 1/4.

  In the case of internal node data recovery, that is, when internal node data held in the backup memory 13 is set in the original flip-flop, the scan chain 15 is set so that the sub scan chains 21 to 24 function in parallel. The The selection signal TB is set so as to select the output (TI) of the backup memory 13. Internal node data TI1 to TI4 from the backup memory 13 are input to the sub scan chains 21 to 24. The backup control circuit 12 updates the address ADDR of the backup memory 13 for each clock from the initial setting value, and controls the internal node data TI1 to TI4 to be supplied to the sub scan chains 21 to 24 in the order in which they are saved. The internal node data TI1 to TI4 supplied to the sub scan chains 21 to 24 move the shift registers formed in the sub scan chain through the selection circuits 210, 220, 230, and 240 toward the outputs TO1 to 4. To go. When shifting by the number of flip-flops included in the sub-scan chain, the original internal node data is set in each flip-flop. Thus, the internal state of the target circuit 11 has been recovered. Thereafter, when the backup recovery mode is canceled, the target circuit 11 returns to a normal operation.

  As described above, the operation state of the semiconductor integrated circuit including the circuit that saves the internal node data to the backup memory 13 and recovers the internal node data from the backup memory 13 to the target circuit 11 using the scan chain (sub-scan chain). Will be described with reference to FIG. Here, it is assumed that the target circuit 11 is a CPU (central processing unit) built in the semiconductor integrated circuit, and the processing state of the software executed by the CPU is described as the state of the target circuit 11. The operation state when the semiconductor integrated circuit is viewed from the outside (software) is shown on the left side of FIG. The operation state of the target circuit 11, the backup control circuit 12, and the backup memory 13 when viewed from the inside (hardware) is shown on the right side of FIG.

  In a normal operation, the semiconductor integrated circuit may enter a standby state due to, for example, periodic processing or man-machine interface processing. At that time, the CPU 11 executes a WFI (Wait for Interrupt) instruction and enters a standby state. Usually, in the standby state, the execution of software is stopped. In this case, the hardware lowers the power supply voltage to the minimum standby voltage to reduce power consumption so that immediate execution can be resumed when an interrupt signal INT for instructing process resumption is input. In order to further reduce power consumption, in the present invention, as indicated by a broken line in FIG. 3, the power supply to the CPU 11 is stopped, and the leakage current in the standby state is reduced. Since the internal state of the CPU 11 is cleared when the power of the CPU 11 is turned off, the internal state of the CPU 11 is saved in the backup memory 13 before the power is turned off.

  When an interrupt signal INT serving as a trigger for restarting the operation of the CPU 11 is input to the backup control circuit 12, the power of the CPU 11 is turned on. The internal state of the CPU 11 is recovered from the backup memory 13, and execution of the software is resumed. Since the interrupt signal INT is input, the software first executes the interrupt process and then returns to the normal process. Therefore, the software operates as if the standby state is maintained without being affected by the power ON / OFF.

  That is, the target circuit (CPU) 11 is in a normal operation state until the WFI command is issued, and the software is stopped by the WFI command, so that the internal state is frozen. When the WFI instruction is issued, the backup control circuit 12 and the backup memory 13 are activated from the standby state. The backup control circuit 12 puts the target circuit (CPU) 11 into a retreat state where a scan chain is set. The backup control circuit 12 saves the frozen internal node data of the target circuit (CPU) 11 in the backup memory 13. When all the internal node data of the target circuit (CPU) 11 is saved, the backup control circuit 12 controls the switch 14 to stop the power supply to the target circuit (CPU) 11. The backup control circuit 12 is in a standby state until the interrupt signal INT is input. Since the backup control circuit 12 and the backup memory 13 are configured to have a smaller circuit scale and lower power consumption than the target circuit (CPU) 11, leakage current is reduced.

  When the interrupt signal INT is input to the backup control circuit 12, the backup control circuit 12 returns from the standby state to the operating state. First, the backup control circuit 12 controls the switch 14 to resume power supply to the target circuit (CPU) 11. Next, the backup control circuit 12 puts the target circuit (CPU) 11 in a recovery state in which the scan chain is set. The backup control circuit 12 supplies the internal node data TI stored in the backup memory 13 to the sub scan chain and restores the internal state. When the internal state of the target circuit (CPU) 11 is restored to the original state, the backup control circuit 12 cancels the recovery state of the target circuit (CPU) 11 and activates the target circuit (CPU) 11. The target circuit (CPU) 11 resumes operation. The backup control circuit 12 and the backup memory 13 are in a standby state until the next WFI instruction is issued. Here, the target circuit 11 has been described as being a CPU. However, the target circuit 11 is not limited to the CPU, and can be similarly implemented by a random logic circuit.

  In this way, serial data is sent to the sub-scan chains 21 to 24 shorter than the scan chain 15 to reset the internal state, and the recovery time is shortened. As described above, according to the present invention, the internal state can be saved and restored in a shorter time, and the leakage current during the standby period can be reduced.

  FIG. 4 is a block diagram showing the configuration of a scan chain provided with a path for further shortening the minimum recovery time. The minimum recovery time is the time required when saving is instructed immediately after the saving of internal state data is started, that is, when recovery of internal state data is instructed. The scan chain 15 shown in FIG. 4 is further provided with a selection circuit at the head of each of the sub scan chains 21 to 24 shown in FIG.

  The scan chain 15 includes sub-scan chains 31, 32, 33, and 34. The sub scan chain 31 includes selection circuits 319 and 310 and flip-flops 311 to 314. Similarly, the sub scan chain 32 includes selection circuits 329 and 320 and flip-flops 321 to 324, the sub scan chain 33 includes selection circuits 339 and 330 and flip flops 331 to 334, and the sub scan chain 34 includes Selection circuits 349 and 340 and flip-flops 341 to 344 are provided. The parts other than the selection circuits 319, 329, 339, and 349 are the same as the scan chain shown in FIG.

  Based on the selection signal BR, the selection circuits 319, 329, 339, and 349 select either the saved internal node data TI output from the backup memory 13 or the internal node data TO output from the sub scan chain. The data is output to the selection circuits 310, 320, 330, and 340.

  In the sub scan chain 31, the selection circuit 319 inputs the internal node data TI1 input from the backup memory 13 and the internal node data TO1 output from the sub scan chain 31. Based on the selection signal BR, the selection circuit 319 selects and outputs the internal node data TO1 to be fed back when the internal state is saved, and selects the saved internal node data TI1 when the internal state is restored. Output. The selection circuit 310 receives the scan input SIn and the output signal of the selection circuit 319. Based on the selection signal TB, the selection circuit 310 selects and outputs the scan input signal SIn during the scan path test, and selects and outputs the output signal of the selection circuit 319 during the internal state saving / recovery. The flip-flops 311 to 314 are connected in a chain to form a shift register, and an output signal of the selection circuit 310 is input thereto. The output signal of the flip-flop 314 is output as internal node data TO1, and is sent to the sub scan chain 32 in the next stage.

  In the sub scan chain 32, the selection circuit 329 inputs the internal node data TI2 input from the backup memory 13 and the internal node data TO2 output from the sub scan chain 32. Based on the selection signal BR, the selection circuit 329 selects and outputs the internal node data TO2 so as to be fed back when the internal state is saved, and selects and outputs the saved internal state TI2 when the internal state is recovered. To do. The selection circuit 320 inputs the output data TO1 of the sub-scan chain 31 in the previous stage and the output signal of the selection circuit 329. Based on the selection signal TB, the selection circuit 320 selects and outputs the pre-stage output data TO1 during the scan path test, and selects and outputs the output signal of the selection circuit 329 during the internal state saving / recovery. The flip-flops 321 to 324 are connected in a chain to form a shift register, and the output signal of the selection circuit 320 is input thereto. The output signal of the flip-flop 324 is output as internal node data TO2, and is sent to the sub-scan chain 33 at the next stage.

  Similarly, in the sub scan chain 33, the selection circuit 339 inputs the internal node data TI3 input from the backup memory 13 and the internal node data TO3 output from the sub scan chain 33. Based on the selection signal BR, the selection circuit 339 selects and outputs the internal node data TO3 so as to be fed back when the internal state is saved, and selects and outputs the saved internal state TI3 when the internal state is restored. To do. The selection circuit 330 inputs the output data TO2 of the sub-scan chain 32 in the previous stage and the output data of the selection circuit 339. Based on the selection signal TB, the selection circuit 330 selects and outputs the pre-stage output data TO2 during the scan path test, and selects and outputs the output signal of the selection circuit 339 during the internal state saving / recovery. The flip-flops 331 to 334 are connected in a chain to form a shift register, and an output signal of the selection circuit 330 is input thereto. The output of the flip-flop 334 is output as internal node data TO3 and sent to the sub-scan chain 34 at the next stage.

  Similarly, in the sub scan chain 34, the selection circuit 349 inputs the internal node data TI4 input from the backup memory 13 and the internal node data TO4 output from the sub scan chain 34. Based on the selection signal BR, the selection circuit 349 selects and outputs the internal node data TO4 so as to be fed back when the internal state is saved, and selects and outputs the saved internal state TI4 when the internal state is recovered. To do. The selection circuit 340 receives the output data TO3 of the sub-scan chain 33 in the previous stage and the output data of the selection circuit 349. Based on the selection signal TB, the selection circuit 340 selects and outputs the previous-stage output data TO3 during the scan path test, and selects and outputs the output signal of the selection circuit 349 during the internal state saving / restoring. The flip-flops 341 to 344 are connected in a chain to form a shift register, and the output signal of the selection circuit 340 is input thereto. The output of the flip-flop 344 is output as the internal node data TO4 and also output to the outside as the output SOn of the scan chain 15.

  The operation of the scan chain 15 will be described with reference to FIGS. 5A, 5B, and 5C. When the scan chain is not formed, the flip-flops 311 to 314, the flip-flops 321 to 324, the flip-flops 331 to 334, and the flip-flops 341 to 344 hold the internal state of the target circuit 11.

  In the case of the scan path test, as shown in FIG. 5A, the flip-flops inherent in the target circuit 11 form a scan chain. At this time, the selection signal TB is set so as to select scan path test data. The selection signal BR may be set either because it does not affect the signal path. Accordingly, the flip-flops 311 to 314, the flip-flops 321 to 324, the flip-flops 331 to 334, and the flip-flops 341 to 344 form one continuous shift register. As indicated by a thick line in FIG. 5A, scan path test data is input from the scan input SIn, and is sequentially set in each flip-flop by moving through the flip-flops.

  Once the scan path test data is set in each flip-flop, the scan chain is once released and the internal logic operation is checked. The result is taken into each flip-flop, and a scan chain is formed again. The check result set in each flip-flop is sequentially output from the scan output SOn by moving the flip-flop forming the shift register. In this way, data is input / output in the scan path test.

  Next, a save operation for saving the internal node data of the target circuit 11 to the backup memory 13 will be described with reference to FIG. 5B. In the internal node data saving operation, the selection circuits 310, 320, 330, and 340 select and output data input from the selection circuits 319, 329, 339, and 349 based on the selection signal TB, respectively. Set to The selection signal BR is set so that the outputs TO1 to TO4 of the sub-scan chains 31 to 34 are returned to their own inputs TI1 to TI4, respectively. That is, as indicated by the bold line in FIG. 5B, the internal node data is shifted so as to circulate within each sub-scan chain. Therefore, when all the internal node data held in the sub scan chain 31 is output as the output data TO1, the original internal node data is set in the flip-flops 311 to 314. Similarly, in the sub-scan chains 32, 33, and 34, when all the internal node data has been output, the flip-flops 321 to 324, the flip-flops 331 to 334, and the flip-flops 341 to 344 retain the original internal node data. To do.

  This is nothing but saving and restoring internal node data at the same time. For example, when the interrupt signal INT is input while the internal node data of the target circuit 11 is being saved to the backup memory 13 and the return operation must be started, the operation of the target circuit is performed when the save operation is completed. It is possible to resume. In the configuration of the scan chain 15 shown in FIG. 2, once the save operation is started, it is necessary to save all internal node data to the backup memory 13 and then restore the internal node data from the backup memory 13 to the scan chain 15. is there. On the other hand, the normal operation of the target circuit 11 can be resumed immediately after the save operation by circulating the internal node data TO1 to TO4 of the sub scan chains 31 to 34 to itself. Therefore, it is possible to shorten the time from the start of the evacuation operation to the recovery of the operation.

  A recovery operation for recovering the internal state of the target circuit 11 from the internal node data stored in the backup memory 13 will be described with reference to FIG. 5C. As described with reference to FIG. 5B, the internal memory data of the target circuit 11 is stored in the backup memory 13 in order. When recovering this data to the target circuit 11, the selection circuits 310, 320, 330, and 340 select and output data input from the selection circuits 319, 329, 339, and 349, respectively, based on the selection signal TB. Is set as follows. The selection signal BR is set so that the selection circuits 319, 329, 339, and 349 select and output the internal node data TI output from the backup memory 13.

  That is, as indicated by a thick line in FIG. 5C, the internal node data TI1 input from the backup memory 13 is shifted in the sub scan chain 31 and set in the flip-flops 311 to 314. Similarly, the internal node data TI2 is shifted in the sub scan chain 32 and set in the flip-flops 321 to 324. Internal node data TI3 is shifted in sub-scan chain 33 and set in flip-flops 331-334. Internal node data TI4 is shifted in sub scan chain 34 and set in flip-flops 341-344.

  As described above, the internal node data held in the backup memory 13 is stored in the flip-flops 311 to 314, the flip-flops 321 to 324, the flip-flops 331 to 334, and the flip-flops 341 to 344, and returns to the original internal state. . Thereafter, the scan chain is released and the target circuit 11 returns to normal operation.

  In the above description, each sub-scan chain is described as including the same number of flip-flops. However, the total number of flip-flops included in the scan chain 15 is not necessarily a multiple of the number of sub-scan chains. Therefore, when the number of flip-flops included in each sub-scan chain is different, it is preferable to insert dummy flip-flops that hold temporary internal node data to make the numbers uniform. It is also possible to configure so that sub-scan chains having the same number of included flip-flops are simultaneously output to the backup memory. In that case, the number of dummy flip-flops to be inserted can be reduced or unnecessary. It is also possible to save and restore internal node data of sub-scan chains having different numbers of built-in flip-flops by changing the shift clock provided for each sub-scan chain.

  FIG. 6 is a block diagram showing an example of the scan chain 15 provided with dummy flip-flops. This dummy flip-flop belongs to another scan chain, and operates as a part of the other scan chain during the scan path test. The scan chain 15 shown in FIG. 6 is in a state where the flip-flops 224 and 241 of the scan chain shown in FIG. 2 are not present. That is, the scan chain 15 shown in FIG. 6 has fewer flip-flops included in the sub scan chains 22 and 24 than the sub scan chains 21 and 23. In the sub-scan chain 22, a flip-flop (hereinafter referred to as a dummy flip-flop) 224 ′ that is not included in the scan chain 15 is connected to the subsequent stage of the flip-flop 223. Accordingly, the flip-flop 223 is connected to the dummy flip-flop 224 ′ and the selection circuit 230 of the next-stage sub-scan chain 23. The dummy flip-flop 224 ′ outputs the output of the flip-flop 223 to the backup memory 13. In the sub-scan chain 24, the dummy flip-flop 241 ′ is connected to the preceding stage of the selection circuit 240. The internal node data TI4 output from the backup memory 13 is input to the dummy flip-flop 241 '. The output of the dummy flip-flop 241 ′ is input to the flip-flops 242 to 244 constituting the shift register via the selection circuit 240. In this way, by connecting the dummy flip-flops 224 ′ and 241 ′ to the sub-scan chains 22 and 24, the sub-scan chains 22 ′ and 24 including the same number of flip-flops as the flip-flops included in the sub-scan chains 21 and 23. 'Is formed. Therefore, the sub scan chains 21, 22 ', 23, 24' can output the same number of internal state data to the backup memory 13. Also, the sub scan chains 21, 22 ', 23, 24' can take the same number of internal state data from the backup memory 13 and set it in each flip-flop. Here, the number of over / under flip-flops has been described as one circuit per sub-scan chain. However, even if there are a plurality of flip-flops, the number of flip-flops in each sub-scan chain can be made uniform. Further, the dummy flip-flop operates in the same way regardless of whether it is connected to either the front or back of the original sub-scan chain, or further connected to both the front and back sides. It is also possible to arrange a second selection circuit at the head of the sub-scan chain to which this dummy flip-flop is connected, and feed back the output of each sub-scan chain to the head as shown in FIG. It is.

  In this way, by connecting the dummy flip-flops, the number of flip-flops included in the sub-scan chain can be made uniform without including the dummy flip-flops in the scan chain during the scan path test. This dummy flip-flop can be included in the scan chain together with the backup control circuit, and can be prevented from affecting the scan path test of the target circuit.

  Next, a second embodiment will be described with reference to FIG. In the second embodiment, an example in which the interface between the scan chain and the backup memory is different from that of the first embodiment will be described. FIG. 7 shows a block diagram of the semiconductor integrated circuit. The semiconductor integrated circuit includes a target circuit 11, a backup memory 13, a backup control circuit 12, a switch 14, and a bus interface unit 16. The target circuit 11 is a circuit whose internal state is saved to the outside, and its power supply is controlled by the switch 14. The switch 14 is controlled by the backup control circuit 12. The internal state of the target circuit 11 is placed on the system bus 18 by the bus interface unit 16 and saved in the backup memory 13. The internal state stored in the backup memory 13 is put on the system bus 18 and is restored to the target circuit 11 via the bus interface unit 16. The backup control circuit 12 controls the saving / recovering of the internal state of the target circuit 11.

  The configuration and operation of the target circuit 11 are the same as those of the circuit shown in FIG. Accordingly, the internal state held in the scan chain 15 is output to the outside as the scan output SO during the scan path test. When the internal state of the target circuit 11 is saved, the internal node data held in the scan chain 15 is sent to the bus interface unit 16 through a path divided into sub scan chains. At this time, the internal node data is preferably sent to the bus interface unit 16 in the bus interface unit 16 with a data width equal to the bus width. The bus interface unit 16 adjusts the signal level and timing of the internal node data and outputs the adjusted data to the system bus 18. In synchronization with this, the backup memory 13 takes in the internal node data from the system bus 18 and stores it. The address ADDR of the backup memory 13 is supplied from the backup control circuit 12.

  When the internal state of the target circuit 11 is recovered, the internal node data stored in the backup memory 13 is read based on the address ADDR output from the backup control circuit 12 and sent to the system bus 18. In synchronization with this, the bus interface unit 16 takes in data from the system bus 18 and supplies it as internal node data TI to the sub-scan chain of the target circuit 11. The bus interface unit 16 adjusts the timing for fetching data from the system bus 18 and the conversion of the signal level. The sub scan chain performs the operation described in the first embodiment.

  As described above, the internal node data TO is stored in the backup memory 13 via the system bus 18, and the internal node data stored in the backup memory 13 is stored as internal node data TI in the target circuit 11 via the system bus 18. The target circuit 11 is returned to the original internal state.

  The semiconductor integrated circuit backs up part of the system memory connected to the system bus 18 by saving the internal node data of the target circuit 11 to the backup memory 13 via the system bus 18 and recovering from the backup memory 13. It can also be used as the memory 13. In that case, the backup control circuit 12 accesses the memory based on the interface specification of the system bus 18.

  If the system memory can be accessed via the system bus 18, the backup memory 13 may be outside the semiconductor integrated circuit in which the target circuit 11 is built. That is, by supporting a general-purpose interface, the degree of freedom in selecting a memory used as a backup memory is improved.

  As described above, by dividing the scan chain into sub-scan chains, the internal node data of the target circuit 11 is saved and recovered in a short time. Furthermore, since the internal state of the target circuit 11 is held externally, power supply to the target circuit 11 can be stopped, and power consumption can be reduced. Further, by inserting a selection circuit at the head of each sub-scan chain and returning the output of the sub-scan chain, it is possible to further shorten the recovery operation time according to the cancellation of the internal state saving operation.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. It is a block diagram which shows the structure of the same scan chain. It is a figure which shows the operation state of the semiconductor integrated circuit. It is a block diagram which shows the other structure of the same scan chain. It is a figure which shows the operation | movement at the time of the test of the scan chain of another structure. It is a figure which shows the operation | movement at the time of the retraction | saving of the scan chain of the other structure. It is a figure which shows the operation | movement at the time of the recovery of the scan chain of another structure. It is a block diagram which shows the structure of the scan chain provided with the same dummy flip-flop. FIG. 10 is a block diagram showing another configuration of the semiconductor integrated circuit.

Explanation of symbols

11 target circuit 12 backup control circuit 13 backup memory 14 switch 15 scan chain 16 bus interface unit 18 system bus 21, 22, 23, 24 sub scan chain 210, 220, 230, 240 selection circuit 211-214, 221-224, 231 234, 241 to 244 Flip-flops 31, 32, 33, 34 Sub-scan chains 310, 320, 330, 340 Select circuits 311 to 314, 321-324, 331-334, 341-344 Flip-flops 319, 329, 339, 349 selection circuit

Claims (10)

Including flip-flops,
A normal operation mode for executing a predetermined function;
A scan path test mode that configures a scan chain including the flip-flop and performs verification of the function using the scan chain;
A target circuit having a save mode for writing data held by the flip-flop in the normal operation mode to a storage device via the scan chain,
In the save mode, the scan chain outputs the data from the output end of the scan chain to the storage device and receives it from the input end of the scan chain. The scan chain includes a plurality of sub-scan chains,
In the save mode, the plurality of sub scan chains output the data held by the flip-flop included in the sub scan chain in the data from the output end of the sub scan chain to the storage device and the sub scan The semiconductor integrated circuit according to claim 1, wherein a retraction operation received from an input end of the chain is performed.   The semiconductor integrated circuit according to claim 2, wherein each of the sub-scan chains included in the scan chain performs the evacuation operation. The target circuit further has a recovery mode for acquiring the data written in the storage device during the save mode via the scan chain;
When the target circuit makes a transition from the save mode to the recovery mode before the scan chain completes outputting the data to the storage device, the target circuit writes the data written to the storage device before the transition The semiconductor integrated circuit according to claim 1, wherein the recovery mode is terminated at the time when the signal is acquired.   The scan chain further includes a first selector that selectively outputs one of data held by the flip-flop and data stored in the storage device in the normal operation mode. Item 14. The semiconductor integrated circuit according to Item 1.   The scan chain further includes a second selector that selectively outputs one of data output from the first selector and test data for executing the function verification. 5. The semiconductor integrated circuit according to 5.   The semiconductor integrated circuit according to claim 1, wherein the scan chain includes a plurality of flip-flops connected in series.   4. The semiconductor integrated circuit according to claim 3, wherein a clock supplied to a part of each of the sub scan chains is different from a clock supplied to the other sub scan chains.   4. The semiconductor integrated circuit according to claim 3, wherein the number of the flip-flops included in each of the sub scan chains is the same.   The semiconductor integrated circuit according to claim 2, wherein the sub-scan chain further includes a dummy flip-flop in addition to the flip-flop.

Images