JPH1078836A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption by reducing the leakage current during standby of a data processor. SOLUTION: Plural sequential circuits in a CPU + core 114 are constituted of plural scannable flip flops and plural combined circuits. The data of those flip flops are successively scanned-out and saved to a ferroelectric memory 110 by the control of a control circuit 103 before transition from a normal state to a waiting state. Data held in memories in a cache 122 or an RAM 127 are also successively read and saved by the control of the control circuit 103, and a power source switching circuit 146 is controlled so that power supply to those inside modules can be interrupted. The power source switching circuit 146 is controlled so that the power supply to those inside modules can be resumed before transition form the standby state to the normal state. Those saved data are successively read out of the ferroelectric memory 110, and written in the inside module which holds each data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processor, such as a microprocessor, which has reduced power consumption in a standby state.

[0002]

2. Description of the Related Art One of technical problems in various data processing devices such as a microprocessor is to reduce power consumption when the data processing device is in a standby state. Various devices have been conventionally devised to reduce power consumption. A typical method is to stop the clock supplied to the inside of the data processing device.

Usually, most of a plurality of internal modules constituting a data processing device are constituted by a sequential circuit, and the sequential circuit includes a plurality of combinational circuits and a plurality of storage elements (for example, a plurality of storage elements) for constituting a sequential circuit together therewith. ,
Latch or flip-flop) in many cases. In each internal module, the output of each storage element is connected to one of the combinational logic circuits, and the output of the combinational logic circuit is further connected to another storage element, and these storage elements are generated inside the data processing device. It operates according to the set clock or a clock externally provided. That is, the data held in one of the storage element paths is read out, input to one of the combinational circuits connected to the storage element, and the output of the combinational circuit is further input to another storage element.

Even if the supply of the clock to the module is stopped while the power supply voltage to the internal module is being supplied, the internal state of the internal module is maintained. Then, the operation of the internal module can be resumed. Therefore, conventionally, the supply of the clock to the internal module not used when the data processing device is in the standby state is stopped, thereby reducing the power consumption of the data processing device in the standby state. As a specific operation mode, for example, a CPU
Only in the sleep mode, the supply of the clock to it is stopped, and the clock is continuously supplied to the peripheral circuit module. There is a standby mode or the like in which the supply is stopped and the operation of the clock generation circuit is also stopped.

When the data processing device is in a standby state,
Even if the supply of the clock to the internal module is stopped, the level of the clock to be supplied to the internal module and the power supply voltage must be maintained in order for the storage element in the internal module to retain the information held up to that time. Cannot be lowered. Therefore, a leak current continues to be generated in the internal module, which results in power consumption. For this reason, an effective method for reducing the leak current of the circuit in the standby state is desired.

As one attempt for that, a method has been proposed in which a substrate bias is applied to a semiconductor integrated circuit on which a data processing device is mounted during standby. For example, Kuroda et al., “50% power saving circuit maintaining speed” (IEICE Technical Report, ED95-38, 1995-06, pp. 9-1)
See 5).

In recent years, rewritable nonvolatile memories have been increasingly mounted on microprocessors in consideration of various conveniences. Non-volatile memory types include EPROM, EEPROM, and FL.
Although there is an ASH memory or the like, there are limitations on the number of rewrites and inconvenience of the writing method. However, recently, a ferroelectric memory (FRAM) has emerged as a non-volatile memory whose number of rewrites, writing, and reading have approached that of a DRAM. Since FRAM is non-volatile,
Since a refresh operation is not required for holding data, the power consumption of this memory during standby can be extremely small, and the access time is equivalent to that of a DRAM.
There is also an advantage that the cell area is significantly smaller than that of the RAM. For details of FRAM, refer to “Ferroelectric Thin-Film Memory” edited by Shiozaki et al.
2-260).

Another technical problem in various data processing devices such as a microprocessor is to reduce a test time for detecting a circuit failure. Conventionally, methods mainly used for detecting a failure of a microprocessor include:
There is a method of providing a test pattern from outside the microprocessor. However, this method has a problem in that the amount of test patterns from the outside becomes enormous as the microprocessor becomes faster and more highly integrated, thereby increasing the test time. In particular, it is known that generation of a test pattern for detecting a failure in a sequential circuit is more difficult than generation of a test pattern for detecting a failure in a combinational circuit. For this reason, recently, many microprocessors have constituted a sequential circuit with a plurality of logic circuits and a plurality of flip-flops connected thereto as described above, and have provided a scan circuit for the flip-flops. As a result, an arbitrary value can be set to these flip-flops, so that the failure detection of the sequential circuit is facilitated, and the problem of failure detection is reduced to a problem of only the combinational circuit.

As a recent technique for detecting a fault in the combinational circuit at high speed, a built-in self-test circuit BIST is used.
(Built-In Self-Test). The BIST is a module built in the processor. This module generates a random pattern, gives the pattern to the combinational circuit, receives the output from the combinational circuit, compresses the result, and outputs the result to the outside. Such an operation is performed. Using this output, the presence or absence of a fault on the microprocessor is determined. This BIS
For more information on T, see "A Tutorial on B
uilt-InSelf-Test Part 1:
Principles "(IEEE DESIGN &
TEST OF COMPUTERS, MARC
H, 1993, pp. 139-157. 73-82) and "A Tuto
real on Built-In Self-Test
Part 2: Applications ”(IEEE
EDESSIGN & TEST OF COMPUTER
RS, JUNE, 1993, pp. 69-77).

Even if this technique is used, it is necessary to supply a large number of test patterns from the BIST circuit to the module to be inspected and to collect response data corresponding to the test patterns from the module to be inspected to the BIST circuit. To speed up the inspection, it is desirable to speed up the supply of these test patterns and the collection of response data for each.

[0011]

When the processor is on standby,
Even in the conventional method of stopping the clock supply to the unused internal modules, power consumption occurs due to leakage current during standby. It is clear that as processors become more highly integrated and operate at higher speeds, the ratio of the power consumption due to the leakage current to the total power consumption of the processor will increase.

An object of the present invention is to provide a data processing device capable of further reducing power consumption during standby.

A more specific object of the present invention is to provide a data processing device capable of further reducing power consumption during standby by adding a relatively simple circuit.

Another object of the present invention is to provide a data processing device capable of supplying test patterns and collecting response data for each of them at high speed in failure detection using a built-in self-test circuit.

[0015]

In order to achieve the above object, a processor for executing an instruction in a data processor according to the present invention comprises a plurality of combinational logic circuits and a plurality of storage elements combined therewith. This data processing device saves a plurality of internal data held in the plurality of storage elements to the standby memory, and later saves the plurality of internal data held in the plurality of storage elements to the standby memory. A save / restore circuit that restores the saved plurality of internal data to the plurality of storage elements, and supplies a power supply voltage for an save state to the processing device after the save / restore circuit saves the plurality of internal data; A power supply for supplying to the processing device such that a power supply voltage for normal operation is supplied to the processing device before the plurality of saved internal data is recovered by the save / restore circuit. And a power supply switching circuit for switching a.

In particular, in a desirable mode of the present invention, when saving the plurality of internal data held in the plurality of storage elements, the save / recovery circuit sequentially scans out the internal data and saves the internal data. A scan circuit for sequentially scanning in the plurality of saved internal data into the plurality of storage elements when recovering the plurality of internal data saved in the memory to the plurality of storage elements; When saving the plurality of internal data held in the memory, the plurality of internal data scanned out from the plurality of storage elements are sequentially written to the standby memory, and the plurality of internal data saved in the save memory are written. A memory for sequentially reading out the plurality of saved internal data when the internal data of the plurality of storage elements are restored to the plurality of storage elements; And a control circuit.

In particular, in another desirable mode of the present invention, the evacuation memory is a rewritable nonvolatile memory,
Preferably, it comprises a ferroelectric memory.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a data processing apparatus according to the present invention will be described in more detail with reference to embodiments shown in the drawings.

<Embodiment of the Invention> (1) Outline of Apparatus In FIG. 1, reference numeral 101 denotes a microcomputer according to the present invention. It is mounted on one large-scale integrated circuit (one chip). The microcomputer 101 includes:
CPU core 114, cache 122, RAM 12
7 are provided. The RAM 127 is a RAM used as a part of the main memory of the microprocessor 101, and holds data used by the CPU core 114.
Most of the remaining main memory is realized by a RAM (not shown) provided separately from a chip on which the microprocessor 101 is mounted. Cache 12
2 is a RAM 127 and an external RAM (not shown)
Is a cache that holds a copy of a part of the data in the main memory realized by.

The CPU core 114 executes a microinstruction required by the microcomputer. In the present embodiment, the ROM storing the microinstruction is provided outside the microcomputer, and is provided for simplification. Not shown in FIG.

The control circuit 103 includes the microprocessor 1
01 is a circuit for controlling execution of a save operation, a recovery operation, and a test operation. This circuit includes the microprocessor 10
Before putting the CPU 1 into the standby state, some internal modules that are not used when the microprocessor 101 is in the standby state, specifically, the internal data of the CPU core 114, the cache 122, and the RAM 127 are transferred via the path switch 112. To the ferroelectric memory 110. For this standby operation, the test clock TCLK is generated by the clock generation circuit 104, and the test clock TCLK is supplied to the internal module during the standby operation until all the internal data is on standby.
Thereafter, the microprocessor 101 is set in a standby state.
In the standby state, the power supply switching circuit 146 interrupts the supply of power to the internal modules not used during standby, such as the internal modules, the ferroelectric memory 110, the path switch 112, and the BIST circuit 132. Before returning the microprocessor 101 from the standby state to the normal operation state, supply of power to these internal modules is restarted by the power supply switching circuit 146, and the internal data saved in the ferroelectric memory 110 is transferred to the CPU core 114, The cache 122 and the RAM 127 are restored via the path switch 112.

The ferroelectric memory 110 is provided for holding the internal data to be saved in the microprocessor 101 with low power consumption. The ferroelectric memory 110 is connected to the pass switch 112 in the save operation, the recovery operation, and the test operation. During this time, it is used for data transfer between the some internal modules and the ferroelectric memory 140. Here, the ferroelectric memory is a non-volatile memory utilizing the hysteresis characteristics of the ferroelectric insulating film. Although there are several types of ferroelectric memories as described in the above-cited documents, in this embodiment, any type can be used in principle.

The clock generation circuit 104 includes the control circuit 10
Under the control of 3, the supplied clock can be switched. That is, during the normal operation, the normal operation clock CLK is supplied to various internal modules inside the microprocessor through the common line 107, and during the save operation, the recovery operation, and the test operation of the microprocessor 101, A test clock TCLK having the same frequency as the normal clock is output, and the control circuit 103
Are specific internal modules in the microprocessor 101, here the CPU core 114 and the cache 12 which are involved in the save operation, the recovery operation, and the test operation.
2 or the RAM 127 is selectively supplied with the test clock.

When the microprocessor 101 is in a standby state, the clock generation circuit 104 includes an internal module other than the control circuit 103 in the microprocessor 101, specifically, the CPU core 114 and the cache 12
2. Normal clock CLK to RAM 127, ferroelectric memory 109, path switch 112, and BIST circuit 132
Is stopped under the control of the control circuit 103. For this purpose, the CPU core 114, the cache 122, the RAM 1
The line 107 for supplying the normal clock CLK from the clock generation circuit 104 to an internal module other than the control circuit 103 such as 27 is provided separately from the signal line 151 for supplying the normal clock CLK to the control circuit 103 from the clock generation circuit 104. Have been.

The power supply switching circuit 146 is externally supplied with a power supply 147 for normal operation and a power supply 148 for standby (which is equal to the ground potential). When the state is reached, the CPU core 114, the cache 12
2. The control circuit 10 which is in an unused state such as the RAM 127
3 and the power supply to the internal modules other than the clock generation circuit 104 is stopped under the control of the control circuit 103. Therefore, the CPU core 114, the cache 122, the RAM 1
27, ferroelectric memory 109, path switch 112, B
A line 149 for supplying a power supply potential to an internal module other than the control circuit 103 and the clock generation circuit 104 such as the IST circuit 132 is connected to the control circuit 103 and the clock generation circuit 104.
Are provided separately from the line 147 for supplying the power supply potential to the power supply. Note that the control circuit 103 and the clock generation circuit 104
, Power for normal operation is always supplied via a line 147. As described above, while the microprocessor 101 is in the standby state, the control circuit 103 and the clock generation circuit 104
Power consumption due to leakage current in other internal modules.

Generally, an internal module constituting a data processing device includes a plurality of random modules and a macro module. Here, the random module is a module having a sequential circuit as a main component, and is usually a module generated by automatic logic synthesis. In the present embodiment, this sequential circuit includes a plurality of storage elements (here, assumed to be flip-flops) and a plurality of combinational logic circuits interconnecting them. The macro module refers to a module having a memory such as a ROM or a RAM as a main component. The number of these modules depends on the size of the data processing device. In FIG. 1, the CP
The U core 114 is a random module, and the cache 112 and the RAM 127 are macro modules.

In the present embodiment, a plurality of internal data held by each of a plurality of storage elements of a sequential circuit constituting a random module such as the CPU core 114 are sequentially saved in a predetermined order. A scan circuit for sequentially recovering the saved internal data to each storage element is used. In addition, by sharing the main part of the scan circuit with the scan circuit used for the test operation, the above-described save / recovery is realized with the addition of a small number of circuits.

The BIST circuit 132 checks the microprocessor test with the path switch 112 and the ferroelectric memory 1.
40 is used. At this time, the ferroelectric memory 140 is used as a buffer for holding a plurality of test patterns and a buffer for holding a plurality of response data from the CPU core 114 for the plurality of buffers. Less than,
The details of the apparatus of FIG. 1 and its operation will be further described.

(2) Saving of Internal Data (2A) Activation of Standby Operation The transition of the microprocessor 101 to the standby state and the transition to the normal state are performed by a line 102 from another processor (not shown).
Is started by a stop signal STP and a start signal START given to the control circuit 103 through the control circuit 103. Further, B
A test start request TEST is also provided from the IST circuit 132 to the control circuit 103 via the line 108.

Referring to FIG. 4, in the control circuit 103,
The start circuit 401 receives the stop signal STP and the start signal STAR.
T, the test start request TEST is received, and the reception of each signal is notified to the state machine 405 via the line 403. The state machine 405 controls the control circuit 1 so that an operation corresponding to the received request is executed.
Various circuits in 03 are activated via a line 408 at timings determined according to the respective circuits.

Specifically, upon receiving the start signal START, the start circuit 401 starts the operation of saving the internal data of the internal module to be saved as follows. FIG. 6 shows a timing chart of some signals related to the save operation.

The starting circuit 401 first outputs a request for generating a test clock to the clock switching control circuit 404 via the line 402. Clock switching control circuit 40
In response to this request, 4 supplies a request for generating a test clock to the clock generation circuit 104 via the line 105 until the standby operation is completed in all the internal modules for which the save operation is to be performed. The clock generation circuit 104
In response to this test clock generation request, the test clock TCLK is supplied to the control circuit 103 via the line 106, and the ferroelectric memory 110 and the path switch 11
2. An internal module, such as the BIST circuit 132, used during an operation other than the normal operation is also provided via the line 106.
The test clock TCLK is supplied until all save operations of the internal module to be saved and recovered are completed.

Further, the activation circuit 401 instructs the state machine 405 to start the save operation via a line 403. The state machine 405 controls various circuits in the control circuit 103 in response to the instruction to start the save operation. First, the module designation circuit 407 is instructed to select a module for the save operation.

In response to this instruction, the module specifying circuit 407 responds to the instruction by an internal module to be subjected to the save operation, in this example, the CPU core 114, the cache 122, and the RAM.
127 are sequentially selected according to a predetermined order. When the save operation in the selected internal module is completed, the next internal module is selected. Module designation circuit 407
Are the CPU core 114, the cache 122, the RAM 12
7 are selected, the select signal TSEL
1, TSEL2, TSEL3 are connected to lines 409, 410, 41
Output to 1. The module specifying circuit 407 continues to output a select signal for each internal module for a period necessary for saving the internal data in each internal module until the save operation in each internal module is completed.

The test clock supply circuit 420 includes a plurality of As corresponding to internal modules to be subjected to the evacuation / recovery operation.
ND gates 415A, 415B, and 415C. These AND gates are connected to a test clock TCLK supplied by the clock generation circuit 104 and the select signal TSE.
One of L1, TSEL2, and TSEL3 is supplied. Thus, the AND gates 415A, 415B, 41
5C, when the corresponding CPU core 114, cache 122, and RAM 127 are selected, the test clocks TCLK1, TCLK2, and TCLK are supplied to the corresponding internal module via lines 136, 137, and 138, respectively.
CLK3. Thus, the reading of the internal data in each internal module is sequentially activated.

(2B) Reading of Data from CPU Core 114 Referring to FIG. 2, in the normal operation state, the CPU core 114 is supplied with the normal operation power from the power supply switching circuit 146 via the line 149 to generate the clock. It operates in response to a normal operation clock CLK supplied from circuit 104 via line 107. The CPU core 114 operates in response to the test clock TCLK1 supplied from the control circuit 103 via the line 136 in the above-described save operation, recovery operation, and test operation.

The CPU core 114 includes a circuit for decoding an instruction, a circuit for executing the decoded instruction by dividing it into a plurality of pipeline stages, a plurality of arithmetic units for executing an operation required by the decoded instruction, or It is composed of a plurality of basic circuit parts consisting of a plurality of registers and the like used in the instruction, and most of these basic circuit parts are
It is composed of a sequential circuit.

During normal operation, the CPU core 114 reads data DO2 from the cache 122 and the RAM 127 via the buses 126 and 133, respectively.
Alternatively, DO3 is received, and this data is input to one appropriate basic unit circuit. The output of the basic unit circuit is C
The output data DI2 or DI3 from the PU core 114 is supplied to the cache 122 or the RAM 127 via the bus 118 or 119, respectively. Selection of a basic unit circuit for supplying data input to the CPU core 114 or selection of a basic unit circuit for supplying data to be output from the CPU core 114 is performed by a switch (not shown).

In the present embodiment, the sequential circuit of each basic circuit portion includes a plurality of flip-flops (F
F) and a plurality of combinational circuits. In the figure, a plurality of flip-flops (FF) 205 connected in this manner are used as an internal structure of L (L is a plurality) sequential circuits included in a plurality of basic circuit portions in the CPU core 114.
And a plurality of combination circuits 208 are schematically shown.

In the following, for simplicity, the flip-flop group of each sequential circuit is composed of M × M flip-flops, and each flip-flop group is arranged in M rows and M columns.
Here, M is equal to the number of bits of data supplied to each sequential circuit, and is equal to the data width of the buses 113 and 123 of the CPU core 114 in the present embodiment. Therefore, the M flip-flops in the same column hold one of the M bits of the same data. Further, the number of columns M indicates the number of stages of the logical operation executed in this sequential circuit. Therefore, during normal operation, this sequential circuit includes M FFs in the leftmost column in the figure.
Shows that M-bit data is supplied and M-bit data is output from the M FFs in the rightmost column of FIG.

Further, the flip-flop in the lowermost row of the flip-flop group of each sequential circuit is connected to the flip-flop in the uppermost row of the next sequential circuit. Thereby, the flip-flop group of the all-sequence circuit has the total number N × M (however,
Assume that N = L × M) flip-flops. The input line 203 during the save / recovery operation of the M flip-flops in the first row of the first sequential circuit is connected to the input buffer 201.
, And the output line 206 for the save operation of the M flip-flops in the bottom row of the final sequential circuit is connected to supply data to the output buffer 211.

Here, for each flip-flop, the address i of the row to which the flip-flop belongs and the address j of the column are assigned to the flip-flop, and the flip-flop is represented as FF [i, j]. The combinational logic circuit connected to the normal output side of the loop is denoted by C [i, j].

Each flip-flop has four inputs and two outputs and constitutes a scan latch. Each FF [i, j] has a normal operation clock CLK and a test clock TCLK
One is supplied via line 107 or 136, respectively.

In normal operation, M flip-flops having the same row address i operate so as to constitute one shift register. That is, each FF [i, j]
Captures the input 204 and outputs the output 2 of each FF [i, j] when the normal operation clock CLK is supplied thereto.
07 is supplied to the combinational logic circuit C [i, j] on the output side connected to the FF [i, j], and the output of the combinational logic circuit C [i, j] is supplied to the next FF [i, j +
1]. The input of the flip-flop FF [i, 1] at the head of each row is supplied to the CPU core 114 via the bus 1
This is one bit of data input from the switch 26 or 133 via a switch (not shown). The output of the last flip-flop FF [i, M] in each row is supplied to the bus 118 or 119 via a switch circuit (not shown). Thus, during normal operation, a number of flip-flops 205 in the CPU core 114 and a number of combinational logic circuits 2
08 performs one of the processes to be executed by the CPU core 114 on the data supplied from the bus 126 or 133, and outputs the result data.

When the number of flip-flops in any one of the sequential circuits is larger than the data width M, the flip-flop group forming the sequential circuit is divided into a plurality of partial flip-flop groups each having M or less stages. When connecting the input / output lines 203 and 206 for evacuation and recovery of each of the plurality of partial flip-flop groups to another flip-flop group, the partial flip-flop group is connected to one or other of the partial flip-flop groups. May be connected to form a matrix of M columns in FIG. Further, when the number of flip-flops in any one of the sequential circuits is smaller than the data width M, when the input / output lines 203 and 206 for save / recovery of the flip-flop group are connected to another flip-flop group, M in FIG. What is necessary is just to add to the flip-flop group via flip-flops of the number of stages less than M stages so as to form a row of columns, and connect the added flip-flop to the other flip-flop group.

As can be seen from the above description, the sequential circuit in the CPU core 114 contains information relating to one or more instructions being executed by the CPU core. In the case where the operation of the CPU core 114 is interrupted for power saving, the operation is shifted to the standby state, and the operation of the CPU core 114 is restarted after the power supply is cut off, the internal state of the CPU core 114 is changed to the standby state. Can be restored to the internal state of the CPU core 114 immediately before the transition to the state, the user can continue to use the microprocessor from the program execution state at the time of interruption. However, the flip-flops constituting these sequential circuits are volatile, and the power supply voltage is
When the information is no longer supplied to the core 114, the information held in these flip-flops disappears. For this purpose, in the present embodiment, before shutting off the power to the CPU core 114, the internal data held in the flip-flops of the plurality of sequential circuits in the CPU core 114 are saved, and the data is restored later. I have. In order to realize this saving, as described below, at the time of transition from the normal state to the standby state, the internal data held in these flip-flops are scanned out and saved, and the normal state is changed to the standby state. At the time of transition, a scan circuit that scans these saved internal data into these flip-flops is used.

When the test clock TCLK1 is supplied to each flip-flop, the N flip-flops having the same column address j operate so as to constitute one shift register. That is, each FF [i, j]
Captures the test input 203 when the test clock TCLK1 is supplied thereto, and outputs each FF [i, j].
Is supplied to the output FF [i + 1, j] connected to the FF [i, j]. Output buffer 2
11, the output signals 206 of the FFs [N, 1] to FF [N, M] are stored in parallel in synchronization with the test clock 106. That is, when the operation with the test clock starts, {FF [N, 1], FF [N, 2], ‥‥‥‥, FF [N, M]} ｛FF [N-1, 1], FF [N- 1,2], ‥‥‥‥, FF [N-1, M]｝ ｛FF [N-2, 1], FF [N-2, 2], ‥‥‥‥, FF [N-2, M ]:: The contents of all flip-flops are read out to the data bus 123 through the output buffer 211 in the order of {FF [1,1], FF [1,2], {, FF [1, M]}. The above-described operation of reading the internal data is performed by the CPU core 11.
4 is also used in the test operation.

At the time of the recovery operation described later, a plurality of internal data saved from all the sequential circuits in the CPU core 114 are supplied to the input buffer 201 via the bus 113 in the order in which the respective data are saved. Are sequentially transferred to all the flip-flops within, and as a result, the data saved from each flip-flop is restored to each flip-flop. That is, at the time of the saving operation, the data of the flip-flop of each sequential circuit in the CPU core 114 is sequentially scanned out to the output buffer 211 and further saved to the ferroelectric memory 140 via the data bus 123 and the path switch 112. . Note that the above-described internal data read operation is performed by the CPU.
It is also used during the test operation of the core 114.

As can be seen from the above description, in the present embodiment, the signal lines 203 and 206 interconnecting a plurality of flip-flops in a plurality of sequential circuits in the CPU core 114.
The clock supply circuit 420 and other circuits in the control circuit 103 that supply the test clock TCLK to these flip-flops sequentially scan out the data held by these flip-flops, or send the data to these flip-flops. This means that a scan circuit for sequentially scanning in is realized, and the internal data of these flip-flops are saved and recovered using the circuit.

As will be described later with respect to the test operation,
During the test operation of the CPU core, a control circuit is added so as to realize the scan-out operation required for the test operation by sharing the scan circuit. Therefore,
In the present embodiment, the main part of the scan circuit for saving and restoring is shared with the test scan circuit. This allows the CPU
The circuit for saving and restoring the internal data of the random module such as the core 114 is simplified.

(2C) Writing of Internal Data to the Ferroelectric Memory 110 When the internal data is read from the CPU core 114 to the bus 123, the multiplexer 1 in the path switch 112
30 selects the bus 123. After the internal data on the bus 123 is stored in the output register 129, the internal bus 14 in the ferroelectric memory 110 is passed through the data bus 128.
2 and further transferred to the ferroelectric memory cell array 140.
Are written sequentially.

The operation of the path switch 112 at this time is as follows.
It is controlled by the control circuit 103. That is, in the control circuit 103, the select signals TSEL1, TSEL2, or TSEL3 output earlier by the module designating circuit 407 are output.
(In this example, the select signal TSEL1) is output to the multiplexer 130 via the line 111, and the buses 123, 1
One of the buses 26 and 133 (in this example, the bus 123) designated by the select signal is selected. Further, the state machine 405 responds to the transition instruction from the start-up circuit 401 to the standby state, and outputs the first internal data from the internal module (in this example, the CPU core 114) during the evacuation operation to the multiplexer 130. In synchronization with the timing supplied to the output register 129 via
Register update control circuit 414 is activated via line 408 for a save operation. When activated for the save operation, the circuit 414 repeatedly generates a set signal instructing to take in the internal data on the bus selected by the multiplexer 130 in synchronization with the test clock TCLK. It is supplied to the output register 129.
In response to the set signal, the output register 129 sequentially takes in the internal data sequentially supplied from the multiplexer 130 and supplies the data to the internal bus 142 of the ferroelectric memory 110 via the bus 128.

The ferroelectric memory 110 has the output register 12
9 is sequentially written to the ferroelectric memory cell array 140 via the internal bus 141. This writing is controlled by the control circuit 103. That is, the state machine 405 in the control circuit 103 supplies the first internal data to be saved to the internal bus 142 in the ferroelectric memory 110 in response to the start instruction of the standby operation from the start circuit 401. The ferroelectric memory control circuit 4
13 and the address generation circuit 412 are activated via line 408 for a write operation. Ferroelectric memory control circuit 4
When activated for the write operation, the write signal 13 repeatedly generates a write signal in synchronization with the test clock TCLK, and supplies the write signal to the ferroelectric memory 110 via the line 109. When activated for a write operation, the address generation circuit 412 starts from a head position in the ferroelectric memory cell array 140 and outputs an address of a continuous save area having a predetermined size to the test clock TCLK.
And is supplied to the ferroelectric memory cell array 140 via the line 139. The size of the save area is determined in advance for each internal module depending on the amount of all internal data to be saved from the internal module. The ferroelectric memory control circuit 413 and the address generation circuit 412 generate these write signals and write addresses in synchronization with the subsequent internal data to be saved being supplied to the ferroelectric memory cell array 140. I do.

(2D) Saving of Internal Data of Cache 122 The cache 122 has a memory for holding a plurality of cached data and a memory for holding data for searching each data. After the saving operation for the CPU core 114 is completed as described above,
These data in the cache 122 are saved.
That is, in the control circuit 103, the CPU core 114
When the saving of the internal data of the cache 122 is completed, the module designating circuit 407
2 and the test clock supply circuit 409 supplies the test clock TCLK2 to the cache 122. Test clock TCLK for cache 122
The state machine 405 activates the macro module control circuit 406 in synchronism with the timing at which the 2 starts to be supplied. This circuit 406 sequentially generates the address of the memory holding the internal data in the cache 122 and supplies the address to the cache 122 via the line 144. further,
A read request is repeatedly generated and supplied to the cache 122 via the line 135. Thus, the cache 122
Is read to the bus 126, and the ferroelectric memory 110 is read in the same manner as the internal data of the CPU core 114.
Evacuated to The internal structure of the cache 122 required for this save operation is the RAM 127 described below.
Since it is the same as the internal structure necessary for the retreat operation, its detailed description is omitted.

(2E) Saving the Internal Data in the RAM 127 After the saving operation for the cache 122 is completed as described above, the saving operation for the RAM 127 is performed in the same manner as in the case of the cache 122.

Referring to FIG. 3, the RAM 127 includes a memory cell array 303, an input buffer 301 for reading and writing data from and to the memory cell array 303, and an address latch 3
04 and an output buffer 306. OR gate 3
The normal operation clock CLK is supplied from the clock generation circuit 104 via the line 107 during normal operation to each of the devices 07, 308, and 309, and is controlled during normal operation such as save operation, recovery operation, or test operation. The test clock TCLK3 is supplied from the circuit 103 via the line 106. The address latch 304 stores an address 14 to be accessed from the control circuit 103 at times other than the normal operation.
4 is given. The control circuit 103 further provides a read request or a write request via a line 135.

The address latch 304 is connected to the control circuit 103
In synchronization with the test clock TCLK3 given by
A memory cell designation address 144 given from the control circuit 103 is held. When the request given from the control circuit 103 via the line 135 is a write request, the memory cell array 303 writes the data fetched into the input buffer 301 into the address position indicated by the address latch 304. Otherwise, the data already written at the address position indicated by the address latch 304 is read.

When the macro module control signal 135 supplied from the control circuit 103 indicates a read operation, the output buffer 306 outputs the data read from the memory cell array 303 to the test clock TCLK3 input to the OR gate 309 or to the normal mode. The data is captured in synchronization with the operation clock CLK and output to the bus 133. Input buffer 30
1 is the test clock T input to the OR gate 307
The data on the data bus 119 is held in synchronization with CLK3.

Therefore, during the standby operation, data stored in the memory cell array 303 is sequentially read out to the bus 133. These data are saved in the ferroelectric memory 110 by the method already described. At the time of the recovery operation described later, the memory cell array 303
9. The data supplied via the input buffer 301 is sequentially stored at the address indicated by the address latch 304.

(2F) Power supply cutoff, test clock supply stop In the control circuit 103, the state machine 405 responds to the above-mentioned save operation start instruction from the start-up circuit 401 and generates a plurality of internal modules to be saved. Upon completion of the save operation, the power supply control circuit 421 is activated via the line 408 for the save operation. Power control circuit 421
Requests the power supply switching circuit 146 to change the power supply voltage via the line 145 when activated for the save operation.
The power supply switching circuit 146 selects the standby power supply 148 (which is equal to the ground potential) according to the power supply change request by the line 145, and eventually, the CPU core 114, the cache 122, the RAM 127, the path switch 112, and the ferroelectric substance. The power supply to the memory 110 and the BIST circuit 131 is stopped. As a result, it is possible to suppress the leakage current during standby in these modules. Note that power for normal operation is always supplied to the control circuit 103 and the clock generation circuit 104.

When all the necessary internal data have been saved, the state machine 405 notifies the start circuit 401 of the completion of the save. When the start circuit 401 receives this notification, the clock switching control circuit 404 performs the save operation. Notifying the completion, the clock switching control circuit 404 requests the clock generation circuit 104 to end the generation of the test clock. Thus, no test clock is generated. The standby operation ends as described above.

(3) Recovery of Internal Data (3A) Restart of Power Supply and Activation of Recovery Operation When a start signal START is supplied from another processor (not shown) to the control circuit 103 via the line 102, the start circuit 401 Activate the transition operation (recovery operation) to the normal state. Since the operation of the control circuit 103 at this time is similar to the retreat operation, only the points different from the retreat operation will be briefly described below. FIG. 7 shows a timing chart of some signals related to the recovery operation.

The activation circuit 401 first requests the clock switching control circuit 404 to generate a test clock in the same manner as in the save operation, and further, the activation circuit 401
The start of the recovery operation is instructed to the state machine 405 through the line 403. The state machine 405 controls various circuits in the control circuit 103 in response to the instruction to start the recovery operation.

The state machine 405 activates the power supply control circuit 421 via the line 408 for the recovery operation in response to the instruction to start the recovery operation. Power supply control circuit 42
When activated for the recovery operation, 1 requests the power supply switching circuit 146 for a power supply voltage change request PWR via the line 145. The power supply switching circuit 146 is connected to this line 145
Power supply 1 for normal operation according to power supply change request PWR
47, and eventually, the CPU core 114, the cache 1
22, the power supply to the RAM 127, the path switch 112, the ferroelectric memory 110, and the BIST circuit 131 is restarted.

Further, it instructs module specifying circuit 407 to select a module for the recovery operation. The operation of the circuit 407 at this time is the same as that at the time of the save operation, and the test clock supply circuit 420
TCLK3 is sequentially output from K1.

(3B) Reading of Saved Data from Ferroelectric Memory 110 The state machine 405 responds to the start instruction of the recovery operation from the start-up circuit 401 and the ferroelectric memory control circuit 413 and the address generation circuit 412. Is activated for a read operation via line 408. When activated for the read operation, the ferroelectric memory control circuit 413 repeatedly generates a read signal in synchronization with the test clock TCLK and supplies the read signal to the ferroelectric memory 110 via the line 109. When activated for the read operation, the address generation circuit 412 synchronizes the address of the above-described save area in the ferroelectric memory cell array 140 with the test clock TCLK, similarly to the case where the address generation circuit 412 is activated for the write operation. And supplied to the ferroelectric memory cell array 140 via line 139. In this way, the internal data saved in the ferroelectric memory cell array 140 is sequentially read in the same order as the saving order of each data, and the internal bus 1
The data is read out to the input register 115 in the path switch 112 via 41, 142 and 117.

(3B) CPU core 114, cache 1
22, writing of save data to the RAM 127 The operation of the path switch 112 during the recovery operation is performed by the control circuit 1
03. Unlike the save operation, in the control circuit 103, the state machine 405 responds to the start instruction of the recovery operation from the activation circuit 401, and
In synchronization with the timing at which the first save data from the ferroelectric memory 110 is supplied to the input register 115, the register update control circuit 414 is activated via a line 408 for a recovery operation. This circuit 414 repeatedly generates a set signal for instructing the capture of the save data on the bus 117 in synchronization with the test clock TCLK, and supplies it to the input register 115 via the line 416. Input register 11
In response to the set signal, 5 sequentially fetches save data sequentially supplied via the bus 117 and supplies the data to the multiplexer 116. The module specifying circuit 407 generates select signals TSEL1, TSEL2, or TSEL3 output via the line 111 as in the case of the standby operation, and the respective signals are supplied to the multiplexer 116. The multiplexer 116 includes a CPU core 114,
The bus 11 connected to the cache 122 and the RAM 127
3, 118 and 119 are selected according to the select signal supplied from the line 111. Thus, the CPU core 11
The internal data saved from 4 is sequentially supplied to the internal data and written into a plurality of flip-flops. Thus, the internal data of the CPU core 114 is recovered. Accordingly, the state of the CPU core 114 becomes a state immediately before transition to the save state, and the CPU core 114 can resume the operation from that state.

Thereafter, the internal data saved from the cache 122 is sequentially supplied to the internal data and written into the memory therein. Similarly, the internal data saved from the RAM 127 is sequentially supplied to the internal data and written into the memory cell array 303 (FIG. 3) therein. Cache 12
2. When recovering the internal data to the RAM 127,
In the control circuit 103, the state machine 405 activates the macro module control circuit 406 for recovery. This circuit 406, when activated for recovery,
Write request via the cache 122 and the RAM 12
7 is different from that during the evacuation operation.

(3C) Resumption of Supply of Normal Clock When all the necessary internal data have been recovered, the state machine 405 notifies the start-up circuit 401 of the completion of the recovery. The switching control circuit 404 requests the completion of the recovery operation, and the clock switching control circuit 404 requests the clock generation circuit 104 to switch the clock. The clock generation circuit 104 stops the generation of the test clock, and furthermore, the CPU core 114 and the cache 1
22. Start supplying a normal clock to the RAM 127.
Thus, the recovery operation ends.

(4) Test Operation Failure detection is performed using the BIST circuit 132. Referring to FIG. 5, when receiving a start signal 143 from an external processor (not shown), the self-test start circuit 516
Through 08, a test operation start instruction is notified to the control circuit 103 in FIG. In the control circuit 103, the starting circuit 4
01 instructs the clock switching circuit 404 to switch the clock in response to the test start instruction. As in the case of the above-described recovery operation, the clock repetition circuit 404 switches the clock to the clock generation circuit 10.
Instruct 4 In the same way as in the case of the recovery operation,
The supply of the normal clock to the CPU core 114, the cache 122, and the RAM 127 via the line 107 is stopped, and the test clock TCLK is supplied to the control circuit 103, the ferroelectric memory 110, and the path switch 112 instead.

In the control circuit 103, the starting circuit 401
The state machine 405 instructs the BIST control circuit 419 to start a test operation. This circuit 419 is connected to line 15
Inform the self test state machine 514 via 0 that the self test has started. The self-test state machine 514 controls the control signals 510, 504, 505, 5
The control of the pattern generator 509, the internal bus output control circuit 503, the data buffer 506, the pattern compressor 513, and the external bus output control circuit 519 is performed using 11, 11 and 518. First, using the control signal 510, the pattern generator 50 is used.
9 is started. When activated, the pattern generator 509 sequentially generates different portions of the test pattern data,
The signal is passed to the internal bus output control circuit 503 through the signal line 508. The internal bus output control circuit 503 transmits the different portions of the test pattern data through the signal line 502 to the internal bus 5.
01 sequentially. The different portions of the test pattern are sequentially stored in a test pattern buffer area of a predetermined size in the ferroelectric memory 110. In the present embodiment, it is assumed that this buffer area starts from the head position of the ferroelectric memory 110.

The writing of the test pattern into the ferroelectric memory 110 is performed by the control circuit 103 as follows. In the control circuit 103, the state machine 405
Starts the ferroelectric memory control circuit 413 and the address generation circuit 412 for writing data. When activated for writing, these circuits repeatedly supply a write request to the ferroelectric memory 110 and sequentially supply different write addresses to the ferroelectric memory 110, as in the case of the save operation. Thus, different portions of the test pattern sequentially transferred from the internal bus output control circuit 503 in the BIST circuit 132 are sequentially written to the ferroelectric memory cell array 140 in the ferroelectric memory 110.

In the control circuit 103, the state machine 4
Step 05 repeats writing to the ferroelectric memory 110 for each of the plurality of test patterns. When the writing of these test patterns is completed, the ferroelectric memory control circuit 413 and the address generation circuit 412
As in the case of the recovery operation, it starts up for data reading. When activated for reading, these circuits repeatedly supply a read request to the ferroelectric memory 110 and sequentially supply different read addresses, as in the case of the recovery operation. Thus, different portions of one test pattern written in the ferroelectric memory cell array 140 are sequentially read from the ferroelectric memory 110.

In the control circuit 103, the state machine 4
In step 05, the module specifying circuit 407 and the register update control circuit 414 are activated for the test operation in the same manner as the recovery operation, in synchronization with the reading of the leading partial data of the one test pattern. The register update control circuit 414 instructs, via the input register line 417, the capture of the partial data read from the ferroelectric memory 110. In this embodiment, assuming that only the CPU core 114 having a built-in scan circuit is a circuit to be tested, the module designation circuit 407 selects this CPU core 114 when activated for a test operation, and The signal TSEL1 is output to the multiplexer 116 and the CPU core 114. When there are a plurality of test target modules, those modules are sequentially selected in the same manner as in the recovery operation.

In this way, different portions of the test pattern data read from the ferroelectric memory 110 are sequentially supplied to the CPU core 114, and further, the test clock TC
LK1 is supplied to the CPU core 114. CPU core 1
Numeral 14 sequentially scans in different portions of the test pattern data. As described above, the CPU core 11
4 incorporates a scan circuit that connects a plurality of flip-flops and sequentially reads internal data held by the flip-flops, or sequentially scans in a plurality of data into the flip-flops. The scan-in of the test pattern data is realized by controlling the scan circuit in the same manner as the operation of recovering the internal data described above with reference to FIG.

Thereafter, the control circuit 103 causes the flip-flops to take different portions of the response data of the plurality of combination circuits with respect to the test data.
Specifically, each flip-flop FF [i, j] in FIG.
Of the combinational logic circuit C [i, j-1] connected via the data input terminal 204 during normal operation of this flip-flop. What is necessary is just to make this flip-flop hold | maintain. The circuit for generating the set signal for this purpose is omitted in FIG. 2 for simplicity, but it is well known that the different portions of the response data to the test data are sequentially taken into the flip-flops.

Thereafter, the control circuit 103 sequentially scans out different portions of the fetched response data. The operation at this time is the same as the above-described internal data saving operation. Thus, the CPU core 114 sequentially outputs different portions of the generated response data to the bus 123.

In other words, in the case of the test operation just described, when the scan data is scanned in to the CPU core 114 and the response data is scanned out, the scan circuit is operated in the same manner as in the above-described recovery operation and save operation. The same operation is performed, and before the scan circuit scans out, a different portion of the response data corresponding to the test pattern data may be held in the flip-flop.
Thus, in the present embodiment, two operations are realized by sharing the scan circuit at the time of the evacuation / recovery operation and at the time of the test operation, and changing only the control of the scan circuit.

In the control circuit 103, the state machine 405 sequentially writes different portions of the response data in the response data buffer area in the ferroelectric memory in the same manner as in the above-described save operation. In the present embodiment, it is assumed that the buffer area for response data starts from the head position of the ferroelectric memory cell array 140 and is the same area as the buffer area for test pattern described above. For this reason, after all of the different portions of the test pattern data held in the ferroelectric memory cell array 140 have been read, supply of the different portions of response data to the ferroelectric memory cell array 140 is started. like,
The total number of different portions of the test pattern data held in the ferroelectric memory cell array 140 is determined.

In the control circuit 103, the state machine 4
In step 05, the above operation is repeated for a plurality of test patterns held in the ferroelectric memory 110 after partial data having different response data is written in the ferroelectric memory cell array 140. Thereafter, the ferroelectric memory control circuit 413 and the address generation circuit 412 are activated so that different partial data of response data for each test pattern is sequentially read from the ferroelectric memory 110.
However, unlike when reading out test pattern data,
The path switch 112 does not capture these response data. First, the ferroelectric memory cell array 14
Different parts of one response data written to 0 are sequentially read out to the bus 142 via the bus 141. BIS
In the T circuit 132, the self test state machine 51
4 instructs the data buffer 506 via the line 505 to take in different partial data of the response data sequentially supplied via the bus 131. Each response pattern taken into the data buffer is compressed by the pattern compressor 513, and further, by the external bus output control circuit 519.
It is supplied to an external processor (not shown) for failure analysis. The ferroelectric memory cell array 140 repeats reading the other response data written therein,
The T circuit repeats the above operation for each response data.

As described above, in the present embodiment, a plurality of test patterns are successively transferred from the BIST circuit 132 to the buffer area in the ferroelectric memory 110.
Different portions of each test pattern data are continuously transferred from the buffer area to the test target circuit. further,
Different partial data of response data from the test target circuit is continuously transferred to the buffer area in the ferroelectric memory 110. After the above operation is repeated for different test patterns in the buffer area, a plurality of response data corresponding to those test patterns are transmitted from the buffer area to the BI pattern.
The data is continuously transferred to the ST circuit 132. Accordingly, one test pattern data is supplied to the test target circuit, and response data is supplied to the test data from the test target circuit.
The test can be performed much faster than when a series of operations of supplying to the T circuit is repeated for different test pattern data.

<Modifications> The present invention is not limited to the above-described embodiments, but includes the following modifications and other modifications without departing from the spirit of the present invention.

(1) In the above embodiment, an example has been described in which data in all flip-flops constituting all the sequential circuits in the CPU core is saved and recovered. A plurality of flip-flops constituting a minimum required part of the sequential circuit when transitioning to the state are selected in advance, and only a part of these flip-flops is selected.
It goes without saying that the scan circuit described in the embodiment may be used.

(2) The present invention can be applied to data processing devices other than microcomputers, for example, digital signal processors and other processors.

(3) In the above-described embodiment, during standby, C
Although the power supply voltage is not substantially supplied to the PU core or the like, the power saving effect can be obtained even if a voltage lower than the power supply voltage for normal operation is supplied.

(4) F instead of ferroelectric memory 103
It is also possible to use a nonvolatile memory such as a LASH memory. However, the operation speed of the ferroelectric memory 103 is
It is superior to a FLASH memory or the like in cell area, number of repetition operations, and the like.

(5) The microcomputer 101 or other data processing devices can be formed on a plurality of chips. However, when mounted on one chip, there are advantages such as cost reduction, security enhancement, and power consumption reduction.

(6) The state transition signal 102 may be given from a random module during normal operation.

(7) The test start signal 143 can be generated by any random module in the microprocessor 101.

(8) The form of the flip-flop constituting the sequential circuit of the CPU core 114 may be a form to which a set signal or the like is added for normal operation in addition to the form shown in FIG.

(9) While the data processing device 101 is in the normal operation mode, the ferroelectric memory 110 can be used as a ROM. For this purpose, program instructions or data not directly related to the save operation and the recovery operation are stored in a specific area of the memory in advance.

[0092]

According to the present invention, the contents of the sequential circuit can be saved in the data saving memory when the data processing device is on standby, and the power supply voltage can be reduced during standby, so that the leakage current flowing through the sequential circuit during standby can be consumed. Power can be eliminated.

In particular, when the save / recovery circuit is constituted by a scan circuit, the structure of the save / recovery circuit can be simplified.

In particular, when a non-volatile memory is used as the data saving memory, the power consumption of the entire data processing apparatus during standby can be further reduced.

Further, when a ferroelectric memory is used as the non-volatile memory, power consumption during standby can be eliminated, and the transition of the data processing apparatus to the standby state or recovery from the standby state can be performed at high speed.

Further, a scan latch is used as a sequential circuit in the data processing apparatus, a ferroelectric memory is used as the memory for saving data, and a BIST circuit is provided in a chip. This ferroelectric memory is separated from the BIST circuit. A plurality of test pattern data supplied are used as a buffer for temporarily holding, and a plurality of response data output from the module to be inspected and to be transferred to the BIST circuit are temporarily stored. In this case, the failure can be detected at high speed.

[Brief description of the drawings]

FIG. 1 shows an overall view of a microprocessor according to the present invention.

FIG. 2 shows a detailed view of the CPU core described in FIG.

FIG. 3 is a detailed view of a RAM in FIG. 1;

FIG. 4 shows a detailed diagram of a control circuit in FIG.

FIG. 5 is a detailed diagram of a BIST circuit in FIG. 1;

FIG. 6 is a timing chart of various signals of the microprocessor of FIG. 1 at the time of transition from a normal state to a standby state.

7 shows a timing chart of various signals when the microprocessor of FIG. 1 transitions from a standby state to a normal state.

[Explanation of symbols]

 139 Address 144 Address 145 Power switch signal 147 Power supply for normal operation 148 Power supply for standby 205 Flip-flop (FF) 208 Combination circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location G06F 1/00 335C (72) Inventor Hiroyuki Tanigawa 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd.Semiconductor Division (72) Inventor Yasuhisa Shimazaki 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In-house Semiconductor Division, Hitachi Ltd. (72) Nobuyoshi Kobayashi, Kosui, Tokyo 5-20-1, Honmachi Semiconductor Division, Hitachi, Ltd.

Claims (15)

[Claims] 1. A processing device for executing an instruction, comprising:
One having a sequential circuit composed of a plurality of combinational logic circuits and a plurality of storage elements for forming a sequential circuit in combination therewith; an evacuation memory; and a plurality of internal circuits held in the plurality of storage elements Reading data, saving to the standby memory, reading the plurality of saved internal data from the saving memory,
A save / restore circuit for restoring the plurality of storage elements; and a power supply voltage for a standby state is supplied to the processing device after the plurality of internal data is saved by the save / recovery circuit. A power supply switching circuit for switching a power supply voltage to be supplied to the processing device so that a power supply voltage for normal operation is supplied to the processing device before the plurality of internal data is recovered. 2. The save / recovery circuit, when saving the plurality of internal data held in the plurality of storage elements, sequentially scans out the internal data and saves the plurality of internal data in the save memory. When restoring a plurality of internal data to the plurality of storage elements, a scan circuit for sequentially scanning in the plurality of saved internal data to the plurality of storage elements; and a plurality of the plurality of storage elements held in the plurality of storage elements. When saving the internal data, the plurality of internal data scanned out from the plurality of storage elements are sequentially written to the standby memory, and the plurality of internal data saved to the save memory is written to the plurality of memory devices. 2. The memory control circuit according to claim 1, further comprising: a memory control circuit for sequentially reading out the plurality of saved internal data when the storage element is restored. Data processing equipment. 3. The scanning circuit according to claim 2, wherein the plurality of storage elements include a plurality of signal paths for connecting an output of each storage element to an input of another storage element, and the plurality of storage elements are held in the plurality of storage elements. A clock supply circuit that supplies a scan clock to the plurality of storage elements when the internal data is saved and when the plurality of internal data saved in the save memory is restored to the plurality of storage elements. In response to the scan clock supplied when the internal data held in the plurality of storage elements is saved, the plurality of storage elements transfer the internal data held therein to the plurality of signal paths. And the scan clock supplied when the plurality of internal data saved in the save memory are restored to the plurality of storage elements. In response, the data processor according to claim 2 comprising an internal data sequentially read from the memory for the retreat from the element to realize a shift register for sequentially shifting in through the plurality of signal paths. 4. When testing the sequential circuit, different portions of test data are sequentially scanned into the plurality of storage elements, and different portions of response data from the plurality of combinational logic circuits to the scanned-in test data. And a test scan circuit for sequentially scanning out the different portions of the held response data, wherein the test scan circuit stores the test pattern in the plurality of storage elements. Is scanned in through the plurality of signal paths, and the response data is scanned out through the plurality of signal paths. When scanning out the response data, the plurality of storage elements are scanned A circuit for controlling the clock supply circuit so as to supply a clock; and after scanning the test pattern into the plurality of storage elements, the response data from the plurality of logic circuits to the scanned-in test pattern is written. 4. The data according to claim 3, further comprising a circuit for supplying a signal for causing the plurality of storage elements to hold different portions of the response data from the plurality of logic circuits before the scan-out, to the plurality of storage elements. Processing equipment. 5. The data processing device according to claim 1, wherein said save memory is a rewritable nonvolatile memory. 6. The data processing device according to claim 5, wherein said nonvolatile memory is a ferroelectric memory. 7. The data processing device according to claim 5, wherein said nonvolatile memory is a flash memory. 8. A random access memory for holding data used by the processing device; and evacuation of data stored in the random access memory to the standby memory before putting the processing device into a standby state. After the processing device is in a standby state, before the normal operation state, further comprising a memory data save and recovery circuit to restore the data of the random access memory saved in the memory for standby to the random access memory, The power supply switching circuit supplies the processing device with the power supply voltage for the normal operation in synchronization with switching between the power supply voltage for the normal operation and the power supply voltage for the standby state. 6. The data processing device according to claim 5, wherein the power supply voltage for the standby state is switched. 9. A cache for holding a copy of a part of the data of the random access memory, wherein the memory data save / recovery circuit is stored in the cache before the processing device is put into a standby state. A circuit for saving the information to the standby memory, setting the processing device in the standby state, and restoring the cache information saved in the standby memory to the cache before the normal operation state. Wherein the power supply switching circuit supplies the processing device with the power supply voltage for the normal operation and the power supply voltage for the standby state. 9. The data processing apparatus according to claim 8, wherein the power supply voltage for the standby state and the power supply voltage for the standby state are switched and supplied. 10. A pattern generator for generating random test pattern data to be provided to the processing device for failure diagnosis, a pattern compressor for compressing response pattern data corresponding to the random test pattern data, and testing the data processing device. A plurality of random pattern data sequentially generated from the pattern generator are sequentially transferred to the evacuation memory, and are further sequentially read from the evacuation memory and transferred to the processing device. Data transfer for sequentially transferring a plurality of response pattern data sequentially given from the processing device to the test pattern data to the buffer area in the evacuation memory, sequentially reading them from the memory, and sequentially transferring the read data to the pattern compressor. A plurality of random test circuits in the plurality of storage elements. A scan that scans in each of the pattern data, stores response pattern data from the plurality of logic circuits for the scanned-in random test pattern data in the plurality of storage elements, and scans out the stored response pattern data. The data processing device according to claim 1, further comprising a circuit. 11. The data processing device according to claim 1, wherein said data processing device includes a microprocessor. 12. A sequential circuit comprising a plurality of combinational logic circuits and a plurality of storage elements for combining them to form a sequential circuit; a non-volatile memory for evacuation; and a memory held by the plurality of storage elements. Read out the plurality of internal data, save the data to the standby memory, read the plurality of saved internal data from the save memory,
A save / restore circuit for restoring the plurality of storage elements; and a power supply voltage for a standby state is supplied to the sequential circuit after the plurality of internal data is saved by the save / recovery circuit. A power supply switching circuit for switching a power supply voltage supplied to the sequential circuit so as to supply a power supply voltage for normal operation to the sequential circuit before the plurality of internal data is recovered. 13. The save / recovery circuit, when saving the plurality of internal data held in the plurality of storage elements, sequentially scans out the internal data and saves the internal data in the save memory. When restoring a plurality of internal data to the plurality of storage elements, a scan circuit for sequentially scanning in the plurality of saved internal data to the plurality of storage elements; and a plurality of the plurality of storage elements held in the plurality of storage elements. When saving the internal data, the plurality of internal data scanned out from the plurality of storage elements are sequentially written to the standby memory, and the plurality of internal data saved to the save memory is written to the plurality of memory devices. 13. A memory control circuit for sequentially reading out the plurality of saved internal data when the storage element is restored. Placing the data processing device. 14. The scan circuit, wherein the plurality of storage elements include a plurality of signal paths for connecting an output of each storage element to an input of another storage element, and the plurality of storage elements are held by the plurality of storage elements. A clock supply circuit that supplies a scan clock to the plurality of storage elements when the internal data is saved and when the plurality of internal data saved in the save memory is restored to the plurality of storage elements. In response to the scan clock supplied when the internal data held in the plurality of storage elements is saved, the plurality of storage elements transmit the internal data held therein to the plurality of signals. The plurality of internal data saved in the save memory are sequentially shifted out through the path, and the scan clock supplied when the plurality of internal data is restored to the plurality of storage elements. In response to the click, the data processing device sequentially read internal data consists element to realize a shift register for sequentially shifting in through the plurality of signal paths according to claim 13 wherein the memory for the retreat. 15. When testing the sequential circuit, different portions of test data are sequentially scanned into the plurality of storage elements, and different portions of response data from the plurality of combinational logic circuits to the scanned-in test data. And a test scan circuit for sequentially scanning out the different portions of the held response data, wherein the test scan circuit stores the test pattern in the plurality of storage elements. Is scanned in through the plurality of signal paths, and the response data is scanned out through the plurality of signal paths. When scanning out the response data, the scan is stored in the plurality of storage elements. A circuit for controlling the clock supply circuit so as to supply a clock for the test, and after scanning the test pattern into the plurality of storage elements, the response data from the plurality of logic circuits to the scanned-in test pattern. 15. The circuit according to claim 14, further comprising a circuit for supplying a signal for causing the plurality of storage elements to hold different portions of the response data from the plurality of logic circuits to the plurality of storage elements before scanning out. Data processing device.