JP2021025974A - Semiconductor circuit device - Google Patents

Abstract

To reduce a time period from end of diagnosis by a logic BIST to restart of normal operation of a logic circuit included in a circuit block.SOLUTION: Attention has been paid to a fact that a register value inside a circuit block to be diagnosed by a logic BIST section 3 is set to a value for allowing a normal operation before diagnosis. The register value inside the circuit block after the diagnosis has been maintained to be equal to that before the diagnosis. This reduces time period from end of diagnosis by the logic BIST 3 to restart of normal operation of the circuit block.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor circuit device.

As a semiconductor circuit device, a device equipped with a diagnostic function by logic BIST (Built-In Self Test) is provided for functional safety of a circuit block composed of a plurality of logic circuits. The diagnosis by this logic BIST is executed during the normal operation of the circuit block. Diagnosis by logic BIST can be applied to various logic circuits, and has advantages such as labor saving in design by automatic insertion.

Japanese Patent No. 6438353 Japanese Patent No. 2008-267998

However, after the execution of the diagnosis by the logic BIST, the register value inside the circuit block becomes a value different from that before the execution of the diagnosis by the logic BIST, so that the logic circuit may not normally operate depending on the registration value.

Therefore, in order for the logic circuit to resume normal operation, it is necessary to set an appropriate value that can be operated in the register inside the circuit block, but it takes time to set an appropriate value in the register. During that time, the logic circuit cannot be operated and it takes time to resume normal operation.

Patent Document 1 is to prevent the output of logic BIST from affecting the cache memory, interrupt state, sleep, and other execution states when executing logic BIST on logic circuits such as CPU and accelerator. , Prevents performance deterioration.

However, the one in Patent Document 1 is for suppressing the influence on the peripheral circuits of the target circuit diagnosed by the logic BIST, and speeds up returning the state of the target circuit itself diagnosed by the logic BIST to the normal operation. Can't be done.

Further, in Patent Document 2, a circuit that holds the output value of the circuit to be diagnosed is provided at the time of failure diagnosis so that the operation of the external circuit that receives the output and operates during the diagnosis is not hindered. ing.

However, Patent Document 2 is for increasing the availability of the circuit by operating the subsequent circuit even during the diagnosis by the logic BIST, and enhances the availability of the circuit by speeding up the recovery from the diagnosis by the logic BIST. It is not possible.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor circuit device capable of speeding up from the end of diagnosis by logic BIST to the resumption of normal operation of a logic circuit of a circuit block. is there.

According to the invention of claim 1, the test target unit (2) forms a scan chain by serially connecting scan flip-flops (7) provided in a circuit block formed by combining a plurality of logic circuits at the time of diagnosis. .. The logic BIST unit (3) executes a scan test for detecting a failure of a logic circuit by shifting a test pattern into the scan chain and observing observation data shifted out of the scan chain. At this time, the register value maintenance unit (6, 8, 9) maintains the register value inside the circuit block after the execution of the diagnosis by the logic BIST unit as the same as before the execution. As a result, the logic circuit of the circuit block can be normally operated immediately after the diagnosis of the logic BIST unit (3) is executed.

Functional block diagram showing a semiconductor circuit device in one embodiment Function block diagram showing the save / restore function of the register value save target circuit Functional block diagram showing a modified embodiment (No. 1) Functional block diagram showing a modified embodiment (Part 2) Flowchart showing the operation of Logic BIST Logic BIST timing chart Logic BIST timing chart showing a modified embodiment

Hereinafter, one embodiment will be described with reference to the drawings.
As shown in FIG. 1, the semiconductor circuit device 1 includes a target circuit 2 (corresponding to a test target unit) to be diagnosed in a scan test, and a logic BIST unit 3 that executes a scan test on the target circuit 2. It is composed of.

The target circuit 2 is composed of a register value save target circuit 4, a circuit not subject to register value save / hold (hereinafter referred to as a normal circuit) 5, and a register value hold target circuit 6 (corresponding to a register value maintenance unit). ..
The register value save target circuit 4 and the normal circuit 5 are composed of a circuit block formed by combining a plurality of logic circuits. One circuit block generates an output pattern by performing a logical operation on an input pattern from an external circuit block or a circuit block in the previous stage, and outputs the output pattern to the circuit block in the subsequent stage or the outside.

Scan flip-flops (hereinafter referred to as scan FF) 7 are provided on the input side and the output side of one circuit block, respectively. The scan FF7 forms a scan chain by serially connecting the input side and the output side in a state of being replaced by flip-flops mounted on the input side and the output side of one circuit block.

The register value save target circuit 4 is a circuit in which the importance of saving is higher than that of the normal circuit 5. As peripheral circuits of the register value save target circuit 4, a register value save unit 8 (corresponding to a register value maintenance unit) and a write-back control unit 9 (corresponding to a register value maintenance unit) are provided. The register value saving unit 8 stores the register value of the register value saving target circuit 4 inside the circuit block as a backup when the diagnosis execution by the logic BIST is started.

As shown in FIG. 2, the write-back control unit 9 has a first transmission path 9a for transmitting a scan test value from the logic BIST unit 3 to the circuit block, and a second transmission path 9a for transmitting a backup value from the register value saving unit 8 to the circuit block. A transmission path 9b and a switching unit 9c capable of switching between the first transmission path 9a and the second transmission path 9b are provided. The write-back control unit 9 restores the backup value saved in the register value save unit 8 by the switching unit 9c when the diagnosis execution by the logic BIST is completed by writing it back as the register value of the register value save target circuit 4.

The register value holding target circuit 6 is composed of a large number of registers, and a set value is stored in each register. Since the register value holding target circuit 6 is a storage circuit for holding the set value, it is excluded from the diagnosis target by the logic BIST unit 3 even in the target circuit 2. Therefore, the scan FF7 is not provided on the input side and the output side of the register value holding target circuit 6, and the logic BIST unit 3 cannot detect the failure. Therefore, a method such as executing a cyclic check of the set value from the outside. It is desirable to configure it so that failure detection can be determined.

On the other hand, a host control unit 10 and a signature value storage unit 11 are provided as peripheral circuits of the register value holding target circuit 6. The host control unit 10 sets a predetermined set value in the register of the register value holding target circuit 6 at an appropriate timing.

The signature value is stored in the signature value storage unit 11 by the host control unit 10. This signature value is shifted out from the scan chain according to the set value given to the normal circuit 5 and the register value saving unit 8 during the scan test of the normal circuit 5 and the register value saving unit 8 by the logic BIST unit 3. This is the expected value obtained by compressing the planned observation data.

The logic BIST unit 3 is composed of a logic BIST control unit 12, a random pattern generation unit 13, and a signature calculation / comparison unit 14. During the scan test, the logic BIST control unit 12 shifts in by giving a scan mode signal, a scan clock signal, and a random data signal to the scan chain corresponding to the normal circuit 5 and the register value save target circuit 4, and also shifts in from the scan chain. The failure of the target circuit 2 is determined by observing the observed data that is shifted out.
In addition, in FIG. 1, the case where there is one circuit block is illustrated for simplification of explanation. Further, the illustration of the output line of each signal from the logic BIST control unit 12 to the target circuit 2 is omitted.

The random pattern generation unit 13 generates a random pattern (corresponding to a test pattern) as a test pattern for a scan test and shifts it into the scan chain. In the state where the random pattern is stored in the scan FF7 provided on the input side of the circuit block, the observation data which is the logical operation result corresponding to the random pattern stored in the scan FF7 on the input side is shifted out from the scan chain. ..

The signature calculation / comparison unit 14 calculates the signature value obtained by compressing the observation data shifted out from the scan chain, and compares it with the expected value obtained in advance and the expected value stored in the signature value storage unit 11 to perform a logic circuit. Judge the failure of.

By the way, after the diagnosis is executed by the logic BIST unit 3, there is a possibility that a value in which the logic circuit cannot normally operate normally is stored in the register inside the circuit block. In such a case, the logic circuit that has resumed normal operation does not operate normally, which causes a problem in the logical operation by the logic circuit.

Under these circumstances, in the present embodiment, by adopting the following configuration, it is possible to prevent the logic operation by the logic circuit from being hindered after the diagnosis is executed by the logic BIST unit 3.
(1) Configuration in which the register value save target circuit 4 is provided A mechanism is incorporated to automatically save the register value inside the circuit block during the execution of the diagnosis by the logic BIST and restore it when the diagnosis execution by the logic BIST is completed. In this case, if all the register values of the target circuit 2 are saved, the circuit area of the register value saving unit 8 becomes large and the saving execution time becomes long.

Therefore, the register with high importance of saving is classified into the register with low importance, and only the register value with high importance of saving is backed up in the register value saving unit 8. In this case, a mechanism for writing back the saved backup value to a register having a high importance of saving is required. Therefore, the shift-in path of the random pattern and the shift-out path of the observation data are separated by the register to be saved and the register not to be saved, and only the path of the register to be saved is the path to save and restore the register value. , Implemented its control configuration.

Specifically, the scan FF 7 is configured separately as a register value save target circuit 4 to be saved and a normal circuit 5 not to be saved, and a path for saving the register value to the register value save unit 8 and a register value. A write-back control unit 9 for switching a path for writing back the register value saved in the save unit 8 to the register value save target circuit 4 is provided on the input side of the register value save target circuit 4.

When the write-back control unit 9 is mounted on the semiconductor circuit device 1, the register value save operation by the logic BIST unit 3 causes the register value to be sent to the register value save unit 8 at the start of diagnosis of the logic BIST unit 3 as shown in FIG. Evacuate (S1).
Next, the random pattern is shifted into the scan chain (S2), the logic circuit is operated with the random set value (S3), and then the signature value that compresses the expected value corresponding to the random pattern and the shift out from the scan chain. The operation result is confirmed by comparing the observed data with the compressed signature value (S4).

When the above confirmation operation is executed a predetermined number of times (S5: YES), the logic BIST is completed, the write-back control unit 9 is operated to switch the scan chain input to the output of the register value save unit 8, and the register value save unit It is restored by writing back the register value saved in 8 (S6).

By the above operation, as shown in FIG. 6, the register value save operation, the random pattern shift-in operation, the observation data shift-out operation, and the register value write-back operation can be executed in order.
As shown in FIG. 7, the save operation and the write-back operation may simultaneously execute the shift-in of the random pattern and the shift-out of the observation data. According to such a configuration, the diagnosis time of the logic BIST can be shortened.

(2) Configuration for providing the register value holding target circuit 6 The register value holding target circuit 6 is provided as a non-diagnosis target by the logic BIST unit 3. As a matter of course, the register value holding target circuit 6 which is excluded from the diagnosis target of the logic BIST does not need to reset the register value after the diagnosis by the logic BIST unit 3. The register value holding target circuit 6 assumes a function as a holding circuit in which set values such as configuration values set by the host control unit 10 are set at the time of circuit startup and hold values that do not change during operation.

Further, the connection portion between the register value holding target circuit 6 which is excluded from the logic BIST and the normal circuit 5 and the register value saving target circuit 4 which are the targets of the logic BIST is subjected to the logic BIST in the same connection state as in the normal operation. Execute. As a result, the failure of the connection portion between the register value holding target circuit 6 and the logic BIST target circuit can be detected by the logic BIST unit 3. That is, when the diagnosis by the logic BIST unit 3 is executed with the set value given to the normal circuit 5 and the register value save target circuit 4 from the register value holding target circuit 6, the observation data in which the set value is shifted out is affected. Will give.

Since the set value affects the observation data in this way, the boundary between the register value holding target circuit 6 and the normal circuit 5 is determined by comparing the signature value obtained by compressing the shifted out observation data with the expected value. It becomes possible to determine the failure.

Here, the signature value, which is an expected value obtained as a test result of executing the logic BIST, depends on the register value of the register value holding target circuit 6 which is excluded from the logic BIST target. Therefore, the signature value storage unit 11 for storing the signature value is provided, and the expected value of the signature value can be stored by the host control unit 10. As the signature value in this case, the signature value corresponding to the register value of the register value holding target circuit 6 is set by the host control unit 10 during normal operation.

As shown in FIG. 3, the register value holding target circuit 6 logics by setting the input data to the register value saving target circuit 4 and the normal circuit 5 by the logic BIST unit 3 to a fixed value selected by the selector unit 15. It is also possible to make the test result by the BIST unit 3 independent of the register value of the circuit not subject to the logic BIST. In this case, it is not necessary to keep the signature value as the set value.

However, since the failure detection rate at the boundary between the circuit not subject to logic BIST and the circuit subject to logic BIST decreases, it is necessary to implement a method of separately inspecting the selector unit 15 which is the boundary. As a method for that, as shown in FIG. 4, it is conceivable to feed back the signal output from the selector unit 15 from the buffer 16 and compare it with the original value.

Since the failure detection rate of the circuit by the logic BIST unit 3 changes depending on the boundary setting value, the effect of the logic BIST can be enhanced by selecting a setting value that makes the detection rate as high as possible.

In the present embodiment, the registers of the target circuit 2 must be classified into a save target, a retention target, and three other circuits, and each of them must be configured as a different scan chain when a scan test is inserted to execute the logic BIST. However, it may take time and effort to design. However, if the circuit designer can classify the registers, the scan FF7 classified by classification can be incorporated by classifying and specifying the registers in the scan test insertion tool corresponding to Logic BIST. ..

According to such an embodiment, the following effects can be obtained.
Focusing on the fact that the register value inside the circuit block to be diagnosed by the logic BIST unit 3 is set to a value that can be normally operated before the diagnosis is executed, the register value inside the circuit block after the diagnosis is executed is set to the value after the diagnosis is executed. Since they are maintained to be the same, it is possible to speed up the period from the end of the diagnosis by the logic BIST unit 3 to the restart of the normal operation of the circuit block.

(Other embodiments)
In the above embodiment, the semiconductor circuit device 1 is provided with the register value saving target circuit 4, the register value holding target circuit 6, and peripheral circuits thereof, but only one of them may be provided.
Instead of providing the scan FF7 before and after the circuit block, the scan FF7 may be provided at an arbitrary position inside the circuit block.
Although the failure of the logic circuit is judged by comparing the signature values, the random pattern to be shifted in and the observed data to be shifted out may be directly compared.

Although this disclosure has been described in accordance with embodiments, it is understood that this disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within an equal range. In addition, various combinations and forms, as well as other combinations and forms that include only one element, more, or less, are also within the scope of the present disclosure.

In the drawing, 1 is a semiconductor circuit device, 2 is a target circuit (test target part), 3 is a logic BIST part, 4 is a register value save target circuit, 6 is a register value holding target circuit (register value maintenance part), and 7 is a scan. Flip-flop, 8 is a register value save unit (register value maintenance unit), 9 is a write-back control unit (register value maintenance unit), 9a is a first transmission path, 9b is a second transmission path, 9c is a switching unit, and 10 is. The host control unit and 11 are signature value storage units.

Claims (5)

A test target unit (2) that forms a scan chain by serially connecting scan flip-flops (7) provided in a circuit block formed by combining a plurality of logic circuits at the time of diagnosis.
A logic BIST unit (3) that executes a scan test for detecting a failure of the logic circuit by shifting the test pattern into the scan chain and observing the observation data shifted out from the scan chain.
A register value maintenance unit (6, 8, 9) that maintains the register value inside the circuit block after the execution of the diagnosis by the logic BIST unit is the same as that before the execution.
A semiconductor circuit device equipped with. The test target portion is configured to include a register value save target circuit (4).
The register value maintenance unit
A register value saving unit (8) that saves the register value of the register value saving target circuit before execution of diagnosis by the logic BIST unit and stores it as a backup value, and
The semiconductor circuit device according to claim 1, further comprising a write-back control unit (9) that restores the backup value as the register value after execution of diagnosis by the logic BIST unit. The write-back control unit (9)
A first transmission path (9a) for transmitting a scan test value from the logic BIST unit to the scan chain, and
A second transmission path (9b) for transmitting the backup value from the register value saving unit to the logic circuit, and
The semiconductor circuit device according to claim 2, further comprising a switching unit (9c) capable of switching between the first transmission path and the second transmission path. The test target unit includes a register value holding target circuit (6) excluded from the diagnosis target by the logic BIST unit.
The semiconductor circuit device according to claim 1, wherein the register value maintaining unit is the circuit for holding the register value. The register value holding target circuit is provided so as to set a set value in another circuit in the test target portion.
A host control unit (10) for obtaining an expected value of a signature value obtained by compressing observation data shifted out from the other circuit in which the set value is set, and
A signature value storage unit (11) for storing the expected value is provided.
The logic BIST unit executes the scan test by comparing the expected value stored in the signature value storage unit with the signature value obtained by compressing the observation data, thereby performing the register value holding target circuit and the said. The semiconductor circuit device according to claim 4, wherein a failure at a boundary with another circuit is detected.

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