JP2008244370A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method by which miniaturization of the entire semiconductor device is realized and high cooling effect is obtained, without requiring complex manufacturing processes. <P>SOLUTION: A cooling element utilizing the Peltier effect consists of a semiconductor chip 1 in which an N-type semiconductor region 4 and a P-type semiconductor region 5, having common element formation surface 1a and rear surface 1b are formed; an electrode pad 21 formed on the element formation surface 1a of the N-type semiconductor region 4 of the semiconductor chip 1; an electrode pad 22 formed on the element formation surface 1a of the P-type semiconductor region 5 of the semiconductor chip 1; and a conductive layer 3 formed on the rear surface 1b of the semiconductor chip 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device incorporating a cooling device and a method for manufacturing the same.

  In recent years, portable devices typified by mobile phones have rapidly spread, and there is a demand for downsizing, thinning, and weight reduction of semiconductor devices mounted on them. One of key technologies for realizing this is a high-density package such as a CSP (Chip Size Package) that is as close as possible to the size of a semiconductor chip.

  In particular, W-CSP (Wafer Level Chip Size Package) in which the sealing process is performed in a wafer state is attracting attention as a small package because it can be expected to reduce manufacturing costs.

  In a high-density package such as W-CSP, it is necessary to efficiently cool a semiconductor chip without hindering downsizing which is a feature of the package. As an example of a semiconductor device having such a cooling function, the following conventional technique (for example, see Patent Document 1) can be cited.

In order to integrate, for example, a Peltier element having a cooling effect, this semiconductor device includes a Peltier element together with a semiconductor element in a sealing resin portion of a W-CSP package, and the Peltier element forms a main surface of the semiconductor element. Forced cooling through electrode pads and spherical electrodes.
JP 2006-32453 A

  However, when, for example, a Peltier element having a cooling effect is integrated with the semiconductor device as in the semiconductor device described above, the Peltier element is formed separately from the semiconductor element in the sealing resin portion. In addition to being extremely difficult and complicated to manufacture, it is difficult to reduce the size of the entire semiconductor device.

  The present invention solves the above-described conventional problems, and does not require a complicated manufacturing process, and can achieve a high cooling effect while realizing downsizing of the entire semiconductor device and a manufacturing method thereof I will provide a.

  In order to solve the above-described problem, a semiconductor device according to claim 1 of the present invention includes a semiconductor element in which an N-type semiconductor region and a P-type semiconductor region are formed between an opposing first surface and a second surface, A first conductive layer formed on the first surface of the N-type semiconductor region; a second conductive layer formed on the first surface of the P-type semiconductor region; and the N conductive layer on the second surface of the semiconductor element. A third conductive layer formed over the p-type semiconductor region and the p-type semiconductor region, the n-type semiconductor region and the p-type semiconductor region, the first conductive layer and the second conductive layer, A cooling element is formed of three conductive layers.

  A semiconductor device according to claim 2 of the present invention is the semiconductor device according to claim 1, wherein the N-type semiconductor region and the P-type semiconductor region are electrically insulated by an insulating trench. .

According to a third aspect of the present invention, there is provided the semiconductor device according to the second aspect, wherein the element thickness of the semiconductor element is 90 μm or less.
The semiconductor device according to claim 4 of the present invention is a resin-sealed semiconductor device in which an N-type semiconductor region and a P-type semiconductor region are formed between the first and second surfaces facing each other. An element, a first conductive layer formed on the first surface of the N-type semiconductor region, a second conductive layer formed on the first surface of the P-type semiconductor region, and for the resin sealing A sealing resin covering the first surface of the semiconductor element; a first electrode post formed in a column shape on the first conductive layer and having one end exposed from the sealing resin; and a columnar shape on the second conductive layer A second electrode post formed at one end exposed from the sealing resin; a first electrode formed in contact with one end of the exposed first electrode post; and formed in contact with one end of the exposed second electrode post. And the N-type semiconductor region on the second surface of the semiconductor element. And a third conductive layer formed over the P-type semiconductor region, the N-type semiconductor region and the P-type semiconductor region, the first conductive layer and the second conductive layer, and the first electrode post And the second electrode post, the first electrode and the second electrode, and the third conductive layer form a cooling element, which is resin-sealed to approximately the same dimensions as the semiconductor element. To do.

  The semiconductor device according to claim 5 of the present invention is the semiconductor device according to claim 4, wherein the N-type semiconductor region and the P-type semiconductor region are electrically insulated by an insulating trench. .

A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to the fifth aspect, wherein an element thickness of the semiconductor element is 90 μm or less.
The semiconductor device manufacturing method according to claim 7 of the present invention is a semiconductor device manufacturing method, comprising: preparing a semiconductor wafer having first and second surfaces facing each other; and Forming an N-type semiconductor region between the first surface and the second surface; forming a P-type semiconductor region between the first surface and the second surface of the semiconductor wafer; and the N-type semiconductor region Forming a first conductive layer on the first surface, forming a second conductive layer on the first surface of the P-type semiconductor region, and forming the N on the second surface of the semiconductor wafer. Forming a third conductive layer over the p-type semiconductor region and the p-type semiconductor region.

  A method for manufacturing a semiconductor device according to claim 8 of the present invention is the method for manufacturing a semiconductor device according to claim 7, wherein the N-type semiconductor region and the P-type semiconductor are formed from the first surface of the semiconductor wafer. Forming an insulating trench for electrically isolating the region.

  A method for manufacturing a semiconductor device according to claim 9 of the present invention is the method for manufacturing a semiconductor device according to claim 8, wherein a thickness between the first surface and the second surface of the semiconductor wafer is 90 μm. And polishing the second surface until the following condition is satisfied.

  A method for manufacturing a semiconductor device according to claim 10 of the present invention is a method for manufacturing a resin-sealed semiconductor device, comprising: preparing a semiconductor wafer having first and second surfaces facing each other; Forming an N-type semiconductor region between the first surface and the second surface of the semiconductor wafer; forming a P-type semiconductor region between the first surface and the second surface of the semiconductor wafer; Forming a first conductive layer on the first surface of the N-type semiconductor region; forming a second conductive layer on the first surface of the P-type semiconductor region; and on the first conductive layer Forming a first electrode post on the second conductive layer, forming a second electrode post on the second conductive layer, covering the first surface of the semiconductor wafer with a sealing resin, and the first electrode Expose the post from the sealing resin A step of exposing the second electrode post from the sealing resin, forming a first electrode on the exposed portion of the first electrode post, and a second portion on the exposed portion of the second electrode post. Forming an electrode; and forming a third conductive layer over the N-type semiconductor region and the P-type semiconductor region on the second surface of the semiconductor wafer, wherein the semiconductor device is substantially the same as the semiconductor wafer. It is characterized by resin sealing to the same dimension.

  The semiconductor device manufacturing method according to claim 11 of the present invention is the semiconductor device manufacturing method according to claim 10, wherein the N-type semiconductor region and the P-type semiconductor are formed from the first surface of the semiconductor wafer. Forming an insulating trench for electrically isolating the region.

  A semiconductor device manufacturing method according to claim 12 of the present invention is the semiconductor device manufacturing method according to claim 11, wherein a thickness between the first surface and the second surface of the semiconductor wafer is 90 μm. And polishing the second surface until the following condition is satisfied.

  As described above, according to the present invention, the N-type semiconductor region and the P-type semiconductor region constituting the cooling element can be formed in the semiconductor element. While being manufactured, the cooling element can be configured as a semiconductor element in the same semiconductor element as other semiconductor elements.

  Therefore, it is possible to efficiently and surely obtain a high cooling effect without requiring a complicated manufacturing process and easily realizing downsizing of the entire semiconductor device.

Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be specifically described with reference to the drawings.
(Embodiment 1)
A semiconductor device and a manufacturing method thereof according to the first embodiment of the present invention will be described.
[Construction]
FIG. 1 is a cross-sectional view of a configuration example of a semiconductor device 100 according to the first embodiment. As shown in FIG. 1, the semiconductor device 100 includes a semiconductor chip 1, an electrode pad 21 and an electrode pad 22, a conductive layer 3, an N-type semiconductor region 4, a P-type semiconductor region 5, and an insulating trench 6. ing. The electrode pads 21 and 22 and the conductive layer 3 are not limited to those shown in FIG.

  The semiconductor chip 1 includes an electrode pad 21 and an electrode pad 22 on the element formation surface 1a. An electronic circuit (not shown) is constituted by a semiconductor element such as a transistor on the element forming surface 1a.

  The insulating trench 6 has a depth of 90 μm or less with respect to the semiconductor chip 1 and is usually several tens of μm. However, by polishing the semiconductor chip 1 from the back surface 1 b direction, the thickness of the semiconductor chip 1 becomes the depth of the insulating trench 6. Thus, the N-type semiconductor region 4, the P-type semiconductor region 5 and other regions can be electrically separated.

The cooling function of the semiconductor device 100 according to the first embodiment is that the N-type semiconductor region 4 and the P-type semiconductor region 5 electrically separated by the insulating trench 6, the electrode pad 21 and the electrode pad 22, and the conductive layer 3 It uses the Peltier effect of the cooling element.
[Production method]
FIG. 2 schematically shows a manufacturing process of the semiconductor device 100. First, as shown in FIG. 2A, a semiconductor wafer 1 ′ whose electrical characteristics are evaluated by wafer inspection is prepared. On the element forming surface 1a of the semiconductor wafer 1 ', an electronic circuit (not shown) is constituted by semiconductor elements such as transistors.

Next, as shown in FIG. 2B, an insulating trench 6 is formed on the element forming surface 1a by photolithography etching or the like on the semiconductor wafer 1 ′.
Next, as shown in FIG. 2C, an N-type semiconductor region 4 and a P-type semiconductor region 5 are formed by impurity implantation.

Next, as shown in FIG. 2D, the semiconductor wafer 1 ′ is polished to a thickness that reaches the insulating trench 6 from the back surface 1b.
Next, as shown in FIG. 2E, a metal layer is deposited by sputtering or the like, and electrode pads 21 and electrode pads 22 are formed by photolithography etching or the like.

Next, as shown in FIG. 2F, a metal layer is deposited on the back surface 1b of the semiconductor wafer 1 ′ by sputtering or the like, and the conductive layer 3 is formed by photolithography etching or the like.
According to the first embodiment, by forming the Peltier element integrally with other semiconductor elements in the semiconductor device 100, the semiconductor element, that is, the entire semiconductor device can be reduced in size and a high cooling effect can be realized. In addition, since all the processes can be collectively processed in the wafer state, the cost can be reduced.
(Embodiment 2)
A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described.
[Construction]
FIG. 3 is a structural diagram of the resin-encapsulated semiconductor device 101 according to the second embodiment. As shown in FIG. 3, the resin-encapsulated semiconductor device 101 includes a semiconductor chip 1, a protective film 7, an electrode pad 21 and an electrode pad 22, an N-type semiconductor region 4 and a P-type formed in the semiconductor chip 1. The semiconductor region 5, the insulating trench 6, the electrode post 81 and the electrode post 82, the spherical electrode 91 and the spherical electrode 92, the sealing resin 10, and the conductive layer 3 formed on the back surface 1 b are provided. The electrode pads 21 and 22 and the conductive layer 3 are not limited to those shown in FIG.

  In the semiconductor chip 1, an electronic circuit (not shown) is configured by a semiconductor element such as a transistor on the element forming surface 1a side. The protective film 7 is a passivation for protecting the semiconductor chip 1 from mechanical stress and entry of impurities. Electrode pad 21 and electrode pad 22 are electrically connected to N-type semiconductor region 4 and P-type semiconductor region 5 formed in semiconductor chip 1, respectively.

  A protective film 7 is formed on the semiconductor chip 1 except above the electrode pads 21 and the electrode pads 22. The electrode post 81 and the electrode post 82 are formed above the electrode pad 21 and the electrode pad 22. A spherical electrode 91 and a spherical electrode 92 are formed on the electrode post 81 and the electrode post 82. The sealing resin 10 seals the protective film 7, the electrode post 81, and the electrode post 82.

  The insulating trench 6 has a depth of 90 μm or less with respect to the semiconductor chip 1 and is usually several tens of μm. However, by polishing the semiconductor chip 1 from the back surface 1 b direction, the thickness of the semiconductor chip 1 becomes the depth of the insulating trench 6. Thus, the N-type semiconductor region 4, the P-type semiconductor region 5 and other regions can be electrically separated. The conductive layer 3 is formed on the back surface 1 b of the semiconductor chip 1.

The cooling function of the semiconductor device 101 according to the second embodiment is that the N-type semiconductor region 4 and the P-type semiconductor region 5 electrically separated by the insulating trench 6, the electrode pad 21 and the electrode pad 22, and the conductive layer 3. Further, the Peltier effect of the cooling element constituted by the electrode post 81 and the electrode post 82 and the spherical electrode 91 and the spherical electrode 92 is used.
[Production method]
FIG. 4 schematically shows a manufacturing process of the resin-encapsulated semiconductor device 101. First, as shown in FIG. 4A, a semiconductor wafer 1 ′ whose electrical characteristics are evaluated by wafer inspection is prepared. On the element formation surface 1a, an electronic circuit (not shown) is constituted by a semiconductor element such as a transistor.

Next, as shown in FIG. 4B, an insulating trench 6 is formed in the element formation surface 1a on the semiconductor wafer 1 ′ by photolithography etching or the like.
Next, as shown in FIG. 4C, an N-type semiconductor region 4 and a P-type semiconductor region 5 are formed by impurity implantation.

Next, as shown in FIG. 4D, the metal layer is volumed by sputtering or the like, and the electrode pad 21 and the electrode pad 22 are formed by photolithography etching or the like.
Next, as shown in FIG. 4E, a polyimide resin is applied to the entire surface of the semiconductor wafer 1 ′, and the protective film 7 is formed by photolithography etching except for the electrode pads 21 and 22 above the electrodes.

Next, as shown in FIG. 4F, an electrode post 81 and an electrode post 82 are respectively formed on part of the electrode pad 21 and the electrode pad 22 by plating or the like.
Next, as shown in FIG. 4G, the protective film 7, the electrode pad 21 and the electrode pad 22, the electrode post 81 and the electrode post 82 are sealed with a sealing resin 10.

Next, as shown in FIG. 4H, the surface of the sealing resin 10 is subjected to front surface etching to expose the surfaces of the electrode post 81 and the electrode post 82.
Next, as shown in FIG. 4I, the semiconductor wafer 1 ′ is polished to a thickness that reaches the insulating trench 6 from the back surface 1b.

Next, as shown in FIG. 4J, a metal layer is deposited on the back surface 1b of the semiconductor wafer 1 ′ by sputtering or the like, and the conductive layer 3 is formed by photolithography etching or the like.
Next, as shown in FIG. 4 (k), a spherical electrode 91 and a spherical electrode 92 are formed on the electrode post 81 and the electrode post 82, respectively.

  According to the second embodiment, by making the Peltier element integrally in the semiconductor device 101, the semiconductor element, that is, the semiconductor device, can be downsized and a high cooling effect can be realized. In addition, since all the processes can be collectively processed in the wafer state, the cost can be reduced.

  The semiconductor device and the manufacturing method thereof according to the present invention do not require a complicated manufacturing process and can achieve a high cooling effect while realizing miniaturization of the entire semiconductor device. The present invention is applied to a device, and is particularly effective for a resin-encapsulated semiconductor device using CSP.

Sectional view of the structure of the semiconductor device according to the first embodiment of the present invention. Manufacturing process sectional drawing which shows the manufacturing method of the semiconductor device of the same Embodiment 1 Sectional view of the structure of the semiconductor device according to the second embodiment of the present invention. Manufacturing process sectional drawing which shows the manufacturing method of the semiconductor device of the same Embodiment 2

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1 'Semiconductor wafer 21, 22 Electrode pad 3 Conductive layer 4 N type semiconductor region 5 P type semiconductor region 6 Insulating trench 7 Protective film 81, 82 Electrode post 91, 92 Spherical electrode 10 Sealing resin 100, 101 Semiconductor device

Claims (12)

A semiconductor element in which an N-type semiconductor region and a P-type semiconductor region are formed between an opposing first surface and a second surface;
A first conductive layer formed on the first surface of the N-type semiconductor region;
A second conductive layer formed on the first surface of the P-type semiconductor region;
A third conductive layer formed over the N-type semiconductor region and the P-type semiconductor region on the second surface of the semiconductor element;
A semiconductor device, wherein a cooling element is formed by the N-type semiconductor region and the P-type semiconductor region, the first conductive layer, the second conductive layer, and the third conductive layer. 2. The semiconductor device according to claim 1, wherein the N-type semiconductor region and the P-type semiconductor region are electrically insulated by an insulating trench. The semiconductor device according to claim 2, wherein an element thickness of the semiconductor element is 90 μm or less. A resin-sealed semiconductor device,
A semiconductor element in which an N-type semiconductor region and a P-type semiconductor region are formed between an opposing first surface and a second surface;
A first conductive layer formed on the first surface of the N-type semiconductor region;
A second conductive layer formed on the first surface of the P-type semiconductor region;
Sealing resin that covers the first surface of the semiconductor element for the resin sealing;
A first electrode post formed in a column shape on the first conductive layer and having one end exposed from the sealing resin;
A second electrode post formed in a column shape on the second conductive layer and having one end exposed from the sealing resin;
A first electrode formed in contact with one end of the exposed first electrode post;
A second electrode formed in contact with one end of the exposed second electrode post;
A third conductive layer formed over the N-type semiconductor region and the P-type semiconductor region on the second surface of the semiconductor element;
The N-type semiconductor region and the P-type semiconductor region, the first conductive layer and the second conductive layer, the first electrode post and the second electrode post, the first electrode and the second electrode, Forming a cooling element with the third conductive layer;
A semiconductor device characterized by being resin-sealed to approximately the same dimensions as the semiconductor element. The semiconductor device according to claim 4, wherein the N-type semiconductor region and the P-type semiconductor region are electrically insulated by an insulating trench. The semiconductor device according to claim 5, wherein an element thickness of the semiconductor element is 90 μm or less. A method for manufacturing a semiconductor device, comprising:
Providing a semiconductor wafer having opposing first and second surfaces;
Forming an N-type semiconductor region between the first surface and the second surface of the semiconductor wafer;
Forming a P-type semiconductor region between the first surface and the second surface of the semiconductor wafer;
Forming a first conductive layer on the first surface of the N-type semiconductor region;
Forming a second conductive layer on the first surface of the P-type semiconductor region;
Forming a third conductive layer on the second surface of the semiconductor wafer over the N-type semiconductor region and the P-type semiconductor region. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising forming an insulating trench for electrically insulating the N-type semiconductor region and the P-type semiconductor region from the first surface of the semiconductor wafer. 9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of polishing the second surface until a thickness between the first surface and the second surface of the semiconductor wafer becomes 90 [mu] m or less. A method for manufacturing a resin-encapsulated semiconductor device, comprising:
Providing a semiconductor wafer having opposing first and second surfaces;
Forming an N-type semiconductor region between the first surface and the second surface of the semiconductor wafer;
Forming a P-type semiconductor region between the first surface and the second surface of the semiconductor wafer;
Forming a first conductive layer on the first surface of the N-type semiconductor region;
Forming a second conductive layer on the first surface of the P-type semiconductor region;
Forming a first electrode post on the first conductive layer;
Forming a second electrode post on the second conductive layer;
Covering the first surface of the semiconductor wafer with a sealing resin;
Exposing the first electrode post from the sealing resin;
Exposing the second electrode post from the sealing resin;
Forming a first electrode on the exposed portion of the first electrode post;
Forming a second electrode on the exposed portion of the second electrode post;
Forming a third conductive layer on the second surface of the semiconductor wafer over the N-type semiconductor region and the P-type semiconductor region;
A method of manufacturing a semiconductor device, wherein the semiconductor device is resin-sealed to substantially the same dimensions as the semiconductor wafer. 11. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of forming an insulating trench for electrically insulating the N-type semiconductor region and the P-type semiconductor region from the first surface of the semiconductor wafer. 12. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of polishing the second surface until a thickness between the first surface and the second surface of the semiconductor wafer becomes 90 [mu] m or less.

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