JP2008244286A - Circuit for detecting magnifying factor of avalanche photodiode (apd) - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit which can detect a magnifying factor of an avalanche photodiode (APD). <P>SOLUTION: The circuit for detecting the magnifying factor is equipped with an avalanche photodiode 11, a photodiode which is located so as to receive the same amount of light to the avalanche photodiode and has no magnifying operation, and a comparison means which is located so as to output an amount of current corresponding to the difference between the magnified current outputted from the avalanche photodiode and the current outputted from the phtodiode. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to an imaging apparatus, and more specifically, a circuit for detecting a multiplication factor of an APD used in the imaging apparatus.

  An avalanche photodiode (hereinafter sometimes simply referred to as APD) is an element using a semiconductor. The structure has a P-type region and an N-type region. In addition, a depletion region exists between the P-type region and the N-type region, and plays two roles in the depletion region. The first is photoelectric conversion. The second is signal multiplication. Usually, an APD operates with a single power source. The operating voltage is a very large reverse bias voltage (a negative voltage on the P-type region side and a positive voltage on the N-type region side).

Since the operation includes not only photoelectric conversion but also signal multiplication operation, it is characterized in that a “small input signal” can be extracted as a “large output signal”.
Further, the signal multiplication phenomenon (avalanche multiplication phenomenon) is generated from the electric field intensity around 2 × 10 5 V / cm in Si and 1 × 10 5 V / cm in Ge.

The APD is used for an imaging apparatus aiming at high sensitivity and wide dynamic range. The multiplication factor of APD is determined by the reverse bias voltage applied to APD itself. When used in an image sensor, it is ideal to use the APD at each pixel at an optimum multiplication factor. To this end, a system capable of detecting the multiplication factor of each pixel and controlling the multiplication factor is required.

A system that can detect the multiplication factor of APD is already known (see, for example, Patent Document 1).

In the system disclosed in Patent Document 1, a reverse bias breakdown voltage at a predetermined temperature, a temperature coefficient of the reverse bias breakdown voltage, and an APD element constant are stored in advance in a memory, and a multiplication factor is obtained based on actual temperature information and voltage information. A configuration for calculating is shown.

JP 2004-289206 A

  In Patent Document 1, the multiplication factor is detected from five pieces of information. They are “current amount”, “temperature”, “applied voltage”, and “incident light amount”. However, this is not sufficient for obtaining the multiplication factor of “any incident light”. In addition to these pieces of information, information on “wavelength of incident light” is required. Alternatively, it is necessary to limit the “incident light wavelength”.

Therefore, the present invention has been made to solve the above-mentioned problems, the purpose of which is that "arbitrary incident light" can be a target of incident light, and does not require detection and calculation of applied voltage and temperature information, A multiplication factor detection circuit having a simple configuration is provided.

According to the multiplication detection circuit of the avalanche photodiode according to the present invention, the avalanche photodiode is provided so as to receive the same amount of light as the avalanche photodiode, and the photodiode has no multiplication effect, and is output from the avalanche photodiode. And comparison means provided to output a current amount corresponding to the difference between the multiplied current and the current output from the photodiode.

In the comparison means, a first capacitor for storing a multiplication current output from the avalanche photodiode is connected to a source of the field effect transistor, and a second capacitor for storing the current output from the photodiode is connected to the field effect transistor. The "multiplier current output from the avalanche photodiode" and the "current output from the photodiode" are detected based on the drain current generated by the potential difference between the gate and the source. Means are provided.

Until now, since the multiplication factor varies depending on the “wavelength of incident light”, it has not been possible to detect the multiplication factor for “arbitrary light”.

In the present invention, “arbitrary light” can be a target of incident light, and not only that, detection of “applied voltage” and “temperature” is not required.

The present invention proposes means for detecting the multiplication factor of each pixel. The detection method is performed by comparing “multiplied signal (signal by APD)” and “non-multiplied signal (signal by PD)”. The “multiplied signal” is the signal at point A in FIG. The “signal that has not been multiplied” is the signal at point C in FIG.

The FET 3 is used to compare the signals at points A and C in FIG. By using the FET 3, the signal of the difference between the points A and C is transferred to the point B. The signal transferred to point B varies depending on the multiplication factor. Here, it is assumed that the threshold voltages of all the transistors are 0 V, and the capacitances of the capacitors 6 and 7 are C.

As for the connection relationship of all elements, the anode of the APD 11 is connected to the DC power source VAPD.
The cathode of APD 11 is connected to point A. Point A is connected to the source of a field effect transistor (hereinafter also referred to as FET) 1, the anode of capacitor 6, the source of FET 4, and the source of FET 3. The cathode of the capacitor 6 is connected to GND. The gate of the FET1 is connected to the pulse voltage source Vres1. The drain of the FET1 is connected to the voltage source Vr1. The gate of the FET 4 is connected to the pulse voltage source Vres2. The drain of the FET 4 is connected to the point D, and the point D is connected to the voltage source Vr1. The gate of the FET 3 is connected to the C point. The drain of the FET 3 is connected to the point B. Point C is connected to the cathode of PD 12, the anode of capacitor 7, and the source of FET 2. The cathode of the capacitor 7 is connected to GND. The anode of the PD 12 is connected to the DC power source VPD. The gate of the FET2 is connected to the pulse power supply Vres1.
The drain of the FET2 is connected to the DC power supply Vr1.
The point B is connected to the anode of the capacitor 8, the source of the FET 5, and the Vout terminal.
The cathode of the capacitor 8 is connected to GND. The gate of the FET 5 is connected to the pulse voltage source Vres3. The drain of the FET 5 is connected to the voltage source Vr2.

The FET 1 is used to charge the potential at the point A to Vr1. The capacitor 6 is used for storing the optical signal current generated by the APD 11. The FET 2 is used to charge the potential at the point C to Vr1. The capacitor 7 is used for storing the optical signal current generated by the PD 12. The FET 3 compares the potential at the point C and the point A, and when the potential at the point A is large, it has a role of moving the electric charge of the potential difference to the point B. The FET 4 has a role of limiting the amount of charge going from the point A to the point B. Due to this limitation, signal charges proportional to the multiplication factor are accumulated at the point B. The FET 5 is used to charge the potential at the point B to Vr2. The capacitor 8 is used for accumulating charges moving from the point A to the point B.

When “multiplier is 1”, the amount of signal charge transferred to point B is zero. In “when the multiplication factor is 2”, the signal charge amount transferred to the point B is (Vr1−Vres2) / C. In “when the multiplication factor is 3 times”, the signal charge amount transferred to the point B is 2 × (Vr1−Vres2) / C. In “when the multiplication factor is 4 times”, the signal charge amount transferred to the point B is 3 × (Vr1−Vres2) / C. Thus, the signal charge amount at point B is (multiplication factor-1) × (Vr1−Vres2) / C, and it becomes possible to detect the multiplication factor.

This operation will be described with reference to FIGS.

FIG. 2 shows a circuit including FET4, FET3, APD11 and PD12 extracted from FIG.

The connection relationship of all elements is shown below. The anode of the APD 11 is connected to the DC voltage source VAPD. The cathode of APD 11 is connected to point A. Point A is connected to the anode of the capacitor 6, the source of the FET 4, and the source of the FET 3. The cathode of the capacitor 6 is connected to GND. The gate of the FET 4 is connected to the pulse voltage source Vres2. The drain of the FET 4 is connected to the point D, and the point D is connected to the voltage source Vr1. The gate of the FET 3 is connected to the C point. The drain of the FET 3 is connected to the point B. Point C is connected to the cathode of PD12. The anode of the PD 12 is connected to the DC power source VPD. Point B is connected to the anode of the capacitor 8 and the output terminal of Vout. The cathode of the capacitor 8 is connected to GND.

The capacitor 6 is used for storing the optical signal current generated by the APD 11. The FET 3 compares the potential at the point C and the point A, and when the potential at the point A is large, it has a role of moving the electric charge of the potential difference to the point B. The FET 4 has a role of limiting the amount of charge going from the point A to the point B. Due to this limitation, signal charges proportional to the multiplication factor are accumulated at the point B. The capacitor 8 is used for accumulating charges moving from the point A to the point B.

FIG. 3 shows the potential diagram of FIG. The ADP 11 outputs a signal from light as a charge accumulated at the point A. The PD 12 outputs a signal from light as a gate voltage at the point C. Here, the potential at point A is VA, and the potential at point C is VC.

Here, if the same signal (negative charge) is input to the points A and C, the voltages of VA and VC decrease by the same amount. However, since APD takes a multiplication factor of 1 or more, | ΔVA | ≧ | ΔVC |. At that time, a charge ((| ΔVA | − | ΔVB |) / C) corresponding to the voltage of | ΔVA | − | ΔVC | is transferred to the point B. The signal (| ΔVA | − | ΔVB |) / C transferred at this time becomes an output.

VA decreases with VB. Until VA becomes smaller than Vres2, charge is transferred from point A to point B as shown in FIG. 4 as in FIG.

When VA becomes smaller than Vres2, the charge at point A flows to point D as shown in FIG. In this state, the transfer of charge from the point A to the point B ends. As a result, the total amount of charges transferred from point A to point B is 0 when “multiplier is 1” as shown in paragraph 0018, and “when multiplication is double”. The signal to be transferred is a charge amount of (Vr1-Vres2) / C. “When the multiplication factor is 3” is 2 × (Vr1−Vres2) / C, and “when the multiplication factor is 4” is 3 × (Vr1−Vres2) / C. In short, the signal becomes (multiplication factor-1) × (Vr1-Vres2) / C, and the multiplication factor can be detected as Vout.

  While the present invention has been described in detail with reference to a preferred embodiment, the present invention is not limited to this embodiment and, of course, many modifications can be made without departing from the spirit of the invention. is there.

In the embodiment of the present invention, it is a circuit diagram of a detection circuit of a multiplication factor by an avalanche photodiode. FIG. 2 shows a circuit including FET4, FET3, APD11 and PD12 extracted from FIG. FIG. 3 is a potential diagram of FIG. 2 and illustrates signal charge transfer. FIG. 4 is a diagram in the case where the accumulation time of the potential diagram of FIG. 3 has elapsed (VA <Vres2), and represents signal charge transfer. FIG. 5 is a diagram in the case where the accumulation time of the potential diagram of FIG. 4 has elapsed (VA ≧ Vres2), and represents the transfer of signal charges.

Explanation of symbols

1, 2, 3, 4, 5 N-channel MOSFET
6, 7, 8 Capacitor 11 APD
12 PD

Claims (2)

An avalanche photodiode,
A photodiode that is provided so as to receive the same amount of light as an avalanche photodiode and does not have a multiplication effect;
Comparing means provided to output a current amount corresponding to the difference between the multiplication current output from the avalanche photodiode and the current output from the photodiode, the amplification of the avalanche photodiode Magnification detection circuit. The comparison means connects a first capacitor for storing the multiplication current output from the avalanche photodiode to the source of the field effect transistor, and connects a second capacitor for storing the current output from the photodiode to the gate of the field effect transistor. And means for detecting the multiplication factor by comparing the “multiplier current output from the avalanche photodiode” and the “current output from the photodiode” based on the drain current generated by the potential difference between the gate and the source. 2. A multiplication detection circuit for an avalanche photodiode according to claim 1, further comprising:

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