JP2008243315A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device, preventing erroneous decision of logical data due to a leak current of a memory cell as much as possible without narrowing a read-out margin. <P>SOLUTION: The device is equipped with: a plurality of nonvolatile memory cells Tij arranged in a matrix state; word lines WLi connected in common to control gates of the plurality of nonvolatile memory cells Tij in one column; bit lines BLi connected in common to drain areas of the plurality of nonvolatile memory cells Tij in one row; source lines Vssk connected to source areas of the plurality of nonvolatile memory cells Tij in one row; and a source line selection circuit 22 for collectively selecting one or more source lines Vssk as a read-out unit in accordance with the bit lines BLi and grounding them. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and an operating method thereof, and more particularly to a nonvolatile semiconductor memory device including a NOR flash memory capable of electrically writing and erasing data and an operating method thereof.

  FIG. 1 is a circuit diagram showing a NOR type flash memory according to a conventional example. FIG. 3A is a cross-sectional view showing the structure of the memory cell.

  In the NOR type flash memory according to the conventional example, as shown in FIG. 1, memory cells Tij are arranged in rows and columns. FIG. 1 shows a part thereof. All memory cells Tij (i = 0 to m, j = 0 to n) arranged in each row direction (horizontal direction on the paper surface) are connected to common bit lines (BLi (i = 0 to m, j = 0 to n)) and all the memory cells Tij arranged in each column direction (vertical direction on the paper surface) are connected to each common word line (WLj (j = 0 to n)) via a gate (control gate). All the memory cells Tij connected and arranged in the row direction are connected to each common source line (Vssk (k = 0 to m / 2)) via the source. The source line (Vssk) is also common between the adjacent bit lines BLi and BLi + 1.

  Each memory cell Tij is composed of an n-channel insulated gate field effect transistor having a floating gate. As shown in FIG. 3A, the main structure is that a gate insulating film 2, a floating gate 3, an intermediate insulating film 4, and a control gate 5 are laminated in this order on a p-type semiconductor substrate 1. An n-type source region 6a and drain region 6b are formed on the surface of the semiconductor substrate 1 on both sides of the laminated structure. Note that the external extraction terminal of the transistor connected to the source region 6a is referred to as a source, and the external extraction terminal of the transistor connected to the drain region 6b is referred to as a drain.

  The memory cell Tij has a medium threshold voltage in a state in which no writing is performed, and the channel easily conducts by applying a positive operating voltage for reading data to the control gate, and the drain current flows. '1' Data is in the status.

  By writing to the memory cell Tij, a logic “0” data state is obtained. In order to perform writing, a desired memory cell Tij is selected by a bit line, a source line, and a word line, the source region 6a (source line (Vssk)) is grounded, and the drain region 6b (bit line (BLi)). A positive voltage is applied to the control gate 5 and a large positive voltage is applied to the control gate 5 (word line (WLj)). Hot electrons are generated mainly in the vicinity of the drain region 6b due to the voltage between the source and the drain, and electrons are injected into the floating gate 4 due to the large positive voltage of the control gate 5 and accumulated. As a result, logic “0” data is written in the desired memory cell Tij. In this state, the memory cell Tij has a high threshold voltage, and even when an operating voltage is applied to the control gate 5, the channel does not conduct, and the drain current does not flow, or even if it flows, the leakage current is small.

  In order to read data, a desired memory cell Tij is selected by a bit line, a source line, and a word line, the source region 6a (source line (Vssk)) is grounded, and the drain region 6b (bit line (BLi)) is connected. A moderate positive voltage is applied, and a positive operating voltage is applied to the control gate 5 (word line (WLj)). When logic “0” data is written, the drain current does not flow or is small. On the other hand, a large drain current flows in the logic “1” data state. These can be measured as bit line current (IBL). Therefore, by measuring the current value, data of logic “0” or logic “1” stored in the desired memory cell Tij can be read.

  As shown in FIG. 2B, a reference current value is set in order to determine whether the data is logic “0” data or logic “1” data. When the bit line current (IBL) is lower than the reference current value, it is determined as logic “0” data, and when it is above, it is determined as logic “1” data. In practice, a certain amount of read margin is provided both above and below the reference current value. That is, in order to determine that the data is logic '0' data, the upper limit of the bit line current (IBL) is set in a range smaller than the reference current value, and on the other hand, to determine that the data is logic '1' data. In addition, the lower limit of the bit line current (IBL) is set in a range larger than the reference current value. It is preferable that the difference between the upper limit and the lower limit of these bit line currents (IBL) is larger because erroneous determination can be avoided and data can be read accurately.

  In order to erase the logic “0” data, all the memory cells Tij are selected, and the source region 6a (all source lines (Vss0) is selected all at once or in units of sectors which are a set of partial memory cells Tij. ~ Vss m / 2)), a positive voltage is applied, the drain region 6b (all bit lines (BL0 to BLm)) is opened, and the control gate 5 (all word lines (WL0 to WLn)) is greatly negative. Apply a voltage of. As a result, electrons in the floating gate 3 tunnel through the gate insulating film 2 and are emitted to the semiconductor substrate 1, thereby erasing data. Erasing can also be performed for each memory cell Tij in an appropriate block.

Patent Documents 1 to 3 are known as techniques related to the NOR type flash memory according to the conventional example.
Japanese Patent Laid-Open No. 07-147098 Japanese Patent Laid-Open No. 09-213090 JP 09-213094 A

  By the way, in the NOR type flash memory according to the conventional example, when data is written, there are some cells that are injected into the floating gate 3 due to device manufacturing variations and the like, and the amount of accumulated electrons varies or is difficult to erase. Often. Moreover, there may be a case where a very large voltage cannot be applied to the control gate 5 or the source region 6a in erasing data due to the relationship between the breakdown voltage of the gate insulating film 2 and the reverse breakdown voltage of the source region 6a. In such a case, the erasing voltage application time is adjusted, or erasing is repeated a plurality of times.

  As a result, when the application time and the number of erasures are adjusted to a cell with a large amount of accumulated electrons, a cell with a large amount of accumulated electrons can emit electrons almost completely. In a cell that can be easily erased, as shown in FIG. 3B, there is a possibility that over-erasure occurs in which not only electrons are emitted but holes are accumulated in the floating gate 3. When excessive erasure occurs, the threshold voltage is lowered, and the channel is in a depletion state or in the worst case in an inversion state as shown in FIG.

  When such a memory cell Tij + 2 and a memory cell Tij in which logic “0” data is written are mixed in one bit line (BLi), the bit line is used to read the data of the memory cell Tij. When a positive voltage is applied to (BLi), the source line (Vssk) is grounded, and a larger positive voltage is applied to the word line (WLj), the voltage is applied to the control gate 5 (WLj) in the memory cell Tij + 2. Even if not applied, a voltage is applied between the drain (BLi) and the source (Vssk), so that a large leakage current (Ileak) flows as shown in FIG. For this reason, the bit line current (IBL = Icell + Ileak) exceeds the lower limit (reference current value), which is the criterion for logic “0” data, and may lead to erroneous determination. Even if the leak current (Ileak) of one memory cell is smaller than the lower limit, which is the criterion for logic '0' data, if a plurality of such cells are connected to the same bit line, the bit is the same as above. A large leak current (Ileak) flows through the line, which may lead to erroneous determination. In order to avoid this, it is necessary to shift the lower limit of the bit line current (IBL), which is the criterion for the logic “0” data, further upward, which is not preferable.

  The present invention has been made in view of such conventional problems, and provides a semiconductor memory device and an operation method thereof that can suppress erroneous determination of logic data due to a leakage current of a memory cell as much as possible without narrowing a read margin. It is intended to provide.

  Patent Documents 1 to 3 described above describe one countermeasure against the problem, but the present invention provides a solution different from these.

  According to one aspect of the present invention, a plurality of nonvolatile memory cells arranged in a matrix, a word line commonly connected to control gates of a plurality of nonvolatile memory cells in one column, and a plurality of nonvolatile memory cells in one row A bit line commonly connected to a drain region of the nonvolatile memory cells, a source line connected to a source region of a plurality of nonvolatile memory cells in one row, and the nonvolatile connected to one bit line There is provided a semiconductor memory device comprising: a source line selection circuit that collectively selects one or more of the source lines as a read unit according to the bit line and reads the ground when reading a volatile memory cell The

  According to the present invention, a plurality of source lines are provided for each bit line. That is, a plurality of memory cells connected to each bit line are divided into one or more memory cells constituting a part thereof, and one or more divided memory cells are collectively connected to one source line. Will be.

  In addition, each bit line is provided with a source line selection circuit that collectively selects one or more source lines as a read unit.

  Therefore, when reading data from the memory cell, a voltage is applied to the selected bit line, all source lines belonging to one read unit including the source line connected to the selected memory cell are grounded, By opening the source line of the read unit, the number of memory cells to which a voltage is simultaneously applied between the first terminal and the third terminal, for example, between the drain and the source at the time of data reading is reduced. be able to. As a result, the leak current flowing through the bit line can be reduced, and the read margin can be made sufficiently wide. In addition, the number of times the voltage is applied simultaneously with the memory cell to be read for one memory cell is at most about the number of memory cells in the reading unit, and the number of times of voltage application per memory cell is reduced. Electrical stress applied to the memory cell is reduced, and reliability can be improved.

  Furthermore, a current measurement circuit, a current comparison circuit, and a division circuit that divides a plurality of source lines and automatically sets them as a readout unit, or a readout unit storage circuit that stores one or more source lines constituting the readout unit In the semiconductor memory device, it is possible to set an upper limit of the leakage current in advance and set a read unit equal to or lower than the upper limit in a shipping test or the like, so that the determination of logic “0” becomes difficult. It is possible to suppress the leakage current from exceeding the upper limit of the reference bit line current.

  Further, since any number of source lines can be selected and set as a read unit for each bit line, the number of times of switching the bias for reading data can be reduced as much as possible while suppressing an increase in bit line current. Is possible.

  Further, even if an over-erased memory cell is included in the read unit, the number of memory cells connected to one source line is minimized and one source line is grouped into one group. Therefore, it is possible to suppress the leakage current from greatly exceeding the upper limit of the reference bit line current as the determination of logic “0” becomes difficult.

  According to another aspect of the present invention, there is provided a method for operating a semiconductor memory device including a plurality of nonvolatile memory cells arranged in a matrix, wherein: (i) the plurality of nonvolatile memory cells in one row Dividing the source line connected to the source region into one or more groups; and (ii) in a state in which electrons accumulated in the floating gate of the nonvolatile memory cell in the group are extracted, Measuring a sum of leak currents flowing through each of the source lines; (iii) comparing a sum of the leak currents with a preset reference current value; and (iv) in one bit line. If even one of all the groups has a total leakage current that exceeds the reference current value, the number of source lines is smaller than that of each group. And (v) repeating the items (i) to (iv), and the sum of the leakage currents of all the groups in the one bit line is equal to or less than the reference current value. (Vii) when reading data from the non-volatile memory cell, selecting the source lines in batches for each read unit and grounding them. A semiconductor memory device operating method is provided.

  According to the present invention, each source line in one bit line is divided into one or more groups, and the leakage current flowing through each group is measured in a state where data of memory cells connected to the source line in each group is erased. Then, when the leakage current of any one group exceeds a predetermined reference current value, it is further subdivided into a group composed of a small number of one or more source lines. Then, when the leakage current becomes equal to or less than a predetermined reference current value, those groups are set as a reading unit.

  Therefore, the bit line current can be divided into as few read units as possible per bit line while maintaining a predetermined range. For this reason, it is possible to reduce the number of times of switching the bias for data reading as much as possible while suppressing an increase in the bit line current.

  Further, even if an over-erased memory cell is included in the group, the number of memory cells connected to one source line is set to one and the minimum one source line is set as one read unit. Therefore, it is possible to suppress the leakage current from greatly exceeding the upper limit of the reference bit line current as the determination of logic “0” becomes difficult.

  According to still another aspect of the present invention, there is provided a method of operating a semiconductor memory device including a plurality of nonvolatile memory cells arranged in a matrix, wherein (i) the plurality of nonvolatile memories in one row Dividing a source line connected to a source region of the cell into a plurality of groups; and (ii) in a state in which electrons accumulated in the floating gate of the nonvolatile memory cell in the group are extracted, Measuring a sum of leak currents flowing through each of the source lines; (iii) comparing a sum of the leak currents with a preset reference current value; and (iv) in one bit line. When the leakage currents of all the groups are equal to or less than the reference current value, the sub-division into groups composed of a larger number of source lines than each group. And (v) repeating the items (i) to (iv), when the leakage current exceeds the predetermined reference current value even in one of all the groups in the one bit line, (Vii) when reading data from the memory cell, the step of setting each group that has been set immediately before and the leakage current of all the groups in the one bit line is equal to or less than a predetermined reference current value, and (vii) In addition, there is provided a method of operating a semiconductor memory device, characterized in that the source lines are selected and grounded for each read unit.

  According to the present invention, contrary to the configuration of the invention according to another aspect, when the leakage current of all the groups in one bit line is equal to or lower than the reference current value, the number of source lines is larger than that of each group. Subdivided into configured groups, and when any one of the leak currents of all the groups in one bit line exceeds the reference current value, it is set immediately before and all of the bits in one bit line are set. Each group in which the leakage current of the group is equal to or less than a predetermined reference current value is set as a reading unit.

  Therefore, the bit line current can be divided into as few read units as possible per bit line while maintaining a predetermined range. For this reason, it is possible to reduce the number of times of switching the bias for data reading as much as possible while suppressing an increase in the bit line current.

  Further, even if an over-erased memory cell is included in the group, the number of memory cells connected to one source line is set to one and the minimum one source line is set as one read unit. Therefore, it is possible to suppress the leakage current from greatly exceeding the upper limit of the reference bit line current as the determination of logic “0” becomes difficult.

  According to the present invention, when data is read from a memory cell, it is possible to prevent the leakage current from flowing significantly exceeding the upper limit of the reference bit line current as the determination of logic “0” becomes difficult. Therefore, it is possible to suppress erroneous determination of logic data due to the leakage current of the memory cell as much as possible without narrowing the read margin. In addition, since the number of times of voltage application per memory cell can be reduced, electrical stress applied to one memory cell is reduced, and the reliability of the device can be improved.

  In addition, since an arbitrary number of source lines can be selected for each bit line and a group can be set, the number of times of bias switching for reading data per bit line can be reduced as much as possible while suppressing an increase in bit line current. Is possible.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
FIG. 4 is a circuit diagram showing a NOR flash memory device according to the first embodiment of the present invention. In FIG. 4, the structure of the memory cell array is simplified for explanation. One memory cell is provided in the square. The flash memory includes a large number of internal circuits, but only those that are particularly necessary are described here.

  FIG. 5 is a circuit diagram showing a specific arrangement of each memory cell in FIG. FIG. 6 is a cross-sectional view showing the structure of one memory cell in FIG. FIG. 7A is a circuit diagram showing a specific configuration of the VSS decoder in the source line selection circuit in the circuit of FIG. FIG. 7B is a truth table for selecting the source line Vssk by a digital signal. FIG. 8A is a circuit diagram showing a specific configuration of the read unit setting circuit connected to the VSS decoder of FIG. 7B in the circuit of FIG. FIG. 8B is a diagram illustrating a register (read unit storage circuit) that stores a read unit.

  In the NOR type flash memory according to the embodiment of the present invention, as shown in FIG. 4, a memory cell array 20 in which memory cells are arranged in rows and columns, a word line selection circuit (coder in words) 21, a source line A selection circuit 22, a bit line selection circuit 26, a sense circuit 27, and a current measurement circuit 28 are provided.

  In the memory cell array 20, as shown in FIG. 5, memory cells Tij (i = 0 to m, j = 0 to n) are arranged in rows and columns. 5 shows a part of the configuration of FIG. Each memory cell Tij is composed of an n-channel insulated gate field effect transistor having a floating gate. As shown in FIG. 6, the main structure is that a gate insulating film 12, a floating gate 13, an intermediate insulating film 14, and a control gate 15 are stacked in this order on a p-type semiconductor substrate 11. An n-type source region 16a and drain region 16b are formed on the surface of the semiconductor substrate 11 on both sides. The external lead terminal of the transistor connected to the source region 16a is referred to as a source, and the external lead terminal of the transistor connected to the drain region 16b is referred to as a drain.

  The memory cell Tij has a medium threshold voltage in a state where data is erased. When reading data, the channel is easily conducted by applying a positive operating voltage of 5V or less to the control gate, the positive operating voltage of 5V or less is applied to the drain, and the drain current is reduced by grounding the source. It is in the state of flowing logic '1' data. Writing to the memory cell Tij has a high threshold voltage, and the gate voltage does not conduct the channel, resulting in a logic '0' data state in which no current flows between the drain and source.

  As shown in FIG. 5, all memory cells Tij arranged in each row direction (horizontal direction on the paper surface) are connected to each common bit line BLi (i = 0 to m) via the drain, and each column direction (paper surface). All the memory cells Tij arranged in the vertical direction are connected to common word lines WLj (j = 0 to n) through gates (control gates).

  Furthermore, all the memory cells Tij connected to one bit line BLi are connected one source at a time to one source line Vssk (k = 0 to n).

  As shown in FIG. 4, each bit line BLi (i = 0 to m) is connected to a bit line selection circuit 26, and a specific bit line BLi is assigned by the bit line selection circuit 26 at the time of data writing and reading. Selected. When erasing data, all the bit lines BLi may be selected at once, or may be selected for each of one or more partial bit lines BLi. Further, all the bit lines BLi (i = 0 to m) are connected to the sense circuit 27 via the bit line selection circuit 25, and the bit line current IBL flowing through the selected bit line BLi is detected when reading data. .

  Each word line WLj (j = 0 to n) is connected to the word line selection circuit 21, and a specific word line WLj is selected by the word line selection circuit 21 when data is written and read. When erasing data, all the word lines WLj may be selected at once, or may be selected for each partial group.

  Each source line Vssk (k = 0 to n) is connected to the source line selection circuit 22 via the word line selection circuit 21.

  The source line selection circuit 22 includes a VSS decoder 23 shown in FIG. 7A, a read unit setting circuit 24 shown in FIG. 8A, and a read unit storage circuit 25 shown in FIG. 8B. Yes.

  As shown in FIG. 7A, the VSS decoder 23 includes an n-channel MOS transistor STk having a switching function for each source line Vssk (k = 0 to n). In order to simplify the explanation, it is assumed in this embodiment that eight source lines Vssk and eight transistors STk (n = 7) are provided. Each transistor STk has a drain connected to one source line Vssk and a source connected to a source line fixed at zero potential. When a selection signal (high level signal) φk (k = 0 to n) is input to the gate of the transistor STk, the transistor STk is turned on and the source line Vssk is grounded. On the other hand, when a non-selection signal (low level signal) φk is input, the transistor STk is turned off and the source line Vssk enters a floating state. The selection signal and the non-selection signal are output from a logic circuit connected to the gate of each transistor STk based on a combination of six digital signals A0 to A2 and A0 (−) to A2 (−). The digital signals A0 (−) to A2 (−) represent inverted signals of the digital signals A0 to A2. A truth table of the logic circuit is shown in FIG. In this embodiment, six digital signals A0 to A2, A0 (−) to A2 (−), and at the same time, a selection signal for the word line WLi. A specific word line WLi is selected by their combination.

  In the VSS decoder 23, all the transistors STk are turned on in an inactive state, and all the source lines VSSk are collectively set to the ground level. On the other hand, by activating the VSS decoder 23, each transistor STk can be individually controlled.

  Next, the read unit setting circuit 24 shown in FIG. 8A and the read unit storage circuit 25 shown in FIG. 8B will be described.

  As shown in FIG. 8A, the read unit setting circuit 24 is connected between source lines Vss0 and Vss1, between source lines Vss2 and Vss3, between source lines Vss4 and Vss5, and between source lines Vss6 and Vss7. Each transistor TR0 is connected via a source / drain region, and a signal line LR0 is connected to the gate thereof. The selection signal SR0 is input from the read unit storage circuit 25 to the signal line LR0. When the selection signal SR0 is a high level signal, the source lines connected to the transistor TR0 are connected to each other and set as a read unit.

  A transistor TR1 is connected between the source lines Vss1 and Vss2 and between the source lines Vss5 and Vss6 via source / drain regions, and a signal line LR1 is connected to the gate thereof. The selection signal SR1 is input from the read unit storage circuit 25 to the signal line LR1. When the selection signals SR0 and SR1 are high-level signals, four source lines Vss0 to Vss3 and Vss4 to Vss7 connected to the transistors TR0 and TR1 are connected to each other and set as a read unit.

  The transistor TR2 is connected between the source lines Vss3 and Vss4 via the source / drain region, and the signal line LR2 is connected to the gate thereof. The selection signal SR2 is input from the read unit storage circuit 25 to the signal line LR2. When the selection signals SR0, SR1, and SR2 are high level signals, all eight source lines Vss0 to Vss7 connected to the transistors TR0, TR1, and TR2 are connected and set as a read unit.

  In this embodiment, the read unit storage circuit 25 is constituted by a register of 3 bits (R0 to R2) per bit line, and stores digital signals SR0, SR1, SR2 for setting a read unit. Such a register is provided for each bit line BLi. Note that one common register may be provided for each bit line BLi. In this case, the read unit setting is common to each bit line BLi.

  When “0” is set to R0 and “0” is set to the other R1 and R2, the reading unit is composed of the above-mentioned two pairs of source lines, “1” is set to R0 and R1, and “2” is set to “2”. When “0” stands, the read unit is composed of the above-mentioned four source line groups, and when “1” stands for all of R0 to R2, the read unit is composed of the above eight source lines.

  In the flash memory device of FIG. 4, the read unit data is input to the read unit storage circuit 25 by the measurer and others based on the current value measured by the current measurement circuit 26 and manually input from the outside. Is done.

  Next, a method for setting a read unit in the source line selection circuit 22 will be described. For example, when the flash memory device of FIG. 4 is tested after manufacture, the read unit storage circuit 25 externally has a read unit of 8 source lines per bit line, a read unit of 4 source lines, and The source line selection circuit 22 is operated by sequentially setting in the case of reading units of two source lines, and the current measuring circuit 26 measures the leakage current of each reading unit in each of the above cases. In this case, the measurement may be advanced when the number of source lines in the reading unit is large and sequentially decreased, or conversely, the measurement may be advanced when the number of source lines is small and sequentially increased.

  In the measurement, the gate is grounded, and a small potential of about 1 V is applied between the source / drain. The measured current value is examined based on the reference current value determined in advance by the measurer and others. Note that this reference current value is set at a position considerably lower than the reference current value described with reference to FIG. In each case, when any one of all read units exceeds the reference current value, '0' is stored in the register bit of the corresponding read unit storage circuit 25, and all read units are stored. When the current value is less than or equal to the reference current value, “1” is stored in the register bit of the corresponding read unit storage circuit 25. For example, in the case of the readout unit of 2 source lines and the readout unit of 4 source lines, the readout current is less than the reference current value for all readout units, and is the reference in the case of the readout unit of 8 source lines. If the current value is exceeded, '1' is set for R0 and R1, and '0' is set for R2.

  By performing such setting for each bit line BLi, read unit data corresponding to all the bit lines is stored.

  Next, a method of operating the flash memory device of FIG. 4 in which the read unit is set in the read unit storage circuit 25 will be described.

  That is, in order to read data from the flash memory, a certain bit line BLi (i = 0 to m) is selected. Based on the address data, read unit data is output from the read unit storage circuit 25, and the read unit setting circuit shown in FIG. 8A sets a read unit for every four source lines. At this time, the VSS decoder is activated and each source line can be controlled. Next, a desired memory cell Tij is selected by the word line WLj (j = 0 to n), the source (source line Vssk) is grounded, and an appropriate positive voltage is applied to the drain (bit line BLi) at 5 V or less. And an appropriate positive voltage of 5 V or less is applied to the control gate 15 (word line WLj). In this case, since the selection signal A0 to A2 and A0 (-) to A2 (-) of the source line Vssk is used as the selection signal for the word line WLj, the corresponding read unit is used for the selected word line WLj. Only the source line to which it belongs is grounded, and the other source lines in the same bit line BLi are floating.

  When logic “0” data is written in the selected memory cell Tij, the drain current does not flow or is small. On the other hand, three memory cells Tij are grounded. However, these memory cells Tij are not selected so that the gate potential is set to the ground potential, the leakage current is small, and the logic “0” data is erroneously determined. As much as the bit line current (IBL) does not flow. On the other hand, when the corresponding memory cell is in the logic “1” data state, a large drain current flows, so there is almost no influence of the other three grounded memory cells Tij. Therefore, by measuring the bit line current (IBL), the data of logic “0” or logic “1” stored in the desired memory cell Tij can be accurately read.

  On the other hand, at the time of data reading, the unselected bit line is opened, the word line is set to the ground potential, and the source line is opened.

  In order to erase the logic “0” data, all the memory cells Tij are selected, and the source (all source lines Vssk (k = 0 to n) are grounded and the drain (all bit lines (BLi (i = 0 to m)) is made floating, and a large negative voltage of about −10 V is applied by the control gate 15 (all word lines (WLj (j = 0 to n)). When activated, all the source lines are fixed to the ground potential, whereby electrons in the floating gate 13 tunnel through the gate insulating film 12 and are emitted to the semiconductor substrate 11 to erase data. Alternatively, it can be performed for each memory cell Tij in an appropriate block.

  On the other hand, when erasing data, the unselected bit line is opened, the word line is set to the ground potential, and the source line is opened.

  Next, for writing, a desired memory cell Tij is selected by the bit line BLi and the word line WLj, the source (source line Vssk) is grounded, and a positive voltage of about 5 V is applied to the drain (bit line BLi). And a large positive voltage of about 10 V is applied to the control gate. As a result, hot electrons are generated mainly in the vicinity of the drain region 16b due to the voltage between the source and the drain, and electrons are injected and accumulated in the floating gate 14 due to the large positive voltage of the control gate 15. As a result, logic “0” data is written in the desired memory cell Tij. In this state, the memory cell Tij has a high threshold voltage, and even when an operating voltage is applied to the control gate 5, the channel does not conduct, and the drain current does not flow, or even if it flows, the leakage current is small.

  On the other hand, at the time of data writing, unselected bit lines (other than BLi) are opened, the word lines are set to the ground potential, and the source lines are opened.

  As described above, in the flash memory according to the first embodiment of the present invention, each bit line BLi is connected to one source line Vssk for each memory cell Tij. In addition, for each bit line BLi, a source line selection circuit 22 that collectively selects four source lines Vssk as a read unit is provided.

  Therefore, when data is read from the memory cell Tij, a voltage is applied to the selected bit line BLi, the four source lines Vssk belonging to the selected read unit are grounded, and the other source lines Vssk are made floating. Thus, the number of memory cells to which a voltage is applied between the drain and source simultaneously with the memory cell Tij to be read can be reduced. As a result, the leakage current flowing through the bit line BLi can be reduced, and the read margin can be made sufficiently large. For this reason, erroneous determination of logic data due to the leak current of the memory cell can be suppressed as much as possible.

  Furthermore, in a specific memory cell, the number of times the voltage is applied simultaneously with the memory cell Tij to be read is at most about the number of memory cells in the read unit, and the number of times the read voltage is applied per memory cell is greatly increased. Can be reduced. For this reason, electrical stress applied to one memory cell is reduced, and reliability can be improved.

  In addition, for each bit line BLi, a plurality of source lines Vssk can be selected and the read unit can be set, so the increase in the bit line current IBL can be suppressed and the number of bias switching times for reading data per bit line BLi can be reduced. It is possible to reduce as much as possible.

  In the flash memory according to the above embodiment of the present invention, as shown in FIG. 5, for each bit line BLi, one memory cell Tij or the like is independently connected to one source line Vssk or the like. However, as shown in FIG. 15, for each bit line BLi, two memory cells Tij, Tij + 1, etc. may be independently connected to one source line Vssk, etc.

  Furthermore, the number of memory cells connected to one source line Vssk can be any number of one or more depending on the level of manufacture, that is, whether the leakage current is large or small.

  In the above embodiment, the six digital signals A0 to A2 and A0 (−) to A2 (−) are not only the selection signal for the word line WLi but also the selection signal for the source line Vssk. In the case where a plurality of memory cells are connected to one source line as in the case where the selection signal for the word line WL is used, the selection signal for the source line Vssk cannot be used as it is. It is good to do as follows. That is, in the above embodiment, as shown in the table of FIG. 7B, the source line (Vssk) can be selected by changing the least significant bit A0 or A0 (−), but as shown in FIG. In this case, as shown in the table of FIG. 7B, the source line (Vssk) can be selected by changing the higher bits A1 or A1 (−), or A2 or A2 (−). For example, when two memory cells are connected to one source line (Vssk), the memory cell is selected by changing the least significant bit A0 or A0 (−) of the selection signal of the word line WLi, but the source line ( Vssk) can be selected by changing A1 or A1 (-). Further, in the case where four memory cells are connected to one source line (Vssk), the source line (Vssk) can be selected by a change of A2 or A2 (−) at a higher level.

(Second Embodiment)
FIG. 9 is a circuit diagram showing a NOR flash memory device according to the second embodiment of the present invention. FIG. 10 is a circuit diagram showing a configuration of a current comparison circuit in the NOR type flash memory device.

  In the second embodiment, as shown in FIG. 9, in addition to the configuration of the first embodiment, a current comparison circuit 29 is further provided.

  The current comparison circuit 29 includes a current measurement circuit described in the first embodiment, a reference current source capable of setting a reference current value manually from the outside or automatically inside, a reference current value thereof, a source A circuit for comparing a leakage current value flowing in a read unit constituted by a single line Vssk or a plurality of source lines Vssk. As a part of the configuration of the current comparison circuit 29, a sense amplifier in the sense circuit 27 is used. As the reference current value, an upper limit value (hereinafter simply referred to as “upper limit value”) of a current from which logic “0” data can be read is set. The comparison determination result is output as a digital signal INA from the sense amplifier for each reading unit. For example, when the leak current exceeds the reference current value, “0” is output, and when the leak current is equal to or less than the reference current value, “1” is output.

  Using this current comparison circuit 29, one or more source lines Vssk can be set as a read unit by the following method as an example. FIG. 11 is a flowchart showing the method.

  First, after erasing data of all memory cells Tij in one bit line BLi, the VSS decoder 23 is deactivated and all source lines Vssk are grounded. Here, erasing data means extracting electrons stored in the floating gate. same as below.

  Further, a ground potential is applied to the word line WLj, and a positive voltage of 1 V or less is applied to the bit line BLi. In this state, the leakage current flowing through the bit line BLi is measured (steps (i) and (ii) above) and compared based on the reference current value (step (iii)). The leak current flowing through the bit line BLi is the total sum of leak currents flowing through all the source lines Vssk constituting the read unit. same as below. In this case, for example, display is performed so that the comparison determination result can be seen from the outside.

  Next, when the current of the bit line BLi exceeds the reference current value, that is, when “0” is displayed on the display device, a group of a smaller number of source lines Vssk for all the source lines Vssk of the bit line BLi. (Steps (iv) and (i)), and is stored in the read unit storage circuit 25 as a new read unit. On the other hand, when the current of the bit line BLi is equal to or less than the reference current value, all the source lines Vssk in the bit line BLi are set as a reading unit at a time.

  Next, for each read unit, all the source lines Vssk belonging to the read unit are grounded and the leakage current is measured (step (ii)), and compared based on the reference current value (step (iii)).

  Next, when at least one current per reference unit exceeds the reference current value, that is, when “0” of the output data of the display device is displayed, all the source lines Vssk of the bit line BLi are displayed. It is subdivided into groups composed of a smaller number of source lines Vssk than the previously set group (step (iv)), and stored in the read unit storage circuit 25 as a new read unit. On the other hand, when the currents of all the reading units are equal to or less than the reference current value, the provisional reading unit at this time is set as the formal reading unit.

  In this way, the current measurement, the current comparison, and the division are repeated until the current values of all the read units are equal to or lower than the reference current value or until the source line Vssk in the read unit becomes one (step (v) ). As a result, for each bit line BLi, the leakage current of all read units becomes equal to or less than the reference current value.

  Then, finally, for each bit line BLi, the read unit in which the leakage current of all the read units is equal to or lower than the reference current value is stored in the read unit storage circuit 25.

  Thus, in the NOR flash memory device, a read operation is performed for each read unit stored in the read unit storage circuit 25 for each selected bit line BLi (step (vi)).

  As described above, according to the second embodiment, since the current comparison circuit 29 is provided, it can be automatically performed that the measurer or the like has performed the comparison determination in the first embodiment. .

  In the measurement of the leakage current for setting the reading unit, the measurement is sequentially shifted from the group including a large number of source lines Vssk to the group including a small number of source lines Vssk. Such a method is effective when the leak current per memory cell is relatively small.

  Further, the bit line current IBL can be divided into as few read units as possible per bit line BLi while maintaining the bit line current IBL below the reference current value. Therefore, it is possible to reduce the number of times of switching the bias for reading data per bit line BLi as much as possible while suppressing the increase in the bit line current IBL.

  Even if the memory cell that is over-erased is included in the read unit, the number of memory cells connected to one source line Vssk is reduced to one, and one source line Vssk is read at least once. Since the unit can be used as a unit, it is possible to suppress the leakage current from greatly exceeding the reference current value as the determination of logic “0” is difficult.

(Third embodiment)
FIG. 12 is a circuit diagram showing a NOR flash memory device according to the third embodiment of the present invention.

  In the third embodiment, an automatic dividing circuit 30 is provided as compared with the configuration of the second embodiment. The automatic division circuit 30 receives the comparison determination result signal from the current comparison circuit 29, determines a read unit based on the comparison determination result signal, and inputs a read unit setting signal to the source line selection circuit 22a. The automatic dividing circuit 30 has a circuit configuration shown in FIG.

  The circuit configuration shown in FIG. 13 includes a division determination circuit 31 and a read unit storage circuit 25.

  As shown in FIG. 13, the division determination circuit 31 is composed of three flip-flops F / F0, F / F1, and F / F2, and in the case of each reading unit of two source lines, reading of four source lines is performed. The current comparison determination result INA for each read unit is sequentially input from the current comparison circuit 29 corresponding to the unit and the read unit of 8 source lines. In each case, “1” is output when all the reading units are below the reference current value, and “0” is output when any one of the reading units exceeds the reference current value. Output. The read unit storage circuit 25 is functionally the same as that of the first and second embodiments. However, it is possible to automatically input data as in the first and second embodiments. Different. The output of the read unit storage circuit 25 is input to the read unit setting circuit 24 in the source line selection circuit 22. The division determination circuit 31 operates when activated, sets a read unit in the read unit storage circuit 25, stops operating when deactivated, and the storage data of the read unit storage circuit 25 is held. . This division determination circuit 31 is activated and operated mainly during a shipping test.

  One or more source lines Vssk can be set as a read unit by the following method as an example using the NOR flash memory device shown in FIG. FIG. 14 is a flowchart showing the method.

  As shown in FIG. 14, first, for the eight source lines Vssk provided in advance for one bit line, two source lines are grouped into four groups (step (i)).

  Next, after erasing data of all memory cells connected to the source line Vssk for each group, a ground potential is applied to the word line WLj, a positive voltage of about 1 V is applied to the bit line BLi, and the source line Vssk is applied. With the grounded, the leakage current is measured for each group (step (ii)). The leakage current value is compared with the reference current value (step (iii)), and the determination result is sequentially input to F / F0. In F / F0, when even one of all the groups has a leak current exceeding a preset reference current value, “0” is output. On the other hand, when all the reading units are equal to or less than the reference current value, “1” is output.

  If the output of F / F0 is '0', the output will not become '1' even if the number of source lines Vssk constituting the read unit is increased. Outputs 0 '. As a result, one source line Vssk is set as a read unit.

  On the other hand, when the output of F / F0 is “1”, the number of source lines Vssk constituting the group is set to four and subdivided into two groups (step (iv)).

  Next, after erasing the data of all the memory cells connected to the source line Vssk for each group, the leakage current is measured for each group. The leak current value is compared with the reference current value, and the determination result is sequentially input to F / F1. F / F1 outputs “0” when the leakage current exceeds a preset reference current value in any group. On the other hand, when all the reading units are equal to or less than the reference current value, “1” is output.

  When the output of F / F1 is “0”, even if the number of source lines Vssk constituting the read unit is increased, the output will not become “1”, so “0” is also output to F / F2 To do. As a result, two source lines Vssk are set as read units.

  On the other hand, when the output of F / F1 is “1”, the number of source lines Vssk constituting the group is eight, which is the number of all source lines Vssk in the bit line BLi.

  Next, after erasing data of all the memory cells connected to the bit line BLi, the leak current is measured collectively. The leak current value is compared with the reference current value, and the determination result is sequentially input to F / F2. F / F2 outputs “0” when the leakage current exceeds a preset reference current value. On the other hand, “1” is output when the leakage current is equal to or less than the reference current value.

  When the output of F / F2 is “0”, as a result, four source lines Vssk are set as read units. On the other hand, when the output of F / F1 is “1”, the entire bit line BLi is set as a read unit (step (v)).

  As a result, in the NOR flash memory device, a read operation is performed for each selected read line for each read unit finally set as described above (step (vi)).

  As described above, according to the third embodiment, since the automatic dividing circuit 30 is provided, the reading unit can be automatically set.

  Contrary to the second embodiment, the leakage current measurement is shifted from a group including a small number of source lines to a group including a large number of source lines. Such a method is effective when the leakage current per memory cell is relatively large.

  Also in this case, the bit line current can be divided into as few read units as possible per bit line while maintaining a predetermined range. Therefore, it is possible to reduce the number of times of switching the bias for reading data per bit line as much as possible while suppressing an increase in the bit line current.

  Further, even if the read unit includes memory cells that are over-erased, the number of memory cells connected to one source line is minimized and one source line is regarded as one read unit. Therefore, it is possible to suppress the leakage current from exceeding the reference current value as the determination of logic “0” becomes difficult.

  The flash memory device and the operation method thereof according to the present invention have been described in detail above according to the embodiments. However, the scope of the present invention is not limited to the examples specifically shown in the above embodiments, and Modifications of the above-described embodiment without departing from the scope of the present invention are included in the scope of the present invention.

  For example, in the above-described embodiment, the present invention is applied to the case where eight word lines WLj and source lines Vssk are configured. However, the present invention is also applicable to a case where any number of word lines WLj and source lines Vssk are configured. The present invention can be applied.

  In the above embodiment, the number of source lines Vssk constituting the read unit is set to 2, 4, and 8, but the present invention is not limited to this. It can be set arbitrarily.

  Further, although the read unit setting circuit 24 in the source line selection circuit 22 has the configuration shown in FIG. 8A, it is not limited to this. Any circuit configuration may be used as long as one or more source lines Vssk are collectively selected by a signal for setting a read unit that is set manually or automatically.

  Further, although the automatic dividing circuit 30 having the configuration shown in FIG. 12 is used, the present invention is not limited to this. It is only necessary to have a function of supplying a readout unit setting signal to the readout unit setting circuit 24 based on the actually measured leakage current value. The read unit setting circuit 24 and the automatic division circuit 30 may be configured so as to exhibit a function of collectively selecting one or more source lines Vssk for each bit line BLi.

  In the second embodiment, leakage current measurement is sequentially shifted from a group including a large number of source lines Vssk to a group including a small number of source lines Vssk. On the contrary, the third embodiment is described. As described above, the leakage current measurement may be sequentially transferred from a group including a small number of source lines Vssk to a group including a large number of source lines Vssk. In the third embodiment, the leakage current measurement is sequentially shifted from the group including a small number of source lines Vssk to the group including a large number of source lines Vssk. On the contrary, the second embodiment is described. As described above, the leakage current measurement may be sequentially transferred from a group including a large number of source lines Vssk to a group including a small number of source lines Vssk.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A plurality of nonvolatile memory cells arranged in a matrix, a word line commonly connected to the control gates of the plurality of nonvolatile memory cells in one column, and a drain region of the plurality of nonvolatile memory cells in one row When reading the commonly connected bit lines, the source lines connected to the source regions of the plurality of nonvolatile memory cells in one row, and the nonvolatile memory cells connected to one of the bit lines, A semiconductor memory device comprising: a source line selection circuit that selects one or more of the source lines as a read unit according to a bit line, and grounds the source line.

(Appendix 2)
2. The semiconductor memory device according to appendix 1, wherein the source line is common to adjacent bit lines.

(Appendix 3)
The supplementary note 1 or 2, further comprising: a current measuring circuit that collectively measures a leakage current in a state in which the data of the memory cells connected to all the source lines included in the read unit are erased for each of the read units. 3. The semiconductor memory device according to any one of 2.

(Appendix 4)
The semiconductor memory device according to claim 4, further comprising a current comparison circuit that compares a reference current value set in advance with each of the bit lines and a leakage current measured for the read unit.

(Appendix 5)
The semiconductor memory device according to appendix 4, wherein the reference current value can be set from outside the current comparison circuit.

(Appendix 6)
7. The semiconductor memory device according to claim 1, further comprising a read unit memory circuit that stores one or more source lines constituting the read unit for each bit line.

(Appendix 7)
For each of the bit lines, based on the current comparison result of the current comparison circuit, the plurality of source lines are divided and set as the read unit, and a signal for collectively selecting each read unit is selected as the source 6. The semiconductor memory device according to any one of appendix 4 or 5, further comprising a dividing circuit for supplying to the line selection circuit.

(Appendix 8)
A method of operating a semiconductor memory device including a plurality of nonvolatile memory cells arranged in a matrix, wherein (i) one or more source lines connected to source regions of the plurality of nonvolatile memory cells in one row And (ii) a sum of leakage currents flowing through the source lines in the group in a state where electrons accumulated in the floating gates of the nonvolatile memory cells in the group are extracted. (Iii) a step of comparing the total sum of the leak currents with a preset reference current value; and (iv) at least one of all the groups in the one bit line. Subdividing into a group composed of a smaller number of source lines than each group when the sum exceeds the reference current value; (V) When the sum of the leakage currents of all the groups in the one bit line is equal to or less than the reference current value by repeating the items (i) to (iv), (Vi) an operation of a semiconductor memory device, wherein (vi) when reading data from the non-volatile memory cell, the source lines are selected in batch for each read unit and grounded Method.

(Appendix 9)
The read unit acquired by performing the steps (i) to (v) is stored in advance in the semiconductor memory device for each bit line, and when reading data from the nonvolatile memory cell, The operation method of the semiconductor memory device according to appendix 8, wherein a read unit is read and used.

(Appendix 10)
An operation method of a semiconductor memory device including a plurality of nonvolatile memory cells arranged in a matrix, wherein (i) a plurality of source lines connected to source regions of the plurality of nonvolatile memory cells in one row Dividing into groups, and (ii) measuring the sum of leakage currents flowing through the source lines in the group in a state where electrons accumulated in the floating gates of the nonvolatile memory cells in the group are extracted. (Iii) a step of comparing the total sum of the leak currents with a preset reference current value; and (iv) the leak currents of all the groups in the one bit line are equal to or less than the reference current value. If there is, a step of subdividing into a group composed of a larger number of source lines than each group, (v) the items (i) to (iv) On the other hand, when even one of all the groups in the one bit line exceeds the predetermined reference current value, it is set immediately before, and all the groups in the one bit line are set. A step of setting each group whose leakage current is less than or equal to a predetermined reference current value as a read unit; and (vi) selecting the source lines in batch for each read unit when reading data from the memory cell. And grounding the semiconductor memory device.

(Appendix 11)
The read unit acquired by performing the steps (i) to (v) is stored in advance in the semiconductor memory device for each bit line, and when reading data from the nonvolatile memory cell, The operation method of the semiconductor memory device according to appendix 11, wherein a read unit is read and used.

FIG. 1 is a circuit diagram showing a NOR type flash memory according to a conventional example. FIG. 2A is a circuit diagram showing a problem of the NOR type flash memory according to the conventional example. FIG. 2B is also a graph. FIG. 3A is a cross-sectional view showing the structure of a memory cell of a NOR type flash memory according to a conventional example, and data writing / erasing. FIG. 3B is a cross-sectional view showing excessive erasure in the memory cell of the NOR type flash memory according to the conventional example. FIG. 4 is a circuit diagram showing the NOR flash memory device according to the first embodiment of the present invention. FIG. 5 is a schematic diagram showing the configuration of the memory cell array of the NOR type flash memory device of FIG. FIG. 6 is a cross-sectional view showing the structure of one memory cell in the memory cell array of FIG. FIG. 7A is a circuit diagram showing the configuration of the VSS decoder in the source line selection circuit of the NOR type flash memory device of FIG. FIG. 5B is a truth table of a selection signal for selecting the source line Vssk. FIG. 8A is a circuit diagram showing the configuration of the read unit setting circuit in the source line selection circuit of the NOR type flash memory device of FIG. FIG. 6B is a schematic diagram showing the configuration of the read unit storage circuit. FIG. 9 is a circuit diagram showing a NOR flash memory device according to the second embodiment of the present invention. FIG. 10 is a circuit diagram showing a configuration of a current comparison circuit of the NOR type flash memory device of FIG. FIG. 11 is a flowchart showing an operation method of the NOR flash memory device of FIG. FIG. 12 is a circuit diagram showing a NOR type flash memory device according to the third embodiment of the present invention. FIG. 13 is a circuit diagram showing a configuration of an automatic dividing circuit of the NOR type flash memory device of FIG. FIG. 14 is a flowchart showing an operation method of the NOR type flash memory device of FIG. FIG. 15 is a circuit diagram showing a NOR flash memory device according to another embodiment of the present invention.

Explanation of symbols

11 ... Semiconductor substrate,
12 ... Tunnel insulating film,
13 ... Floating gate,
14: Intermediate insulating film,
15 ... Control gate,
16a ... source region,
16b ... drain region,
21 ... Word line selection circuit (word decoder),
22, 22a ... Source line selection circuit,
23 ... VSS decoder,
24... Readout unit setting circuit,
25. Reading unit storage circuit,
26: Bit line selection circuit,
27 ... sense circuit,
28: Current measurement circuit,
29 ... Current comparison circuit,
30: Automatic dividing circuit,
31: Division determination circuit,
BLi ... bit line,
Tij ... memory cell,
Vssk ... source line,
WLj ... Word line.

Claims (10)

A plurality of non-volatile memory cells arranged in a matrix;
A word line commonly connected to control gates of a plurality of nonvolatile memory cells in one column;
A bit line commonly connected to drain regions of a plurality of nonvolatile memory cells in one row;
A source line connected to a source region of a plurality of nonvolatile memory cells in one row;
A source line selection circuit that selects one or more of the source lines as a read unit according to the bit line and reads the nonvolatile memory cells connected to one bit line, and grounds them A semiconductor memory device.   2. A current measuring circuit that measures leak current for each read unit at a time in a state where data of memory cells connected to all source lines included in the read unit is erased. The semiconductor memory device described in 1.   2. The semiconductor memory device according to claim 1, further comprising: a current comparison circuit that compares a reference current value set in advance with each of the bit lines and a leakage current measured for the read unit.   4. The semiconductor memory device according to claim 3, wherein the reference current value can be set from outside the current comparison circuit.   2. The semiconductor memory device according to claim 1, further comprising a read unit storage circuit that stores one or more source lines constituting the read unit for each bit line.   For each of the bit lines, based on the current comparison result of the current comparison circuit, the plurality of source lines are divided and set as the read unit, and a signal for collectively selecting each read unit is selected as the source 4. The semiconductor memory device according to claim 3, further comprising a dividing circuit for giving to the line selection circuit. A method for operating a semiconductor memory device comprising a plurality of nonvolatile memory cells arranged in a matrix,
(I) dividing the source lines connected to the source regions of the plurality of nonvolatile memory cells in one row into one or more groups;
(Ii) measuring a sum of leakage currents flowing through the source lines in the group in a state where electrons accumulated in the floating gate of the nonvolatile memory cell in the group are extracted;
(Iii) comparing the sum of the leakage currents with a preset reference current value;
(Iv) A group constituted by a smaller number of source lines than the respective groups when the sum of the leakage currents exceeds the reference current value even in one of all groups in the one bit line. Subdividing into
(V) Repeating the above items (i) to (iv), and reading the respective groups at that time when the sum of the leakage currents of all the groups in the one bit line becomes equal to or less than the reference current value. A step to set the unit,
(Vi) A method of operating a semiconductor memory device, wherein when reading data from the non-volatile memory cell, the source lines are selected in batch for each read unit and grounded.   The read unit acquired by performing the steps (i) to (v) is stored in the semiconductor memory device for each bit line in advance, and when reading data from the nonvolatile memory cell, 8. The method of operating a semiconductor memory device according to claim 7, wherein a read unit is read and used. A method for operating a semiconductor memory device comprising a plurality of nonvolatile memory cells arranged in a matrix,
(I) dividing a source line connected to source regions of the plurality of nonvolatile memory cells in one row into a plurality of groups;
(Ii) measuring a sum of leakage currents flowing through the source lines in the group in a state where electrons accumulated in the floating gate of the nonvolatile memory cell in the group are extracted;
(Iii) comparing the sum of the leakage currents with a preset reference current value;
(Iv) when the leakage currents of all the groups in the one bit line are equal to or less than the reference current value, subdividing into groups composed of a larger number of source lines than the groups;
(V) Repeating the items (i) to (iv) to set immediately before the leakage current exceeds the predetermined reference current value even in one of all the groups in the one bit line. Each group in which leakage current of all groups in the one bit line is equal to or less than a predetermined reference current value is set as a reading unit;
(Vi) A method of operating a semiconductor memory device, wherein when reading data from the memory cell, the source lines are selected in batch for each read unit and grounded.   The read unit acquired by performing the steps (i) to (v) is stored in the semiconductor memory device for each bit line in advance, and when reading data from the nonvolatile memory cell, 10. The method of operating a semiconductor memory device according to claim 9, wherein a read unit is read and used.

Images