JP2008241722A - Probe card and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To apply an accurate voltage to a power terminal of a semiconductor device, even if a contact resistance between a probe for voltage application and the power terminal of the semiconductor device is heightened, in a test of the semiconductor device. <P>SOLUTION: A probe card has an input terminal to which a voltage ia applied; a first probe for voltage application whose one end side is connected electrically to the input terminal, for applying the voltage applied to the input terminal from the other end side to a voltage application object; a first probe for voltage measurement for measuring a voltage of the voltage application object; and an output terminal connected electrically to one end side of the first probe for voltage measurement, for outputting a voltage measured at the other end side of the first probe for voltage measurement and transferred to one end side. The first probe for voltage application and the first probe for voltage measurement are arranged so that a distance between the other end of the first probe for voltage application and the other end of the first probe for voltage measurement is shorter than a distance between one end of the first probe for voltage application and one end of the first probe for voltage measurement. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a probe card used for testing a semiconductor device and a method for manufacturing a semiconductor device using the probe card.

  With reference to FIG. 12 and FIG. 13, a conventional operating voltage supply apparatus for a semiconductor device will be described. FIG. 12 is a diagram schematically showing a circuit configuration for explaining a conventional operating voltage supply apparatus and operating voltage supply method for a semiconductor device. FIG. 13 is a diagram for explaining a connection state between the power supply terminal of the semiconductor device under test and the probe.

  The voltage generator 10 includes a variable voltage power supply 12 and a voltage compensation circuit 14. As is well known, the variable voltage power supply 12 generates a voltage equal to the set voltage Vs set from the outside as required. In the following description, the voltage is based on the chassis ground of the voltage generator 10.

  The voltage compensation circuit 14 includes a first operational amplifier 30 and a second operational amplifier 40. The positive input terminal 32 of the first operational amplifier 30 is connected to the voltage input terminal 22 of the voltage compensation circuit 14. The output terminal 36 of the first operational amplifier 30 is connected to the voltage output terminal 24 of the voltage compensation circuit 14. The negative input terminal 34 of the first operational amplifier 30 is connected to the output terminal 46 of the second operational amplifier 40. The positive input terminal 42 of the second operational amplifier 40 is connected to the measurement voltage input terminal 26 of the voltage compensation circuit 14. The output terminal 46 of the second operational amplifier 40 is connected to the negative input terminal 44 of the second operational amplifier 40 to form a voltage follower circuit. By connecting the voltage output terminal 24 and the measurement voltage input terminal 26 of the voltage compensation circuit 14 with the conductor 28 and short-circuiting them, the first operational amplifier 30 also forms a voltage follower circuit via the conductor 28 and the second operational amplifier 40. Will do. Since the voltage compensation circuit 14 is configured as described above, it operates so that the set voltage Vs input to the voltage input terminal 22 is equal to the measurement voltage Vm input to the measurement voltage input terminal 26. That is, the voltage output terminal 24 outputs the voltage Vs + ΔV obtained by adding the difference voltage ΔV (= Vs−Vm) between the set voltage Vs and the measurement voltage Vm as the output voltage Vo. The internal connection of the voltage generator 10 is made by a printed circuit board, a disposed conductor, or the like according to the design.

  The probe card 51 includes a voltage application probe 55. The voltage application probe 55 electrically connects the voltage application pad 75 of the semiconductor device 72 to be tested and the voltage output terminal 24 of the voltage generator 10. The voltage output from the voltage output terminal 24 of the voltage generator 10 is applied to the voltage application pad 75 of the semiconductor device 72 to be tested.

  Although the voltage compensation circuit 14 ensures that the output voltage Vo at the voltage output terminal 24 of the voltage generator 10 is equal to the set voltage Vs, the applied voltage to the voltage application pad 75 of the semiconductor device 72 under test is In order to increase the accuracy, it is desirable that a measurement voltage at a location near the voltage application pad 75 is input to the measurement voltage input terminal 26 of the voltage generator 10.

  As a measurement probe for a semiconductor device, a probe in which a force probe and a sense probe are connected via a terminal provided in the semiconductor device has been proposed for measurement using a tester (for example, Patent Document 1).

On the other hand, with respect to voltage application, as described with reference to FIGS. 12 and 13, application with one probe is performed.
JP 2000-206146 A

  However, the above-described conventional voltage application method has the following problems. Now, a semiconductor device to be subjected to voltage measurement using a probe is a semiconductor device 72 to be tested. When the deposit 101 having a resistance component adheres to the tip of the voltage application probe 55, the contact resistance between the voltage application probe 55 and the voltage application pad 75 of the semiconductor device 72 to be tested increases. Even if a high-accuracy voltage is output from the voltage output terminal 24 of the voltage generator 10, a voltage drop occurs due to the resistance component of the deposit 101, and the set voltage is applied to the voltage application pad 75 of the semiconductor device 72 under test. The voltage becomes lower than that. It is considered that the adhered material 101 is mainly the one in which the aluminum or the like of the voltage application pad 75 of the semiconductor device 72 to be tested is cut and oxidized when the probe is brought into contact with the terminal.

  An example of a test with the deposit 101 attached will be described with reference to FIG. When the set voltage Vs is 3.0 V, a voltage of 3.0 V is supplied to the tip of the voltage application probe 55. Here, assuming that the current flowing through the voltage application probe 55 during operation of the semiconductor device 72 under test is 100 mA and the contact resistance due to the deposit 101 is 5Ω, the voltage application pad 75 has a voltage of 3.0 V− due to a voltage drop. Only a voltage of 5Ω × 100 mA = 2.5V is supplied.

  Assuming that the margin of the voltage applied to the voltage application pad 75 is 10%, when a voltage of about 3 V is applied to an LSI operating with a low voltage specification, a voltage lower than the set voltage is applied. Problems such as discriminating it as a non-defective product occur. In order to avoid this problem, the tip of the probe is generally polished. However, there is a problem that the productivity is lowered due to the time required for removing and polishing the probe card.

  FIG. 15 is a diagram illustrating a change in contact resistance with respect to the number of contact times of the probe. The horizontal axis indicates the number of contacts to the power supply terminal of the probe, and the vertical axis indicates the value of contact resistance. A curve I in FIG. 15 shows a change in the contact resistance of the probe when the probe is contacted to the power supply terminal with a current of 100 mA flowing. A curve II in FIG. 15 shows a change in the contact resistance of the probe when the probe is brought into contact with the power supply terminal in a state where no current flows. When contact is made with a current of 100 mA flowing, the contact resistance value increases with a smaller number of contacts than when no current is passed.

  When using a commercially available probe, even if it is used in a state where no current flows, contact resistance increases due to deposits, etc., but even if the number of contacts to the power supply terminal of the probe exceeds 3,000, contact Since the resistance is about 1Ω, it can be used without polishing (see FIG. 15: curve II).

  On the other hand, in a probe that is contacted while flowing a current of 100 mA, the contact resistance exceeds 5Ω with the number of contacts of about 500 (see curve I in FIG. 15). When the operating current is 100 mA, the voltage drop due to the contact resistance is 5Ω × 100 mA = 0.5V.

  If the applied voltage is greater than 5V, it is within the allowable range when the voltage margin is 10%. However, for example, in an LSI with a low voltage specification, when the applied voltage is 3.3V, the voltage margin deviates from 10%. End up.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to remove or attach a probe card or polish a probe even if the probe card is repeatedly used for supplying and measuring an operating voltage of a semiconductor device. And a method of manufacturing a semiconductor device using the probe card.

  In order to achieve the above-described object, the probe card according to the present invention has an input terminal to which a voltage is applied, one end side of which is electrically connected to the input terminal, and a voltage applied to the input terminal is applied from the other end side. A first voltage application probe to be applied to the object, a first voltage measurement probe for measuring the voltage to be applied, and one end side of the first voltage measurement probe; And an output terminal for outputting a voltage measured at the other end of the voltage measuring probe and transmitted to the one end. Here, the first voltage application probe and the first voltage measurement probe are the first voltage application probe based on the distance between one end of the first voltage application probe and one end of the first voltage measurement probe. It arrange | positions so that the distance of the other end of a probe and the other end of the 1st probe for voltage measurement may become short.

  According to a preferred embodiment of the probe card of the present invention, one end side is electrically connected to the input terminal, and a voltage applied to the input terminal is applied to the voltage application target from the other end side. It is preferable to arrange the probe so that the first voltage application probe is sandwiched between the first voltage measurement probe and the second voltage application probe.

  Further, according to a preferred embodiment of the probe card of the present invention, the second voltage measuring probe that is electrically connected to the output terminal at one end side and measures the voltage to be applied is replaced with the first voltage applying probe. And the second voltage measurement probe are preferably arranged so as to sandwich the first voltage measurement probe.

  In order to achieve the above-described object, according to the method for manufacturing a semiconductor device of the present invention, a test is performed on a semiconductor device provided with a voltage application pin exposed after assembly using the probe card described above. .

  A first voltage application probe and a first voltage measurement probe are brought into contact with the voltage application pin, and a predetermined voltage is applied from the first voltage application probe to the voltage application pin of the semiconductor device and applied. The voltage is transmitted to the first voltage measuring probe, and the voltage applied to the input terminal is adjusted based on the voltage at the output terminal of the probe card.

  According to another preferred embodiment of the method for manufacturing a semiconductor device of the present invention, a semiconductor device provided with a voltage application pin exposed after assembly using the probe card described above, wherein the voltage application pin and the semiconductor are provided. A semiconductor device provided with a voltage measuring pin electrically connected in the device is tested.

  A first voltage application probe is brought into contact with the voltage application pin, and a first voltage measurement probe is brought into contact with the voltage measurement pin, and a predetermined voltage is applied from the first voltage application probe to the voltage application pin of the semiconductor device. A voltage is applied, the applied voltage is transmitted to the first voltage measuring probe, and the voltage applied to the input terminal is adjusted based on the voltage of the output terminal of the probe card.

  According to the probe card of the present invention, the voltage application probe and the voltage measurement probe are connected to the power supply terminal provided in the semiconductor device under test so as to be separated from each other. A voltage applied to the voltage application pad is measured as a measurement voltage from a voltage measurement pad connected to the voltage application pad via a conductor. By changing the output voltage to the compensation voltage obtained by adding the set voltage and the measured voltage by the difference between the set voltage and the output voltage, an adhering substance having a resistance component adheres to the tip of the voltage application probe. Also, the set voltage is accurately applied to the power supply terminal.

  A current necessary for the operation of the semiconductor device under test flows through the voltage application probe, but this necessary current may exceed the allowable value of the voltage application probe. By providing a plurality of voltage application probes, there is an additional effect that the current flowing per probe can be reduced.

  By providing a plurality of voltage measurement probes, there is an additional effect that it is possible to reduce the probability of malfunction due to poor contact of the voltage measurement probes.

  If the resistance value of the deposit and the current flowing through the deposit are the same, the magnitudes of the voltage drops due to the resistance component of the deposit are equal, and the ratio increases as the applied voltage is lower. By using the method for manufacturing a semiconductor device of the present invention, it is possible to accurately apply a voltage even with an applied voltage of 3.3 V or less.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the configuration and the arrangement relationship are merely schematically shown to the extent that the present invention can be understood. Further, numerical conditions and the like are merely preferred examples, and therefore the present invention is not limited to the following embodiments.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram schematically showing a circuit configuration for explaining an operating voltage supply device to a semiconductor device of the present invention. FIG. 2 shows the connection between the voltage application probe 54 and the voltage measurement probe 56 and the semiconductor device, that is, the voltage application pad 74 and the voltage measurement pad 76 of the semiconductor device 70 to be tested which is the object of voltage supply and voltage measurement. It is a figure for demonstrating a state.

  The operating voltage supply device for a semiconductor device according to the present invention includes a voltage generator 10 and a probe card 50. The voltage generator 10 includes a variable voltage power supply 12 and a voltage compensation circuit 14. The voltage compensation circuit 14 includes a voltage input terminal 22, a voltage output terminal 24, a measurement voltage input terminal 26, a first operational amplifier 30, and a second operational amplifier 40. In the following description, the voltage is based on the chassis ground of the voltage generator 10. The ground of the semiconductor device under test is connected to the chassis ground of the voltage generator 10.

  The variable voltage power supply 12 generates a voltage equal to the set setting voltage Vs. The voltage generated by the variable voltage power supply 12 is applied to the voltage input terminal 22 of the voltage compensation circuit 14. The positive input terminal 32 of the first operational amplifier 30 is connected to the voltage input terminal 22 of the voltage compensation circuit 14. The output terminal 36 of the first operational amplifier 30 is connected to the voltage output terminal 24 of the voltage compensation circuit 14. An output voltage Vo is output from the voltage output terminal 24. The negative input terminal 34 of the first operational amplifier 30 is connected to the output terminal 46 of the second operational amplifier 40. The positive input terminal 42 of the second operational amplifier 40 is connected to the measurement voltage input terminal 26 of the voltage compensation circuit 14. The output terminal 46 of the second operational amplifier 40 is connected to the negative input terminal 44 of the second operational amplifier 40 to form a voltage follower circuit.

  The probe card 50 includes a voltage application probe 54 and a voltage measurement probe 56 so as to be separated from each other. Furthermore, the probe card 50 has an input terminal and an output terminal. The probe card 50 is detachable from the voltage generator 10 of the operating voltage supply device. When the probe card 50 is attached to the voltage generator 10, the input terminal of the probe card 50 is connected to the voltage output terminal 24 of the voltage generator 10, and the output terminal of the probe card 50 is measured by the voltage generator 10. Connected to the voltage input terminal 26. The voltage application probe 54 is electrically connected between the voltage application pad 74 provided on the semiconductor device 70 to be tested and the voltage output terminal 24 of the voltage generator 10, so that the semiconductor device 70 to be tested is connected. A voltage necessary for the operation is applied to the voltage application pad 74 as an output voltage. The voltage measurement probe 56 is electrically connected between the voltage measurement pad 76 provided on the semiconductor device 70 to be tested and the measurement voltage input terminal 26 of the voltage generator 10 to test the semiconductor device 70 to be tested. Is measured as a measurement voltage Vm. Here, the voltage application pad 74 and the voltage measurement pad 76 of the semiconductor device under test 70 are connected via a conductor 78 provided in the semiconductor device 70 under test, and the voltage application pad and the voltage measurement are measured. The pad potentials are equal.

  The voltage output terminal 24 and the measurement voltage input terminal 26 of the voltage compensation circuit 14 are connected via a voltage application probe 54, a voltage application pad 74, a conductor 78, a voltage measurement pad 76, and a voltage measurement probe 56. When the voltage output terminal 24 and the measurement voltage input terminal 26 are electrically connected, the first operational amplifier included in the voltage compensation circuit 14 also forms a voltage follower circuit. Since the voltage compensation circuit 14 is configured as described above, it operates so that the set voltage Vs input to the voltage input terminal 22 is equal to the measurement voltage Vm input to the measurement voltage input terminal 26. That is, the voltage Vs + ΔV obtained by adding the difference voltage ΔV (= Vs−Vm) between the set voltage Vs and the measured voltage Vm to the set voltage Vs is output as the output voltage Vo from the voltage output terminal 24. The internal connection of the voltage generator 10 is made by a printed circuit board or a disposed conductor according to the design. The voltage follower circuit can take an arbitrary value including 0Ω as a resistance value between the output terminal 36 and the negative input terminal 34 of the first operational amplifier 30. Therefore, even if the deposit 101 adheres to the vicinity of the tip of the voltage application probe 54 and the contact resistance between the voltage application probe 54 and the voltage application pad 74 of the semiconductor device 70 under test increases, the voltage is increased. It does not affect the operation of the follower circuit.

  Although the voltage compensation circuit 14 includes two operational amplifiers, the configuration of the voltage compensation circuit is not limited to this. The voltage compensation circuit includes a voltage input terminal, a measurement voltage input terminal, and a voltage output terminal, and the measurement voltage Vm input from the measurement voltage input terminal is equal to the set voltage Vs input to the voltage input terminal. Any configuration can be used as long as it is a compensation circuit having a function of adjusting the output voltage.

  FIG. 16 is a diagram illustrating a change in voltage drop with respect to the number of probe contacts. Here, the current required for the operation of the semiconductor device under test is 100 mA. The horizontal axis indicates the number of contacts of the probe with the power supply pad, and the vertical axis indicates the magnitude of the voltage drop when the current flowing through the probe is 100 mA. A curve III in FIG. 16 shows a change in voltage drop when the probe is contacted to the power supply pad with a current of 100 mA flowing through the probe. A curve IV in FIG. 16 shows a change in voltage drop when the probe is contacted with the power supply pad in a state where no current flows through the probe. If the voltage supply apparatus described so far is used, the polishing time of the probe is determined by the contact resistance of the probe that does not pass current, so the frequency of polishing can be reduced. When the margin for the applied voltage at the time of the test is 10%, the conventional method requires polishing with a contact count of about 200 times with an applied voltage of 3.3 V and about 100 times with an applied voltage of 2.0 V. However, the method of the present invention does not require polishing even if the number of contacts is 3000 or more. Thus, particularly when a low voltage of about 3.3 V at the maximum is applied to the semiconductor device under test, the effect of the present invention is remarkable. In other words, when the operating voltage is supplied to the voltage application pad of the semiconductor device under test using the operating voltage supply device for the semiconductor device, the set voltage can be varied to a maximum voltage of 3.3 volts. It is preferable to set the voltage power supply so that the voltage application probe is brought into contact with the voltage application pad, and at the same time, the voltage measurement probe is brought into contact with the voltage measurement pad.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a diagram schematically showing a circuit configuration of the second embodiment. The difference from the first embodiment is that a conductor is provided between the probe card 50 and the voltage generator 10. Other points are the same as in the first embodiment.

  A first conductor 64 that electrically connects the voltage output terminal 24 and the voltage application probe 54 is provided. In addition, a second conductor 66 that electrically connects the measurement voltage input terminal 26 and the voltage measurement probe 56 is provided.

  With the first conductor 64 and the second conductor 66, the arrangement of the voltage generator 10 and the semiconductor device 70 to be tested can be arbitrarily selected. Thus, it is preferable to provide a first conductor that electrically connects the voltage output terminal and the voltage application probe, and a second conductor that electrically connects the measurement voltage input terminal and the voltage measurement probe. In this way, by connecting a conductor between the voltage generator and the probe card, the shape of the conductor can be freely set, so the arrangement of the voltage generator and the semiconductor device under test can be arbitrarily set. There is a further effect of being able to choose.

(Third embodiment)
The third embodiment will be described with reference to FIGS. 4 and 5. FIG. 4 is a diagram schematically showing a circuit configuration of the third embodiment. The configuration of the voltage generator 10 is the same as that described in the first embodiment.

  The semiconductor device 71a to be tested includes two voltage application pads 74a and 74b and a voltage measurement pad 76. The pads are connected by a conductor 79a.

  The probe card 50a includes a first voltage application probe 54b, a second voltage application probe 54a, and a voltage measurement probe 56 so as to be separated from each other. Both the first voltage application probe 54 b and the second voltage application probe 54 a are connected to a voltage output terminal 24 provided in the voltage compensation circuit 14 of the voltage generator 10. In this case, as shown in FIG. 4, one end of the first voltage application probe 54b connected to the input terminal of the probe card 50a and one end of the voltage measurement probe 56 connected to the output terminal of the probe card 50a The distance between the other ends of the first voltage application probe 54b and the voltage measurement probe 56 connected to the target pads 74b and 76 is shorter than the distance of. Further, the first voltage measurement probe 56 and the second voltage application probe 54a are arranged so as to sandwich the first voltage application probe 54b. FIG. 5 shows a state in which deposits 101 and 102 are adhered between the first voltage application probe 54b and the second voltage application probe 54a and the voltage application pads 74a and 74b.

  A current necessary for the operation of the semiconductor device under test flows through the voltage application probe, but this current may exceed the allowable value of the voltage application probe. In the third embodiment, by providing two voltage application probes, the current flowing per probe is reduced, so that the power supply capability to the semiconductor device under test can be increased. Note that three or more voltage application probes may be provided depending on the current required for the operation of the semiconductor device under test and the allowable value of the voltage application probe. That is, it is preferable to provide a plurality of voltage application probes. Each voltage application probe is provided in one probe card and is commonly connected to a voltage output terminal.

(Fourth embodiment)
A fourth embodiment will be described with reference to FIGS. 6 and 7. FIG. 6 is a diagram schematically showing a circuit configuration of the fourth embodiment. The configuration of the voltage generator 10 is the same as that described in the first embodiment.

  The semiconductor device 71b to be tested includes a voltage application pad 74 and two voltage measurement pads 76a and 76b. The pads are connected by a conductor 79b.

  The probe card 50b includes a first voltage application probe 54, a first voltage measurement probe 56a, and a second voltage measurement probe 56b so as to be separated from each other. Both the first voltage measurement probe 56 a and the second voltage measurement probe 56 b are connected to a measurement voltage input terminal 26 provided in the voltage compensation circuit 14 of the voltage generator 10. In this case, as shown in FIG. 6, one end of the first voltage application probe 54 connected to the input terminal of the probe card 50b and the first voltage measurement probe connected to the output terminal of the probe card 50b. The distance between the other end of the first voltage application probe 54 and the first voltage measurement probe 56a connected to the target pads 74 and 76a is shorter than the distance to one end of 56a. ing. Further, the first voltage application probe 54 and the second voltage measurement probe 56b are arranged so as to sandwich the first voltage measurement probe 56a.

  When a contact failure occurs between the voltage measurement probe and the voltage measurement pad, a voltage higher than the set voltage may be applied to the voltage application pad. By providing a plurality of voltage measurement probes, it is possible to reduce the probability of malfunction due to poor contact between the voltage measurement probe and the voltage measurement pad. Note that three or more voltage measurement probes may be provided. In other words, it is preferable to provide a plurality of voltage measuring probes. Each voltage measurement probe is provided in one probe card, and is commonly connected to a measurement voltage input terminal.

(Fifth embodiment)
The fifth embodiment will be described with reference to FIGS. 8 and 9. FIG. 8 is a diagram schematically showing a circuit configuration of the fifth embodiment. The configuration of the voltage generator 10 is the same as that of the first embodiment.

  In the fifth embodiment, one pad 75 is provided in the semiconductor device 72 under test.

  The probe card 50 includes a voltage application probe 54 and a voltage measurement probe 56 so as to be separated from each other. The voltage application probe 54 and the voltage measurement probe 56 are connected to one pad 75. Generally, the size of the pad is about 80 μm × 80 μm, and the thickness of the probe is about 20 to 30 μm in diameter, so that it can be connected to the pad so as to be separated from each other. In this case, as shown in FIG. 8, the distance between one end of the voltage application probe 54 connected to the input terminal of the probe card 50 and one end of the voltage measurement probe 56 connected to the output terminal of the probe card 50. Rather, the distance between the voltage application probe 54 and the voltage measurement probe 56 connected to the voltage application target pad 75 is shorter.

  Even when the semiconductor device 72 under test is provided with only one pad, the operating voltage supply device of the present invention can be used. That is, the voltage application pad and the voltage measurement pad are preferably a common pad. In this way, the voltage application pad and the voltage measurement pad are used as a common pad, thereby providing an additional effect that the number of power supply pads prepared in advance in the semiconductor device to be tested can be reduced.

(Sixth embodiment)
In the description so far, the operation voltage supply device to the semiconductor device in the wafer state has been described, but the same device can be applied in the test after assembly. In the test after assembly, the probe card may be replaced with the interface board, the probe may be replaced with the contact, and the power supply pad provided on the semiconductor device to be tested may be replaced with the power supply pin.

  A sixth embodiment will be described with reference to FIG. FIG. 10 is a diagram schematically showing a circuit configuration of the sixth embodiment.

  The voltage generator 10 is the same as that described in the first embodiment. The interface board 90 includes a voltage application contact 94 and a voltage measurement contact 96.

  A voltage application pin 84 and a voltage measurement pin 86 are prepared in the semiconductor device 80a to be tested after assembly. A conductor 88 is connected between the voltage application pin 84 and the voltage measurement pin 86. The voltage application contact 94 is connected to the voltage application pin 84, and the voltage measurement contact 96 is connected to the voltage measurement pin 86. Even in the test after assembly, it is possible to apply an accurate voltage to the voltage application pin 84 of the semiconductor device under test.

(Seventh embodiment)
The seventh embodiment will be described with reference to FIG. FIG. 11 is a diagram schematically showing a circuit configuration of the seventh embodiment.

  The voltage generator 10 is the same as that described in the first embodiment. The interface board 90 is the same as that described in the sixth embodiment.

  A voltage application pin 84 is prepared in the semiconductor device 80b to be tested after assembly. A voltage application contact 94 and a voltage measurement contact 96 are connected to the voltage application pin 84. This method makes it possible to apply an accurate voltage to the voltage application pin 84 of the semiconductor device under test even when only one pin is provided in the test after assembly.

It is the schematic for demonstrating 1st Embodiment. It is a figure explaining the connection state in the semiconductor device for a test in 1st Embodiment. It is the schematic for demonstrating 2nd Embodiment. It is the schematic for demonstrating 3rd Embodiment. It is a figure explaining the connection state in the semiconductor device for a test in 3rd Embodiment. It is the schematic for demonstrating 4th Embodiment. It is a figure explaining the connection state in the semiconductor device for test in 4th Embodiment. It is the schematic for demonstrating 5th Embodiment. It is a figure explaining the connection state in the semiconductor device for test in 5th Embodiment. It is the schematic for demonstrating 6th Embodiment. It is the schematic for demonstrating 7th Embodiment. It is the figure which showed schematically the circuit structure for demonstrating background art. It is a figure explaining the connection state at the time of the normal in the semiconductor device for a test in background art. It is a figure explaining the connection state at the time of abnormality in the semiconductor device for a test in background art. It is a figure for demonstrating the relationship between the contact frequency of a probe and the terminal of the semiconductor device for a test, and contact resistance. It is a figure for demonstrating the relationship between the frequency | count of a contact and the voltage drop of a probe and the terminal of the semiconductor device to be tested.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Voltage generator 12 Variable voltage power supply 14 Voltage compensation circuit 22 Voltage input terminal 24 Voltage output terminal 26 Measurement voltage input terminal 28, 73, 78, 79a, 79b, 88 Conductor 30 1st operational amplifier 32 Positive input of 1st operational amplifier Terminal 34 Negative input terminal of the first operational amplifier 36 Output terminal of the first operational amplifier 40 Second operational amplifier 42 Positive input terminal of the second operational amplifier 44 Negative input terminal of the second operational amplifier 46 Output terminal of the second operational amplifier 50 , 50a, 50b, 51 Probe card 54, 54a, 54b, 55 Voltage application probe 56, 56a, 56b Voltage measurement probe 64 First conductor 66 Second conductor 70, 71a, 71b, 72, 80a, 80b For test Semiconductor device 74, 74a, 74b, 75 Voltage application pad 76, 76a, 76b Voltage measurement pad 84 Voltage marking Pin 86 voltage measurement pin 90 interface board 94 voltage applying contacts 96 voltage measuring contacts 101 and 102 deposit

Claims (5)

An input terminal to which a voltage is applied;
A first voltage application probe having one end side electrically connected to the input terminal and applying a voltage applied to the input terminal from the other end side to a voltage application target;
A first voltage measuring probe for measuring the voltage to be applied;
Voltage electrically connected to one end of the first voltage measuring probe, measured at the other end of the first voltage measuring probe, and transmitted to one end of the first voltage measuring probe And an output terminal for outputting
The first voltage application probe and the first voltage measurement probe are the first voltage based on the distance between one end of the first voltage application probe and one end of the first voltage measurement probe. A probe card, wherein the distance between the other end of the application probe and the other end of the first voltage measurement probe is reduced. One end side is electrically connected to the input terminal, and a second voltage application probe for applying a voltage applied to the input terminal from the other end side to a voltage application target is provided with the first voltage measurement probe and the first voltage measurement probe. 2. The probe card according to claim 1, wherein the probe card is arranged so as to sandwich the first voltage application probe with a second voltage application probe. One end side is electrically connected to the output terminal, and a second voltage measurement probe that measures the voltage to be applied is a first voltage application probe and a second voltage measurement probe. The probe card according to claim 1, wherein the probe card is arranged so as to sandwich the first voltage measurement probe. When performing a test of a semiconductor device provided with a voltage application pin exposed after assembly using the probe card according to claim 1.
The first voltage application probe and the first voltage measurement probe are brought into contact with the voltage application pin, and a predetermined voltage is applied from the first voltage application probe to the voltage application pin of the semiconductor device. And applying the applied voltage to the first voltage measuring probe,
A method for manufacturing a semiconductor device, comprising: adjusting a voltage applied to the input terminal based on a voltage of the output terminal of the probe card. A semiconductor device provided with a voltage application pin exposed after assembly using the probe card according to claim 1, wherein a voltage measurement pin electrically connected within the semiconductor device is provided. When testing semiconductor devices
The first voltage application probe is brought into contact with the voltage application pin, and the first voltage measurement probe is brought into contact with the voltage measurement pin. Applying a predetermined voltage to the voltage application pin, and transmitting the applied voltage to the first voltage measuring probe,
A method for manufacturing a semiconductor device, comprising: adjusting a voltage applied to the input terminal based on a voltage of the output terminal of the probe card.

Images