JP2008241272A - Semiconductor testing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing device enabling a delay adjusting width of a deskew circuit to flexibly cope with a skew, by programmably adjusting the timing of the clock signal. <P>SOLUTION: This semiconductor testing device 100 performs processing for adjusting the skew between a test signal and an output signal by the deskew circuit 122, and individually adjusts the timing of the clock signal for a driver and a comparator so as to be restrained in this delay adjusting width, by delaying at an interval of a predetermined period or shorter, when the skew comes off the delay adjusting width of the deskew circuit 122, and performs processing for adjusting the skew by the deskew circuit 122, by making synchronous operation with the clock signal for the driver and for the comparator of individually adjusting the timing by the driver 123 and the comparator 124. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus that performs a test such as operation check on a device under test such as a semiconductor device, and more particularly to a configuration for adjusting a skew generated in signal transmission.

  2. Description of the Related Art Conventionally, in a semiconductor test apparatus that performs a test of operation check by outputting a test signal to an object to be tested (hereinafter referred to as a DUT) such as a semiconductor device, each test is performed based on a clock signal of a predetermined period. The test signals are generated by the cards prepared in (1), and the test according to the test signals is performed on the DUTs connected to the respective cards.

  In addition, when a test signal or an output signal output from the DUT is transmitted through the semiconductor test apparatus, wiring for outputting the test signal to the DUT and wiring for inputting the output signal from the DUT A difference in transmission delay time due to a difference in length, that is, skew occurs. This skew causes a timing error of processing performed in the test and hinders an accurate test. Therefore, the skew is adjusted using a deskew circuit.

  In the semiconductor test apparatus described in the following Patent Document 1, a delay time adjustment circuit is inserted in series with the deskew circuit, and the deskew circuit is used to adjust a coarse level propagation delay time that cannot be adjusted by the fine adjustment deskew circuit. The unit time of the variable delay amount is set large.

Prior to deskewing, find the pin with the slowest propagation delay time on the time meter, compare the delay time with the delay time of the other pins, and adjust the delay time of the other pins to the delay time of the slowest pin Coarse adjustment is performed. Then, fine adjustment by deskew is performed (see, for example, Patent Document 1).
Japanese Unexamined Patent Publication No. 2000-206212 (FIG. 1)

  Further, in the conventional semiconductor test apparatus, the skew caused by signal transmission is adjusted as follows. FIG. 4 is an explanatory diagram showing a configuration of a conventional semiconductor test apparatus 200 that performs skew adjustment.

  The semiconductor test apparatus 200 inputs a clock signal generated at a predetermined cycle by a clock generator (not shown) to each of the plurality of cards B220 via the card A210. In each card B 220, the timing generator / format controller 221 (hereinafter referred to as TG / FC 221) generates a test signal for performing a test such as operation check of the DUT based on this clock signal, and the deskew circuit 222. The signal is output to the DUT on the base board 230 and the probe card 240 to which the card B 220 is connected via the driver 223.

  Then, an output signal output from the DUT in response to the application of the test signal is input to the card B220, and the card B220 receives the output signal via the comparator 224 by the deskew circuit 222. The deskew circuit 222 adjusts the skew generated by different transmission delay times of the test signal and the output signal.

  In such a semiconductor test apparatus 200 according to the prior art, wiring via the driver 223 and the like until the test signal is output to the DUT, and physical wiring via the comparator 224 and the like until the output signal is input to the deskew circuit 222. Due to the difference in length and the like, the transmission delay time of the test signal and the output signal is different, causing a skew.

  The characteristics of the deskew circuit 222, that is, the delay adjustment width (deskew span), resolution, and the like that can adjust the skew are defined in advance in the product specifications of the deskew circuit 222 itself. Normally, the skew adjustment is performed within a range that meets the specifications of the deskew circuit 222.

  On the other hand, when the length changes due to a change in the wiring on the card, the phase of the transmission delay time also changes, and as shown by the oval part (arrow B) indicated by the broken line in FIG. The transmission delay time is greatly shifted between the two. If the phase shift at this time deviates from the delay adjustment range that can be adjusted by the deskew circuit 222, the selection value of the shift register 211 is switched stepwise in the card A 210, and the timing for transmitting the clock signal is set at predetermined intervals. adjust. In this way, after performing the process within the delay adjustment range adjustable by the deskew circuit 222, the actual skew is adjusted by the deskew circuit 222.

  However, in the shift register 211, the timing can be adjusted only stepwise in the cycle of the clock signal as shown in FIG. Further, when there is a large difference between the delay adjustment width adjustable by the deskew circuit 222 and the skew, there is a problem that the deskew circuit 222 can no longer perform the skew adjustment.

  Therefore, an object of the present invention is to provide a semiconductor test apparatus that can flexibly adjust the delay adjustment width of the deskew circuit with respect to skew by adjusting the timing of the clock signal in a programmable manner.

  In order to achieve the above-described problems, a semiconductor test apparatus according to the present invention includes a clock generator that generates a clock signal at a predetermined period, and a device under test based on the clock signal generated by the clock generator. A signal generator for generating a test signal for testing the test signal, a test signal generated by the signal generator, and a transmission process of an output signal output from the test target in response to application of the test signal. A deskew circuit for adjusting skew and a clock adjustment unit for adjusting timing of a clock signal generated by the clock generation unit at intervals equal to or less than the predetermined period are provided.

  With such a configuration, the skew between the test signal and the output signal becomes large, and even when the delay adjustment width that can be adjusted by the deskew circuit is deviated, the clock adjustment unit sets the timing of the clock signal at intervals of a predetermined period or less. It is possible to adjust appropriately in a programmable manner and fit within the delay adjustment width of the deskew circuit. Therefore, it is possible to adjust the skew by flexibly corresponding to the delay adjustment width of the deskew circuit with respect to various sizes of skew.

  In addition, another semiconductor test apparatus according to the present invention includes a clock generator that generates a clock signal at a predetermined period, and a test signal for testing an object to be tested based on the clock signal generated by the clock generator. A signal generator for generating a signal, a driver for applying a test signal generated by the signal generator to the object under test, and an output signal output from the object under test in response to the application of the test signal Is inputted to the comparator, the deskew circuit for adjusting the skew generated in the transmission process of the test signal and the output signal based on the clock signal, and the timing of the clock signal generated by the clock generator less than the predetermined period And a clock adjusting unit that adjusts at intervals.

  According to the present invention, even when the skew between the test signal and the output signal becomes large in the transmission process via the driver or the comparator, and the deviation from the delay adjustment range that can be adjusted by the deskew circuit, the clock adjustment unit This timing can be appropriately adjusted in a programmable manner at intervals equal to or less than a predetermined period, and can be kept within the delay adjustment width of the deskew circuit. As a result, the skew can be adjusted by flexibly corresponding to the delay adjustment width of the deskew circuit with respect to various sizes of skew.

  In the above-described semiconductor test apparatus, the clock adjustment unit is configured by a programmable delay line. As a result, even when using components that are available as general-purpose products at the present time, the timing of the clock signal can be appropriately adjusted in a subtle time unit at intervals of 10 ps, and can be kept within the delay adjustment width of the deskew circuit. .

  According to the semiconductor test apparatus of the present invention, it is possible to flexibly adjust the delay adjustment width of the deskew circuit with respect to the skew by adjusting the timing of the clock signal in a programmable manner.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is an explanatory view showing a configuration example of a semiconductor test apparatus 100 which is an embodiment of a semiconductor test apparatus according to the present invention. The semiconductor test apparatus 100 generates a test signal by a card prepared for each type of test based on a clock signal generated at a predetermined cycle, performs a test on the DUT connected to each card, and performs physical processing of wiring. This is a device provided with a deskew circuit that adjusts a skew generated between a test signal and an output signal from the DUT depending on an appropriate length or the like.

  The semiconductor test apparatus 100 includes a card A110 and a plurality of cards B120 mounted in a test head (not shown). Of these, the card A110 receives a plurality of types of clock signals generated at a predetermined cycle by a clock generator (not shown), adjusts the timing of the clock signals, and outputs the clock signals. That is, the card A110 includes a clock adjustment circuit 111, and outputs a clock signal whose timing is adjusted by the clock adjustment circuit 111 to each of the plurality of cards B120.

  The clock adjustment circuit 111 can adjust the delay of the clock signal in a programmable manner in accordance with a program or setting operated using an operator's computer or the like. Specifically, the clock adjustment circuit 111 individually delays the timing of the clock signal generated in a predetermined cycle at an interval of a predetermined cycle or less (for example, 10 ps) according to the skew generated in each card B120. The function to adjust to. As such a clock adjustment circuit 111, for example, a programmable delay line such as MC100EP196 sold by ON Semiconductor can be used.

  Further, the plurality of cards B120 can generate a test signal for testing the DUT based on the clock signal output from the card A110.

  Further, the plurality of cards B120 are connected to the base board 130 and the probe card 140. The card B 120 includes a TG / FC 121 that generates a test signal based on the clock signal output from the card A 110 and a deskew circuit 122 that adjusts a skew generated between the test signal and the output signal output from the DUT. And a driver 123 that applies (outputs) the input test signal to the DUT, and a comparator 124 that inputs the output signal output from the DUT for comparison with an expected value.

  The deskew circuit 122 has physical lengths of coaxial lines used for a transmission path when a test signal is applied to the DUT through the driver 123 and a transmission path when an output signal from the DUT is input through the comparator 124, respectively. Adjust the skew caused by the difference. That is, the transmission delay time of the test signal generated in the transmission process from the card B 120 to the base board 130, the probe card 140, and the DUT through the driver 123, and the output signal from the DUT are transmitted through the probe card 140, the base board 130, and the comparator 124. The skew due to the difference from the transmission delay time generated in the transmission process until input is adjusted. Note that the delay adjustment width (skew span) and resolution that can be adjusted by the deskew circuit 122 are defined in advance according to the product specifications of the deskew circuit 222.

  The driver 123 operates in synchronization with the driver clock signal output from the card A 110 and inputs the test signal generated by the TG / FC 121 via the deskew circuit 122. This test signal is output to the DUT in contact with the base board 130 and the probe card 140.

  The comparator 124 operates in synchronization with the comparator clock signal output from the card A 110, and receives an output signal output from the DUT in response to the application of the test signal from the driver 123. This output signal has a function of comparing the expected value data or the like for determining the test with the output signal and outputting the comparison result to the deskew circuit 122.

  The semiconductor test apparatus 100 includes a base board 130 and a probe card 140 that are connected to each of the plurality of cards B120, receive test signals, contact the DUT, and input / output signals.

  Subsequently, the operation of the semiconductor test apparatus 100 in the present embodiment will be described. First, when testing the DUT, the clock generator generates a clock signal at a predetermined period.

  The card A 110 receives the clock signal from the clock generation unit, distributes it to each of the cards B 120 via the clock adjustment circuit 111, and outputs it. Each card B 120 generates a test signal for performing a test corresponding to each function based on the clock signal by the TG / FC 121, and contacts the base board 130 and the probe card 140 via the deskew circuit 122 and the driver 123. Output to DUT.

  When the DUT performs an operation or process for each DUT in response to the test signal being applied from the driver 123 and an output signal is output, each card B120 receives this output signal from the comparator 124, and the expected value data The comparator 124 outputs the result to the deskew circuit 122.

  Here, the deskew circuit 122 of each card B120 detects the transmission delay time of the test signal transmitted on the wiring path via the driver 123 in the card B120, the coaxial line, the base board 130, and the probe pin in the probe card 140. To do. The deskew circuit 222 detects the transmission delay time of the output signal transmitted on the wiring path through the probe pin in the base board 130 and the probe card 140, the coaxial line, and the comparator 124 in the card B120, and transmits these signals. A process for adjusting the skew of the test signal and the output signal is performed by a process for comparing the delay times.

  At this time, if the skew is within the delay adjustment width (DESKEW SPAN) of the deskew circuit 222, the skew adjustment is performed without any problem. For example, if each wiring is changed in each card B120, the wiring path is physically changed. And the difference in transmission delay time between the test signal and the output signal may increase. As a result, when the skew of the test signal and the output signal deviates from the delay adjustment width, the clocks distributed and output to the driver 123 and the comparator 124 of each card B120 by each clock adjustment circuit 111 in the card A210. A process of individually adjusting the signal timing is performed so that the skew is within the delay adjustment width of the deskew circuit 122.

  In particular, the clock adjustment circuit 111 can adjust the timings of the clock signals for the driver 123 and the comparator 124 in a programmable manner at intervals of, for example, 10 ps that are equal to or less than a predetermined period. As a result, as shown in FIG. 2, the selection value is selected in a programmable manner corresponding to the skews of various sizes in each card B 120, and the delay amount is set so as to fall within the delay adjustment range adjustable by the deskew circuit 122. It can be adjusted linearly. As a result, the delay adjustment range that can be adjusted by the deskew circuit 122 can be made to correspond to skews of various sizes, as indicated by the ellipse portion (arrow A) indicated by the broken line in FIG.

  In this way, each card B 120 generates a test signal by the TG / FC 121 and inputs it to the driver 123 using the clock signal output at the timing adjusted individually by the clock adjustment circuit 111. The driver 123 operates in synchronization with a driver clock signal whose timing is individually adjusted by the clock adjustment circuit 111, and outputs a test signal to the DUT.

  In each card B120, an output signal from the DUT is input to the comparator 124. The comparator 124 operates in synchronization with the comparator clock signal whose timing is individually adjusted by the clock adjustment circuit 111, and outputs the input output signal to the deskew circuit 122. The deskew circuit 122 performs a process of adjusting the skew generated when the test signal and the output signal are delayed in transmission.

  When the skew is adjusted by the deskew circuit 122, each card B120 performs processing such as test determination, test result aggregation, and statistical calculation using the test signal and the output signal.

  As described above, in the semiconductor test apparatus 100 according to the present embodiment, the deskew circuit 122 of each card B120 detects the transmission delay time of the test signal and the transmission delay time of the output signal, and these transmission delay times are different. A process of adjusting the skew generated by the above is performed. In addition, when the transmission delay time largely deviates between the test signal and the output signal and the skew span (phase) deviates from the delay adjustment range that can be adjusted by the deskew circuit 122, the clock adjustment circuit 111 causes each clock signal to be A process of adjusting the timing individually is performed.

  The timing of the clock signal for the driver and the comparator is delayed by an interval of a predetermined period or less (for example, 10 ps) and adjusted so as to be within a delay adjustment width adjustable by the deskew circuit 122, thereby reducing the wiring length. Even in the case of a significant change, the skew of the test signal and the output signal can be adjusted by the deskew circuit 122.

  For this reason, the delay adjustment width of the deskew circuit 122 is made to flexibly correspond to the actual skew as compared with the case where adjustment is performed in stages at large time intervals for each predetermined period using a shift register or the like as in the prior art. be able to.

  Further, even when there is a large difference between the interval of the predetermined period and the delay adjustment width of the deskew circuit 122, the timing of the clock signal for the driver and the comparator is adjusted to, for example, 10 ps corresponding to various sizes of skew. It is possible to appropriately adjust the delay adjustment width of the deskew circuit 122 by linearly adjusting the time interval with a minute interval. As a result, it is possible to adjust the skew by flexibly corresponding to the delay adjustment width of the deskew circuit 122 with respect to various sizes of skew.

  More specifically, when a specification with a delay adjustment width of 10 ns and a resolution of 10 ps is adopted as the specification per deskew circuit 222, if a plurality of deskew circuits 222 are connected in cascade on the card B120, the whole amount is increased. The delay adjustment range (range) can be expanded. Thereby, for example, even when the physical lengths of the shortest wiring and the longest wiring are extremely different, the delay adjustment width of the deskew circuit 222 can be flexibly widened to perform the skew adjustment.

  In the adjustment method in the above case, each deskew circuit 222 is controlled by a 10-bit digital signal. If the deskew circuit 222 has a resolution of 10 ps, it can be considered that the delay adjustment width can be adjusted substantially linearly in practice. For example, assuming that the clock frequency is 280 MHz, the resolution of 3571 ps (clock cycle) can be achieved with the conventional technique, but this can be improved to 10 ps in the present embodiment. It is.

[Other Embodiments]
In the above-described embodiment, when the skew deviates from the delay adjustment range that can be adjusted by the deskew circuit 122, the clock adjustment circuit 111 adjusts the timing of the clock signal for the driver and the comparator at intervals of a predetermined period or less. However, the present invention is not limited to this, and the timing of the clock signal for controlling the operation of other components such as the TG / FC 121 in the card B120 may be adjusted.

  The clock adjustment circuit 111 causes the skew between the test signal and the output signal for all the DUTs to be tested by each card B120 and each card B120 connected to the card A110 in the semiconductor test apparatus 100. The structure which can be adjusted separately may be sufficient.

  If it is said form, about the wiring in card | curd B120, the base board 130, and the probe card 140, it is not necessary to design a physical wiring length according to the longest wiring in them. For this reason, for example, even when the wiring density is increased due to an increase in the number of DUTs, the wiring length can be individually optimized, thereby reducing the cost and reducing the size of the apparatus. it can. Further, the number of DUTs to be tested can be increased with the downsizing of the apparatus, which greatly contributes to improving the performance of the semiconductor test apparatus 100.

It is explanatory drawing which shows the structure of the semiconductor test apparatus of this embodiment. It is explanatory drawing which shows a mode that the timing of the clock signal of the semiconductor test apparatus of this embodiment is adjusted. It is explanatory drawing which shows the skew produced between the test signal and output signal of the semiconductor test apparatus of this embodiment. It is explanatory drawing which shows the structure of the semiconductor test apparatus of a prior art. It is explanatory drawing which shows a mode that the timing of the clock signal of the semiconductor test apparatus of a prior art is adjusted. It is explanatory drawing which shows the skew produced between the test signal and output signal of the semiconductor test apparatus of a prior art.

Explanation of symbols

100, 200 Semiconductor test equipment 110, 210 Card A
111 Clock adjustment circuit 120, 220 Card B
121,221 Timing generator / format controller (TG / FC)
122, 222 Deskew circuit 123, 223 Driver 124, 224 Comparator 130, 230 Base board 140, 240 Probe card 211 Shift register

Claims (3)

A clock generator for generating a clock signal at a predetermined period;
A signal generator for generating a test signal for testing a device under test based on the clock signal generated by the clock generator;
A deskew circuit that adjusts a skew generated in a transmission process of a test signal generated by the signal generator and an output signal output from the test object in response to application of the test signal;
A semiconductor test apparatus, comprising: a clock adjustment unit that adjusts a timing of a clock signal generated by the clock generation unit at intervals equal to or less than the predetermined period. A clock generator for generating a clock signal at a predetermined period;
A signal generator for generating a test signal for testing a device under test based on the clock signal generated by the clock generator;
A driver for applying a test signal generated by the signal generator to the test object;
A comparator that receives an output signal output from the test object in response to application of the test signal;
A deskew circuit for adjusting a skew generated in the transmission process of the test signal and the output signal based on the clock signal;
A semiconductor test apparatus, comprising: a clock adjustment unit that adjusts a timing of a clock signal generated by the clock generation unit at intervals equal to or less than the predetermined period. The semiconductor test apparatus according to claim 2,
The clock adjustment unit
A semiconductor test apparatus comprising a programmable delay line.

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