JP2008236455A - Transimpedance amplifier and control method of transimpedance amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transimpedance amplifier which requires no external reset signal, and a control method of the transimpedance amplifier. <P>SOLUTION: The transimpedance amplifier 10 ie equipped with a first transimpedance amplifier core circuit 11, a second transimpedance amplifier core circuit 12, an intermediate stage buffer circuit 13, and a gain switching judgement circuit 15 which uses a differential output signal output from the intermediate stage buffer circuit 13 as a comparative input voltage and outputs a gain switching signal based on the comparative input voltage, wherein each of the first and second transimpedance amplifier core circuits 11, 12 is equipped with a gain switching circuit for switching a gain on the basis of the gain switching signal 21, the gain switching judgement circuit 15 has a hysteresis comparator 16, and the hysteresis comparator 16 causes the gain switching circuit to switch the gain based on a plurality of threshold voltages. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a transimpedance amplifier and a method for controlling the transimpedance amplifier.

In an optical transmission device such as an optical transmission system, an optical interconnection, or a passive optical network (PON) system capable of high-speed data transmission, an optical receiving circuit that converts an optical signal into an electric signal is a transimpedance amplifier (Trans Impedance Amplifier (TIA) is used. TIA is an optical signal received as input an input current I _in which is obtained by converting the light electricity by the light receiving element, the impedance conversion gain that is proportional to the value of the feedback resistor, and outputs the converted output voltage V _out.

  Taking the PON system as an example, the upstream packet data from each subscriber side device (Optical Network Unit: ONU) to the station side device (Optical Line Terminal: OLT) is transmitted to the OLT with different power due to the difference in each route. To reach. For this reason, a wide dynamic range is required for the TIA used in the OLT optical receiver circuit.

In general TIA, the amplitude of the input current I _in and increases the output voltage V _out is saturated waveform distortion occurs. In the conventional TIA, in order to achieve both high sensitivity and wide dynamic range characteristics, when the input current _Iin becomes large, the feedback resistance value is reduced to lower the impedance conversion gain, thereby distorting even when a large current is input. The output voltage _Vout with a small amount is obtained.

  On the other hand, when the TDMA (Time Division Multiple Access) method for assigning a unique data transmission time to each user is used in the upstream communication of the PON system, while a certain ONU is sending a packet, other traffic is avoided. The ONU cannot send a packet.

  The time between packets is used for optical receiver setup, clock extraction, and the like. In order to increase the transmission efficiency, it is necessary to shorten the time between packets. As described above, it is required to simultaneously realize high-sensitivity reception, a wide dynamic range, and high transmission efficiency by switching the gain of TIA instantaneously.

  Next, the prior art will be described. FIG. 18 is a functional block diagram of a conventional burst TIA 30. As shown in FIG. 18, the TIA 30 includes a first TIA core circuit 31, a second TIA core circuit 32, a buffer amplifier 33, an output amplifier 34, and a signal level detector 35. The first and second TIA core circuits 31 and 32 operate by switching between two feedback resistance values.

  That is, it operates with a high feedback resistance when the input signal level is low, and switches to a low feedback resistance when the input signal level is high, thereby amplifying the signal without distortion over a wide input range. . When switching the gain, the signal level detector 35 detects the input level, and when it is determined that a certain level of signal has been input, the signal level detector 35 switches to the low feedback resistor.

  The operation of the signal level detector 35 in the prior art will be described in detail. FIG. 19 is a block diagram of a conventional signal level detector 35. As shown in FIG. 19, the signal level detector 35 includes a hysteresis comparator 36. The output of the buffer amplifier constituting the TIA 30 is input to the hysteresis comparator 36 of the signal level detector 35.

FIG. 20 is a diagram showing the input / output characteristics of the conventional signal level detector 35. As shown in FIG. 20, the hysteresis comparator 36 two threshold levels, but provided with a V _{th - L} and V _{th - H,} not utilized only one actually of V _{th - H} of said two threshold level in the prior art. The baseline of the hysteresis comparator input is designed to lie between the two threshold levels.

The baseline of the hysteresis comparator input corresponds to the TIA output level when there is no input signal to the TIA 30 or the “0” level of the signal. When the input signal level exceeds V _{th —} H, the output of the hysteresis comparator changes to “H”, outputs a gain switching signal to the first and second TIA core circuits 31 and 32, and switches the feedback resistance low.

  In the hysteresis comparator 36 having such characteristics, once it is switched to “H”, it cannot be returned to “L” as long as the TIA output is input to the hysteresis comparator 36. Is initialized to “L” by giving to the hysteresis comparator 36.

FIG. 21 is a time chart for explaining the gain switching operation of the entire TIA 30 of the related art. As shown in FIG. 21, consider a case where the input signal 1 having a large amplitude is input to the TIA 30 and the TIA 30 is operating with a low feedback resistance. At this time, since the TIA 30 is operating in the low gain mode, the output thereof has a small amplitude, and the buffer amplifier output, that is, the input amplitude to the signal level detector 35 is also small and is equal to or less than V _{th_H} . The hysteresis comparator output is “H”.

  When receiving the first input signal, the TIA 30 receives the reset signal 37 from the outside, the hysteresis comparator output becomes “L”, and the feedback resistance of the TIA 30 becomes “H” after a certain delay τ, respectively. It is initialized. Subsequently, a second input signal having a large amplitude is input to the TIA 30. Since the second input signal has a large amplitude like the first input signal, it is desirable that the TIA 30 operates with a low feedback resistance. Since the TIA 30 is initialized by the external reset signal 37 immediately before the second input signal is input, the TIA 30 operates with a high feedback resistance.

Therefore, the buffer amplifier output amplitude and the input amplitude to the hysteresis comparator 36 are also large. When the threshold V _{th_H} is exceeded, the hysteresis comparator output changes to “H”, the gain switching signal 38 is output, and the constant delay τ is set. Later, the first and second TIA core circuits 31 and 32 are switched to low feedback resistors. With the above mechanism, the TIA 30 switches its gain according to the input signal strength, and realizes amplification of the signal without distortion over a wide range of input signal strength. An example of the prior art as described above is disclosed in Patent Document 1 below.

JP 2006-311033 A

  However, in the conventional transimpedance amplifier 30 described above, a special signal called the external reset signal 37 is required, so that the interconnectivity with the periphery is impaired, the circuit configuration is complicated, and the external reset signal 37 is mainly used. There is a problem that reception characteristics are deteriorated by acting as a noise source for a signal.

  Accordingly, an object of the present invention is to provide a transimpedance amplifier that does not require an external reset signal and a method for controlling the transimpedance amplifier.

A transimpedance amplifier according to a first invention (corresponding to claim 1) for solving the above-mentioned problem is
A first trans impedance amplifier core circuit that amplifies the current input to the input terminal with a desired gain and outputs the amplified voltage signal as a voltage signal;
A second transimpedance amplifier core circuit with an open input terminal;
An intermediate buffer circuit that differentially amplifies and outputs the output signals from the first and second transimpedance umbo core circuits;
Gain switching determination for using the differential output signal output from the intermediate buffer circuit as a comparison input voltage and outputting a gain switching signal for switching the gains of the first and second transimpedance amplifier core circuits based on the comparison input voltage A transimpedance amplifier comprising a circuit,
The first and second transimpedance amplifier core circuits each include a gain switching circuit that switches a gain based on the gain switching signal,
The gain switching determination circuit includes a hysteresis comparator,
The hysteresis comparator causes the gain switching circuit to switch the gains of the first and second transimpedance amplifier core circuits based on a plurality of threshold voltages.

A transimpedance amplifier according to a second invention (corresponding to claim 2) for solving the above problem is
A first transimpedance amplifier core circuit that amplifies the current input to the input terminal with a desired gain and outputs it as a voltage signal;
A second transimpedance amplifier core circuit having the same configuration as the first transimpedance amplifier core circuit and having an input terminal opened;
An intermediate buffer circuit that differentially amplifies and outputs the output signals from the first and second transimpedance amplifier core circuits;
A gain switching determination circuit that outputs a gain switching signal for switching the gains of the first and second transimpedance amplifier core circuits based on the comparison input voltage using the differential output signal output from the intermediate stage buffer circuit as a comparison input voltage In a transimpedance amplifier comprising:
The first and second transimpedance amplifier core circuits each include a gain switching circuit that switches a gain based on the gain switching signal,
The gain switching determination circuit includes a hysteresis comparator,
The hysteresis comparator is
Switching the gains of the first and second transimpedance amplifier core circuits low by outputting the gain switching signal when the comparison input voltage exceeds a higher threshold voltage of the hysteresis comparator;
The gain of the first and second transimpedance amplifier core circuits is switched high by outputting the gain switching signal when the comparison input voltage falls below a lower threshold voltage of the hysteresis comparator. .

A transimpedance amplifier according to a third invention (corresponding to claim 3) for solving the above problem is
A first trans impedance amplifier core circuit that amplifies the current input to the input terminal with a desired gain and outputs the amplified voltage signal as a voltage signal;
A second transimpedance amplifier core circuit with an open input terminal;
An intermediate buffer circuit that differentially amplifies and outputs the output signals from the first and second transimpedance umbo core circuits;
Gain switching determination for using the differential output signal output from the intermediate buffer circuit as a comparison input voltage and outputting a gain switching signal for switching the gains of the first and second transimpedance amplifier core circuits based on the comparison input voltage A transimpedance amplifier comprising a circuit,
The first and second transimpedance amplifier core circuits each include a gain switching circuit that switches a gain based on the gain switching signal,
The gain switching determination circuit includes a first hysteresis comparator and a second hysteresis comparator,
The comparison input voltage is input as an input signal in parallel to the first hysteresis comparator and the second hysteresis comparator, and the output of the second hysteresis comparator is the gain determination of the first hysteresis comparator. Is input to the first hysteresis comparator as a signal for holding
The first hysteresis comparator changes the gains of the first and second transimpedance amplifier core circuits based on a plurality of threshold voltages,
The second hysteresis comparator holds the gain determination of the first hysteresis comparator based on a plurality of threshold voltages.

A transimpedance amplifier according to a fourth invention (corresponding to claim 4) for solving the above problem is the transimpedance amplifier according to the third invention.
The gain switching determination circuit includes a delay circuit;
The output of the second hysteresis comparator is input to the first hysteresis comparator via the delay circuit.

A transimpedance amplifier according to a fifth invention (corresponding to claim 5) for solving the above problem is the transimpedance amplifier according to the third invention or the fourth invention.
The first hysteresis comparator has a high threshold voltage and a low threshold voltage;
The second hysteresis comparator has a high threshold voltage and a low threshold voltage;
The high threshold voltage of the second hysteresis comparator is lower than the high threshold voltage of the first hysteresis comparator.

A transimpedance amplifier according to a sixth invention (corresponding to claim 6) for solving the above-mentioned problem is the transimpedance amplifier according to the second invention.
The gain switching determination circuit includes a first hysteresis comparator and a second hysteresis comparator,
The first hysteresis comparator is:
Switching the gains of the first and second transimpedance amplifier core circuits low by outputting the gain switching signal when the comparison input voltage exceeds the higher threshold voltage of the first hysteresis comparator;
Switching the gains of the first and second transimpedance amplifier core circuits high by outputting the gain switching signal when the comparison input voltage falls below the lower threshold voltage of the first hysteresis comparator;
The higher threshold voltage in the second hysteresis comparator is lower than the higher threshold voltage in the first hysteresis comparator,
When the comparison input voltage exceeds the higher threshold voltage of the second hysteresis comparator, the gain fixing signal is output to prohibit the gain switching operation of the first and second transimpedance amplifier core circuits. Fixed gain,
The lower threshold voltage of the second hysteresis comparator is equal to the lower threshold voltage of the first hysteresis comparator, and the comparison input voltage is lower than the lower threshold voltage of the second hysteresis comparator. In this case, a gain switching permission signal is output to enable the gain switching operation of the first and second transimpedance amplifier core circuits.

A control method of a transimpedance amplifier according to a seventh invention (corresponding to claim 7) for solving the above-described problem is
A first trans impedance amplifier core circuit that amplifies the current input to the input terminal with a desired gain and outputs the amplified voltage signal as a voltage signal;
A second transimpedance amplifier core circuit with an open input terminal;
An intermediate buffer circuit that differentially amplifies and outputs the output signals from the first and second transimpedance umbo core circuits;
Gain switching determination for using the differential output signal output from the intermediate buffer circuit as a comparison input voltage and outputting a gain switching signal for switching the gains of the first and second transimpedance amplifier core circuits based on the comparison input voltage A control method of a transimpedance amplifier comprising a circuit,
The gains of the first and second transimpedance amplifier core circuits are switched based on a plurality of threshold voltages.

A control method of a transimpedance amplifier according to an eighth invention (corresponding to claim 8) for solving the above-described problem is
A first transimpedance amplifier core circuit that amplifies the current input to the input terminal with a desired gain and outputs it as a voltage signal;
A second transimpedance amplifier core circuit having the same configuration as the first transimpedance amplifier core circuit and having an input terminal opened;
An intermediate buffer circuit that differentially amplifies and outputs the output signals from the first and second transimpedance amplifier core circuits;
A gain switching determination circuit that outputs a gain switching signal for switching the gains of the first and second transimpedance amplifier core circuits based on the comparison input voltage using the differential output signal output from the intermediate stage buffer circuit as a comparison input voltage In a control method of a transimpedance amplifier comprising:
Setting a high threshold voltage and a low threshold voltage for the comparison input voltage;
Switching the gains of the first and second transimpedance amplifier core circuits low by outputting the gain switching signal when the comparison input voltage exceeds a higher threshold voltage;
The gains of the first and second transimpedance amplifier core circuits are switched high by outputting the gain switching signal when the comparison input voltage is lower than the lower threshold voltage.

  According to the present invention, no external reset signal is required in the transimpedance. As a result, a special signal called an external reset signal is required, so the interconnectivity with the surroundings is not impaired, the circuit configuration is not complicated, and the external reset signal is a noise source for the main signal. Therefore, it is possible to switch the gain with high sensitivity and high accuracy.

  Embodiments of the transimpedance amplifier according to the present invention will be described with reference to FIGS. 1 is a functional block diagram of a TIA according to the first embodiment, FIG. 2 is a configuration diagram of a signal level detector according to the first embodiment, and FIG. 3 is a diagram illustrating input / output characteristics of the signal level detector according to the first embodiment. FIG. 5 is a diagram showing the operation when transitioning from the high gain mode to the low gain mode in the first embodiment, FIG. 5 is a diagram showing the operation when transitioning from the low gain mode to the high gain mode in the first embodiment, and FIG. FIG. 7 is a time chart illustrating the operation of the TIA in the first embodiment. FIG. 8 is a time chart illustrating the operation of the TIA in the first embodiment. FIG. 9 is a time chart illustrating the operation of the TIA in the first embodiment, FIG. 10 is a time chart illustrating the operation of the TIA in the first embodiment, and FIG. 11 is a configuration of the signal level detector in the second embodiment. FIG. 12 is a diagram showing input / output characteristics of two hysteresis comparators provided in the signal level detector in the second embodiment, FIG. 13 is a diagram showing operations of the two hysteresis comparators in the second embodiment, and FIG. FIG. 15 is a diagram showing the operation of two hysteresis comparators in the second embodiment, FIG. 15 is a diagram showing the dependency of the output characteristics of the TIA on the input optical signal intensity, and FIG. 16 is a time chart for explaining the operation of the TIA in the second embodiment. FIG. 17 is a time chart for explaining the operation of the TIA in the second embodiment.

  As shown in FIG. 1, a transimpedance amplifier (TIA) 10 according to this embodiment includes a first TIA core circuit 11, a buffer amplifier 13, an output amplifier 14, and a signal level detector 15. The current signal input to the TIA 10 is input to the first TIA core circuit 11 and converted into a voltage signal by an impedance conversion gain proportional to the feedback resistance value and output.

  The second TIA core circuit 12 is exactly the same as the first TIA core circuit 11, but outputs a constant DC potential because the input terminal is open and there is no input signal. Each of the first and second TIA core circuits 11 and 12 includes a gain switching circuit, whereby the feedback resistance value can be switched according to the strength of the input signal.

  The input / output of the buffer amplifier 13 has a differential configuration, the voltage signal output from the first TIA core circuit 11 is sent to the non-inverting input terminal of the buffer amplifier 13, and the voltage signal output from the second TIA core circuit 12 is buffered. The signals are respectively input to the inverting input terminals of the amplifier 13 and differentially amplified and then output to the output amplifier 14.

  Similarly to the buffer amplifier 13, the output amplifier 14 has a differential input / output terminal, and the differential output terminal of the buffer amplifier 13 is connected to the differential input terminal of the output amplifier 14. In the output amplifier 14, the input signal from the buffer amplifier 13 is differentially amplified, and the differential output signal is connected to, for example, an amplitude limiting amplifier provided in the subsequent stage.

  Next, the function of the signal level detector 15 will be described with reference to FIGS. The input of the signal level detector 15 has a differential configuration. The differential output from the buffer amplifier 13 is input to the differential input terminal of the signal level detector 15. The signal level detector 15 determines the level of the input signal and outputs the gain switching signal 21 to the first and second TIA core circuits 11 and 12 according to the result.

  Thereby, the feedback resistance values in the first and second TIA core circuits 11 and 12 are switched to appropriate values. The signal level detector 15 includes a hysteresis comparator 16 (see FIG. 2). The hysteresis comparator 16 detects the input signal level and outputs a gain switching signal 21 according to the result.

The input / output characteristics of the hysteresis comparator 16 in the signal level detector 15 are shown in FIG. As shown in FIG. 3, the hysteresis comparator 16 has two threshold voltages _{V th} _ _L1, V th_H1. When the input signal strength is small and the “L” level of the input signal is V _{th_L1} or less, “L” is output, and the feedback resistance values of the first and second TIA core circuits 11 and 12 are set high. When the input signal level is high and the “H” level of the input signal is _{equal to} or higher than V th — _H1 , the hysteresis comparator 16 outputs “H” and sets the feedback resistance low.

4 and 5 show the relationship between the input current when the gain of the TIA 10 is switched and the input voltage to the hysteresis comparator 16, that is, the TIA output voltage. First, the operation when the feedback resistance of the TIA 10 transitions from a high state to a low state will be described with reference to FIG. When the input current value is small, the TIA 10 operates with a high feedback resistance, and the hysteresis comparator output is “L”. When the input current to the TIA 10 increases and the “H” level of the hysteresis comparator input exceeds the threshold voltage V _{th_H1} on the “H” side, the hysteresis comparator output changes to “H”, and the TIA 10 is low-feedback. Switch to resistance.

Next, the operation when the feedback resistance of the TIA 10 transitions from a low state to a high state will be described with reference to FIG. When the input current value is large, the TIA 10 operates with a low feedback resistance, and the hysteresis comparator output is “H”. When the input current to the TIA 10 decreases and the “L” level of the hysteresis comparator input exceeds the threshold voltage V _{th_L1} on the “L” side, the hysteresis comparator output changes to “L”, and the TIA 10 becomes high feedback. Switch to resistance.

  At the time of transition from the high gain mode to the low gain mode, the “H” level when the TIA 10 is operating with the high feedback resistance is detected, and at the time of transition from the low gain mode to the high gain mode, the TIA 10 has the low feedback resistance. In order to detect the “L” level when operating at, the input current value at which gain switching occurs differs between the two transitions.

  The operation when the present invention is applied to an optical receiver will be described in detail with reference to the drawings. The optical receiver mainly includes a photodiode (PD) 20, a TIA 10, an amplitude limiting amplifier, a clock data recovery device, and the like. Here, the functions of the PD 20 and the TIA 10 will be described as shown in FIG. .

The TIA 10 includes a first TIA core circuit 11, a second TIA core circuit 12, a buffer amplifier 13, an output amplifier 14, and a signal level detector 15. Here, it is assumed that a signal to be handled is expressed by binary values of 0 and 1, that is, an “L” level and an “H” level. Generally have to optical signal has an extinction ratio r _e finite, when the "0" of the optical signal is transmitted, rather than a completely non-signal, an intensity that depends on the optical signal intensity extinction ratio . Optical signal input to the optical receiver is photoelectrically converted by the PD 20, is input to the first TIA core circuit as a current signal I _in.

と表される。 When the average power of the input optical signal is P and the conversion efficiency of the PD 20 is η, the average input current I _in to the PD 20 is

It is expressed.

と表されるため、

と表わされる。 "L" of the input light current, the "H" level and I _L, I _H, considering the extinction ratio r _e,

Because it is expressed as

It is expressed as

と表される。 The input current signal is converted into a voltage signal by the first TIA core circuit 11. The output voltage amplitude at this time is expressed by the product of the input current I _in and the feedback resistance value (R _f ) _in the first TIA core circuit 11. The first TIA core circuit output voltage is

It is expressed.

The second TIA core circuit has the same configuration as that of the first TIA core circuit 11, but since the input is open, a constant DC potential V _ref is always output. The first and second TIA core circuits 11 and 12 operate by switching between two feedback resistance values, and these values are R _{f_L} and R _{f_H} , and R _{f_L} <R _{f_H} . The feedback resistance value is switched and controlled by the signal level detector 15 in the subsequent stage according to the signal level. R _{f — L} is determined by the maximum received light intensity P _{max of} the receiver and the maximum linear amplification output V _{sat of the} TIA 10.

の関係があり、消光比Ｒ_eを考慮すると、

である。 When the input light intensity is P _max

There are relations, considering the extinction ratio R _e,

It is.

FIG. 6 shows the relationship between the “L” and “H” levels and the input optical signal intensity when the TIA 10 operates with a high feedback resistance and a low feedback resistance, respectively. First, the operation of the TIA 10 when the optical signal having the intensity P _{L in} the region 1 as shown in FIG. 6 is input to the optical receiver will be described with reference to FIG. In the initial state of the TIA 10, it is assumed that the hysteresis comparator output of the level detection circuit is “H”, the feedback resistance values of the first and second TIA core circuits 11 and 12 are low, and set to R _{f_L} .

As shown in FIG. 7, for the optical signal intensity is weak in the region of the light intensity of the P _L, TIA 10 is a high gain mode of operation, i.e. it is desirable to operate at the feedback resistor value of R _{f_H.} Immediately before the optical signal having the intensity P _L is input, the hysteresis comparator output is “H” in the level detection circuit, and the TIA 10 operates in the low gain operation mode, that is, the feedback resistance value of R _{f — L.} When an optical signal having an intensity P _L is input to the optical receiver, a signal with a very low level is output from the first TIA core circuit 11.

  When the threshold value on the “L” side of the hysteresis comparator 16 (see FIG. 2) is equal to or higher than the “L” level of the signal operating in the low gain operation mode, the TIA 10 is operating in the low gain operation mode. Since the hysteresis comparator output becomes “L”, it is not desirable. Therefore, it is necessary to set the threshold value on the “L” side of the hysteresis comparator 16 to a certain level or less.

Hereinafter, an operation when an optical signal having an intensity P _L is input will be described. The output signal from the first TIA core circuit 11 is input to the buffer amplifier 13 together with the output voltage from the second TIA core circuit 12, and is output after being differentially amplified, to the signal level detector 15 and the output amplifier 14. Entered. The operation of the hysteresis comparator 16 in the signal level detector 15 at this time will be described. Here, if when the light intensity is input signal P _L TIA is operated at a low feedback resistance, indicating the hysteresis comparator input signal "L" and "H" level, respectively V _{C_L1,} and V _{C_H1.}

の関係があるため、ヒステリシス比較器入力信号がＶ_{th_L1}を下回るとヒステリシス比較器１６から「Ｌ」が出力され、それによって第１及び第２のＴＩＡコア回路１１，１２の帰還抵抗値がＲ_{f_H}に設定される。ＴＩＡ１０における利得切替にはある一定の応答時間τ₁が必要となる。このように、信号の「Ｌ」レベルを検出することによって高い帰還抵抗値を設定することが可能となる。つまり、入力光信号が微弱な状態や無信号状態を、外部リセット信号無しに検出し、ＴＩＡ１０を初期化することが可能となる。

_Therefore , when the hysteresis comparator input signal falls below V _{th_L1} , “L” is output from the hysteresis comparator 16, whereby the feedback resistance values of the first and second TIA core circuits 11 and 12 are changed to R _{f — H} Set to A certain response time τ ₁ is required for gain switching in the TIA 10. Thus, a high feedback resistance value can be set by detecting the “L” level of the signal. That is, the TIA 10 can be initialized by detecting a weak state or no signal state of the input optical signal without an external reset signal.

In the above operation, the operation when the optical signal having the intensity P _L in the region 1 is input in the state where the low feedback resistance value is set in the TIA 10 is described. However, the optical signal having the intensity in the region 1 is input. In this case, it always operates with a high feedback resistance value without depending on the feedback resistance value of the immediately preceding TIA 10. For example, even when a P _L optical signal is input in a state where the feedback resistance value of the TIA 10 is high, when the optical signal of the region 1 is input by setting V _{th_H1} to be _equal to or higher than the “H” level of the signal in advance. Can always be operated in a high gain mode of operation.

Next, the operation of the TIA 10 when the optical signal having the intensity of PH in region 3 in FIG. 6 is continuously input to the optical receiver will be described. Assume that the hysteresis comparator output of the signal level detection circuit is “L”, the feedback resistance values of the first and second TIA core circuits 11 and 12 are high, and are set to R _{f — H.} As shown in FIG. 6, in the region 3 of the light intensity of the P _H, because the input light intensity is large, TIA 10 is low gain mode of operation, i.e. it is desirable to operate at the feedback resistor value of R _{f_L.}

The operation of the hysteresis comparator 16 in the signal level detector 15 at this time will be described with reference to FIG. Here, representing the time of provisionally light intensity is operating in TIA10 high feedback resistance signal PH is input, the hysteresis comparator input signal "L" and "H" level V _{C_L2} respectively, and V _{C_H2.}

の関係があるため、ヒステリシス比較器入力信号がＶ_{th_H1}を上回った瞬間にヒステリシス比較器１６から「Ｈ」が出力され、それによって第１及び第２のＴＩＡコア回路１１，１２の帰還抵抗値がＲ_{f_L}に設定される。ＴＩＡ１０における利得切替にはある一定の応答時間τ₁が必要となる。このように、信号の「Ｈ」レベルを検出することによって低い帰還抵抗値をＴＩＡ１０に設定することが可能となり、外部リセット信号無しにＴＩＡ１０を初期化することが可能となる。

_Therefore, at the moment when the hysteresis comparator input signal exceeds V _{th —} H 1, “H” is output from the hysteresis comparator 16, whereby the feedback resistance values of the first and second TIA core circuits 11 and 12 are changed. _{Rf_L} is set. A certain response time τ ₁ is required for gain switching in the TIA 10. Thus, by detecting the “H” level of the signal, a low feedback resistance value can be set in the TIA 10, and the TIA 10 can be initialized without an external reset signal.

The above operation in a state where the high feedback resistance value in TIA10 is set, the intensity in region 3 has been described the operation when the light signal P _H is input, the optical signal intensity of the region 3 is input In this case, it always operates with a low feedback resistance value without depending on the feedback resistance value of the immediately preceding TIA 10.

For example, even if a P _H optical signal is input while the feedback resistance value of the TIA 10 is low, V _{th_L} is set so that the “H” level of the signal is V _{th_H1} or less and the “L” level is V _{th_L1} or more. By setting in advance, it is possible to operate in the low gain operation mode whenever the optical signal of the region 3 is input.

  In this way, by detecting the “H” level of the signal, it is possible to set a low feedback resistance value when a high-intensity optical signal is input. It becomes possible to initialize the TIA 10 by detecting a weak state or no signal state of the input optical signal without an external reset signal.

Next, the operation when an optical signal having the intensity P _M in region 2 in FIG. 6 is input will be described. When an optical signal having an intensity in this region is input, no gain switching occurs. The operation will be described below with reference to the drawings. As shown in FIG. 9, it is assumed that a low feedback resistance value R _{f — L} is set in the first and second TIA core circuits 11 and 12 immediately before an optical signal having an intensity P _M is input. The “L” level of the signal input to the signal level detector 15 via the first and second TIA core circuits 11 and 12 and the buffer amplifier 13 is V _{C_L3} , and the “H” level is V _{C_H3} .

となるようにヒステリシス比較器１６の閾値が設定されているために、利得切替は起こらず、そのまま低利得モードで動作する。 In region 2, always

Since the threshold value of the hysteresis comparator 16 is set so as to satisfy the following, gain switching does not occur and the operation is performed in the low gain mode as it is.

Next, as shown in FIG. 10, it is assumed that a high feedback resistance value R _{f — H} is set in the first and second TIA core circuits 11 and 12 immediately before an optical signal having an intensity P _M is input. The “L” level of the signal input to the signal level detector 15 via the first and second TIA core circuits 11 and 12 and the buffer amplifier 13 is V _{C_L4} , and the “H” level is V _{C_H4} .

となるように、ヒステリシス比較器１６のＶ_{th_H1}が設定されているために、第１及び第２のＴＩＡコア回路１１，１２の帰還抵抗がＲ_{f_H}の時には線形増幅範囲内で歪みなく動作する。 In region 2, always

Since V _{th_H1} of the hysteresis comparator 16 is set so that the feedback resistance of the first and second TIA core circuits 11 and 12 is R _{f_H} , the hysteresis comparator 16 operates without distortion within the linear amplification range.

  As described above, according to the present embodiment, the gain switching of the TIA 10 detects the intensity of the input signal based on a plurality of threshold voltages, so that it is possible to switch the gain with high sensitivity and high accuracy without using an external reset signal. It becomes.

  The operation of the second embodiment of the present invention will be described with reference to the drawings. Also in the second embodiment, the functional block configuration of the TIA 10 is the same as that of the first embodiment and is as shown in FIG. 1, but the configuration and operation of the signal level detector 15 are different.

As shown in FIG. 11, the configuration of the signal level detector 15 in the second embodiment includes two hysteresis comparators, a first hysteresis comparator 17 and a second hysteresis comparator 18, and a delay circuit 19. The delay circuit 19 provides a constant time delay τ ₂ . The first hysteresis comparator 17 detects the input signal amplitude and outputs a gain switching signal 21 according to the result. The second hysteresis comparator 18 disables the gain from switching suddenly while receiving the payload of any packet signal by enabling / disabling the gain switching operation.

The input / output characteristics of the first and second hysteresis comparators 17 and 18 in the signal level detection circuit 15 are shown in FIG. 12, FIG. 13 and FIG. The first hysteresis comparator 17 has two threshold voltages V _{th_L1} and V _{th_H1} . As in the first embodiment, when the input signal is weak and the “L” level of the input signal is V _{th_L1} or less, “L” is output, and the feedback resistances of the first and second TIA core circuits 11 and 12 are set high. . When the input signal level is high and the “H” level of the input signal is _{equal to} or higher than V _{th —} H 2, the first hysteresis comparator 17 outputs “H” and sets the feedback resistance low.

The second hysteresis comparator 18 has two threshold voltages V _{th_L2} and V _{th_H2} . Here, the relationship of V _{th_L1} = V _{th_L2} and V _{th_H1} > V _{th_H2} is established. The second hysteresis comparator 18 detects the input signal, and outputs “H” when the level exceeds V _{th —} H _2. After a certain delay τ ₂ , the _second hysteresis comparator 17 outputs the gain holding signal. To be entered.

  FIG. 15 shows the relationship between the “H” and “L” levels and the input optical signal intensity when the TIA 10 is operated with a high feedback resistance and a low feedback resistance in the second embodiment. The operation will be described in detail with reference to the time chart shown in FIG.

の関係になる。 An optical signal having an intensity P _M as shown in FIG. 15 is input to the TIA 10, and immediately before that, as shown in FIG. 16, the outputs of the first and second hysteresis comparators are “L”, and the first and second hysteresis comparator outputs. 2 TIA core circuits 11 and 12 are operating with a high feedback resistance. When an optical signal of intensity P _M is input to the TIA 10, the signal level V _{C_H} input to the first and second hysteresis comparators 17 and 18 is as shown in FIG.

It becomes a relationship.

As shown in FIG. 15, when the input optical signal intensity is near the gain switching point, the “H” level exceeds V _{th_H1} due to the transient fluctuation of the intensity when receiving the optical signal. There is a possibility that.

  In general, when a packet signal is transmitted / received in a transmission method such as Ethernet (registered trademark) or ATM, a special code called a preamble is added to the head of the packet, which is used for signal start notification and synchronization. After the preamble, a net data portion called payload is transmitted. In the gain switching type TIA 10, when gain switching occurs while receiving a payload and the signal level changes suddenly, there is a possibility that the signal cannot be received without error.

  Therefore, in the present invention, by using the second hysteresis comparator 18 included in the signal level detector 15, the TIA 10 receives the level value of the signal received by the TIA 10 and after a certain period after detecting the level. Prohibit gain switching.

As shown in FIGS. 13 and 16, when the signal level detector input signal exceeds V _{th —} H 2, the second hysteresis comparator output changes to “H”. After the delay of τ ₂ by the delay circuit, the second hysteresis comparator output “H” is given to the first hysteresis comparator 17 as a gain holding signal, and the gain switching operation after τ _{2 has} elapsed is prohibited. After the lapse of τ _{2, even} if the signal level fluctuates transiently and exceeds V th — _H 1, the first hysteresis comparator output does not change, so that gain switching is not performed.

As shown in FIGS. 14 and 16, when the TIA 10 finishes receiving the packet signal and the level falls below V _{th_L1} and V _{th_L2} , the second hysteresis comparator output changes to “L”, and the delay of τ ₂ Later, it is given to the first hysteresis comparator 17 to cancel the gain holding operation. With such a mechanism, the TIA 10 can be initialized without an external reset signal.

As described in the first embodiment, the low feedback resistance value R _{f_L} is set in the first and second TIA core circuits 11 and 12 immediately before the optical signal having the intensity P _M is input. In this case, no gain switching occurs, and the low gain mode is operated as it is.

Then, it is desirable to operate at TIA10 low feedback resistance, area in 15 3, the operation when the packet signal intensity P _H is input, will be described with reference to FIG. 17. It is assumed that both the first and second hysteresis comparator outputs are “L” and the TIA 10 is a high feedback resistor immediately before the packet signal having the strength P _H is input.

の関係があるため、ヒステリシス比較器入力信号がＶ_{th_H2}、Ｖ_{th_H1}を超えると第１及び第２のヒステリシス比較器１７，１８から「Ｈ」が出力され、それによって第１及び第２のＴＩＡコア回路１１，１２の帰還抵抗値がＲ_{f_L}に設定される。ＴＩＡ１０における利得切替にはある一定の応答時間τ₁が必要となる。 The operation of the first and second hysteresis comparators 17 and 18 in the signal level detector 15 at this time will be described. Here, if when the light intensity is operated in the signal is input TIA10 high feedback resistor P _H, represents the hysteresis comparator input signal "L" and "H" level, respectively V _{C_L3,} and V _{C_H3.}

_Therefore , when the hysteresis comparator input signal exceeds V _{th —} H 2 and V _{th —} H 1, “H” is output from the first and second hysteresis comparators 17, 18, thereby the first and second TIA cores. The feedback resistance values of the circuits 11 and 12 are set to R _{f_L} . A certain response time τ ₁ is required for gain switching in the TIA 10.

Thus, by detecting the “H” level of the signal, a low feedback resistance value can be set in the TIA 10, and the TIA 10 can be initialized without an external reset signal. Also, after lapse of τ ₂ when the first and second hysteresis comparator input signals exceed V th — _{H 2} , the gain hold signal is applied to the first hysteresis comparator 17 and subsequent gain switching is prohibited.

In the above operation, the operation when the optical signal having the intensity P _H in the region 3 is input in a state where a high feedback resistance value is set in the TIA 10 has been described. As described in the first embodiment, the region When an optical signal having an intensity of 3 is input, it always operates with a low feedback resistance value without depending on the feedback resistance value of the immediately preceding TIA 10.

Thus, in a region where the input signal strength to the TIA 10 is large, the TIA 10 operates with a low feedback resistance. Further, by setting the time τ _{2 to} a time corresponding to the preamble length of the packet signal, gain switching can be permitted only during the preamble and gain switching can be prohibited during payload reception.

Next, an operation when an optical signal having an intensity P _L as shown in FIG. 15 is input to the TIA 10 will be described. In this region, since the “H” level of the first and second hysteresis comparators 17 and 18 is not exceeded, it does not depend on the initial states of the first and second TIA core circuits 11 and 12 and is the same as in the first embodiment. The TIA 10 always operates with a high feedback resistance.

  The present invention can be applied to, for example, an optical reception technique for performing digital signal transmission in an optical communication system. Specifically, after converting an optical signal into an electric signal (current signal) by a light receiving element, the current signal is converted into an electric signal. It can be applied to a technique for converting to a voltage signal and shaping and amplifying the waveform. In particular, it can be applied to a high-sensitivity and wide dynamic range reception technology that can respond to burst data signals at high speed and receive signals from minute signals to large signals.

Functional block diagram of TIA in Embodiment 1 Configuration diagram of signal level detector in embodiment 1 The figure which showed the input-output characteristic of the signal level detector in Example 1. The figure which showed the operation | movement at the time of making a transition from high gain mode to low gain mode in Example 1. The figure which showed the operation | movement at the time of making a transition from low gain mode to high gain mode in Example 1. The figure which showed the input optical signal intensity dependence of the output characteristic of TIA Time chart illustrating operation of TIA in embodiment 1 Time chart illustrating operation of TIA in embodiment 1 Time chart illustrating operation of TIA in embodiment 1 Time chart illustrating operation of TIA in embodiment 1 Configuration diagram of signal level detector in embodiment 2 The figure which showed the input-output characteristic of two hysteresis comparators with which a signal level detector is provided in Example 2. The figure which showed operation | movement of the two hysteresis comparators in Example 2. The figure which showed operation | movement of the two hysteresis comparators in Example 2. The figure which showed the input optical signal intensity dependence of the output characteristic of TIA Time chart illustrating the operation of TIA in the second embodiment Time chart illustrating the operation of TIA in the second embodiment Functional block diagram of conventional burst TIA Configuration diagram of conventional signal level detector Diagram showing input / output characteristics of a conventional signal level detector Time chart illustrating conventional gain switching operation of entire TIA

Explanation of symbols

10 TIA (Transimpedance Amplifier)
DESCRIPTION OF SYMBOLS 11 1st TIA core circuit 12 2nd TIA core circuit 13 Buffer amplifier 14 Output amplifier 15 Signal level detector 16 Hysteresis comparator 17 1st hysteresis comparator 18 2nd hysteresis comparator 19 Delay circuit 20 PD (Photo) diode)
21 Gain switching signal

Claims (8)

A first trans impedance amplifier core circuit that amplifies the current input to the input terminal with a desired gain and outputs the amplified voltage signal as a voltage signal;
A second transimpedance amplifier core circuit with an open input terminal;
An intermediate buffer circuit that differentially amplifies and outputs the output signals from the first and second transimpedance umbo core circuits;
Gain switching determination for using the differential output signal output from the intermediate buffer circuit as a comparison input voltage and outputting a gain switching signal for switching the gains of the first and second transimpedance amplifier core circuits based on the comparison input voltage A transimpedance amplifier comprising a circuit,
The first and second transimpedance amplifier core circuits each include a gain switching circuit that switches a gain based on the gain switching signal,
The gain switching determination circuit includes a hysteresis comparator,
The hysteresis comparator causes the gain switching circuit to switch the gains of the first and second transimpedance amplifier core circuits based on a plurality of threshold voltages. A first transimpedance amplifier core circuit that amplifies the current input to the input terminal with a desired gain and outputs it as a voltage signal;
A second transimpedance amplifier core circuit having the same configuration as the first transimpedance amplifier core circuit and having an input terminal opened;
An intermediate buffer circuit that differentially amplifies and outputs the output signals from the first and second transimpedance amplifier core circuits;
A gain switching determination circuit that outputs a gain switching signal for switching the gains of the first and second transimpedance amplifier core circuits based on the comparison input voltage using the differential output signal output from the intermediate stage buffer circuit as a comparison input voltage In a transimpedance amplifier comprising:
The first and second transimpedance amplifier core circuits each include a gain switching circuit that switches a gain based on the gain switching signal,
The gain switching determination circuit includes a hysteresis comparator,
The hysteresis comparator is
Switching the gains of the first and second transimpedance amplifier core circuits low by outputting the gain switching signal when the comparison input voltage exceeds a higher threshold voltage of the hysteresis comparator;
The gain of the first and second transimpedance amplifier core circuits is switched high by outputting the gain switching signal when the comparison input voltage falls below a lower threshold voltage of the hysteresis comparator. Transimpedance amplifier. A first trans impedance amplifier core circuit that amplifies the current input to the input terminal with a desired gain and outputs the amplified voltage signal as a voltage signal;
A second transimpedance amplifier core circuit with an open input terminal;
An intermediate buffer circuit that differentially amplifies and outputs the output signals from the first and second transimpedance umbo core circuits;
Gain switching determination for using the differential output signal output from the intermediate buffer circuit as a comparison input voltage and outputting a gain switching signal for switching the gains of the first and second transimpedance amplifier core circuits based on the comparison input voltage A transimpedance amplifier comprising a circuit,
The first and second transimpedance amplifier core circuits each include a gain switching circuit that switches a gain based on the gain switching signal,
The gain switching determination circuit includes a first hysteresis comparator and a second hysteresis comparator,
The comparison input voltage is input as an input signal in parallel to the first hysteresis comparator and the second hysteresis comparator, and the output of the second hysteresis comparator is the gain determination of the first hysteresis comparator. Is input to the first hysteresis comparator as a signal for holding
The first hysteresis comparator changes the gains of the first and second transimpedance amplifier core circuits based on a plurality of threshold voltages,
The transimpedance amplifier, wherein the second hysteresis comparator holds a gain determination of the first hysteresis comparator based on a plurality of threshold voltages. The transimpedance amplifier according to claim 3,
The gain switching determination circuit includes a delay circuit;
The transimpedance amplifier, wherein the output of the second hysteresis comparator is input to the first hysteresis comparator via the delay circuit. In the transimpedance amplifier according to claim 3 or 4,
The first hysteresis comparator has a high threshold voltage and a low threshold voltage;
The second hysteresis comparator has a high threshold voltage and a low threshold voltage;
A transimpedance amplifier, wherein a high threshold voltage of the second hysteresis comparator is lower than a high threshold voltage of the first hysteresis comparator. The transimpedance amplifier according to claim 2,
The gain switching determination circuit includes a first hysteresis comparator and a second hysteresis comparator,
The first hysteresis comparator is:
Switching the gains of the first and second transimpedance amplifier core circuits low by outputting the gain switching signal when the comparison input voltage exceeds the higher threshold voltage of the first hysteresis comparator;
Switching the gains of the first and second transimpedance amplifier core circuits high by outputting the gain switching signal when the comparison input voltage falls below the lower threshold voltage of the first hysteresis comparator;
The higher threshold voltage in the second hysteresis comparator is lower than the higher threshold voltage in the first hysteresis comparator,
When the comparison input voltage exceeds the higher threshold voltage of the second hysteresis comparator, the gain fixed signal is output to prohibit the gain switching operation of the first and second transimpedance amplifier core circuits. Fixed gain,
The lower threshold voltage of the second hysteresis comparator is equal to the lower threshold voltage of the first hysteresis comparator, and the comparison input voltage is lower than the lower threshold voltage of the second hysteresis comparator. A transimpedance amplifier that outputs a gain switching permission signal to enable the gain switching operation of the first and second transimpedance amplifier core circuits. A first trans impedance amplifier core circuit that amplifies the current input to the input terminal with a desired gain and outputs the amplified voltage signal as a voltage signal;
A second transimpedance amplifier core circuit with an open input terminal;
An intermediate buffer circuit that differentially amplifies and outputs the output signals from the first and second transimpedance umbo core circuits;
Gain switching determination for using the differential output signal output from the intermediate buffer circuit as a comparison input voltage and outputting a gain switching signal for switching the gains of the first and second transimpedance amplifier core circuits based on the comparison input voltage A control method of a transimpedance amplifier comprising a circuit,
A transimpedance amplifier control method, wherein the gains of the first and second transimpedance amplifier core circuits are switched based on a plurality of threshold voltages. A first transimpedance amplifier core circuit that amplifies the current input to the input terminal with a desired gain and outputs it as a voltage signal;
A second transimpedance amplifier core circuit having the same configuration as the first transimpedance amplifier core circuit and having an input terminal opened;
An intermediate buffer circuit that differentially amplifies and outputs the output signals from the first and second transimpedance amplifier core circuits;
A gain switching determination circuit that outputs a gain switching signal for switching the gains of the first and second transimpedance amplifier core circuits based on the comparison input voltage using the differential output signal output from the intermediate stage buffer circuit as a comparison input voltage In a control method of a transimpedance amplifier comprising:
Setting a high threshold voltage and a low threshold voltage for the comparison input voltage;
Switching the gains of the first and second transimpedance amplifier core circuits low by outputting the gain switching signal when the comparison input voltage exceeds a higher threshold voltage;
Controlling the transimpedance amplifier, wherein the gain of the first and second transimpedance amplifier core circuits is switched high by outputting the gain switching signal when the comparison input voltage is lower than the lower threshold voltage. Method.

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