JP2008206745A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain a circuit configuration suited to a performance required for displaying respective images and to easily synchronize the display timings of the images to be displayed at respective image display devices in a game machine provided with the plurality of image display devices wherein the number of pixels is respectively different. <P>SOLUTION: When image data to be displayed are transferred from a sub CPU 61 through a chip set 67 and a PCI-Express bus 74 to a main display 2 and a sub display 7, an image display control circuit 661 generates gradation data based on the respective image data and respectively writes them in VRAMs 662a and 662b. Then, the gradation data are respectively outputted from the VRAMs 662a and 662b to drive circuits 663a and 663b, and the supply timings of image signals from the drive circuits 663a and 663b to the respective displays are controlled so as to synchronize the display timings of the images based on the gradation data. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention provides a game that gives a player a privilege according to a display mode of a symbol displayed when variable display of the symbol is stopped, and performs an effect for improving the interest of the game. The present invention relates to a gaming machine provided with an image display device.

  A slot machine installed in a game hall such as a so-called pachinko shop allows the start switch to be operated when a player inserts a desired number of medals (however, a maximum of three), and the switch is tilted. The three reels rotate and the game starts. On the peripheral surface of each reel, a plurality of types of symbols (generally 21) are drawn at equal intervals, and these symbols are in a certain direction (usually from top to bottom) as the reel rotates. Will be scrolled. Then, when the player operates a stop switch provided corresponding to each reel after all the reels start rotating, the rotation of the reel corresponding to the operated stop switch stops. When all reels are stopped, if a symbol combination corresponding to any combination is displayed along the winning line considered to be effective (hereinafter referred to as the effective line), the combination is established and the winning combination is won. A privilege according to the type of established role is given to the player. That is, in the slot machine, the number of game medals according to the type of winning combination is paid out. On the other hand, when the symbol combination stopped and displayed along the active line does not correspond to any combination, it is lost. Further, when all reels are stopped (when the payout of medals is completed when winning), it becomes possible to insert medals for the next game.

  In the slot machine described above, usually, when a start switch is operated, a lottery for each predetermined role based on a random number (this lottery is called an internal lottery) is performed. As a result of this internal lottery, if a winning combination is won, the slot machine will match the symbol combination corresponding to the winning combination in the internal lottery along the active line when the player operates the stop switch described above. The reel stop control is performed so that the stop display is displayed. On the other hand, if you do not win any combination in the internal lottery (if you lose), no matter what timing the player operates the stop switch, the symbol combination corresponding to any combination will be on the active line. The stop control of the reel is performed so that the stop is not displayed along the line.

  Here, the reel stop control performed when a winning combination is won by an internal lottery, the symbols constituting the symbol combination corresponding to the winning combination (hereinafter referred to as a winning symbol) from the position of the effective line, If the player operates the stop switch when positioned within the range up to 4 symbols upstream (hereinafter, this range is referred to as the reel control range), the winning symbol is stopped at the position of the effective line. In addition, reel stop control is performed. In other words, if the winning symbol is not located within the reel control range and the player operates the stop switch, even if the player wins any role in the internal lottery, the symbol combination corresponding to that role Cannot be stopped along the active line. In this way, the fact that the player was not able to establish a role in spite of winning a certain role in the internal lottery is called “missing”.

  In order to minimize the occurrence of this “missing”, some slot machines described above notify the player of the result of the internal lottery before all three reels stop. In other words, in the slot machine that performs such notification, the player knows the result of the internal lottery, so that when the winning symbol corresponding to the winning combination is located within the reel control range, the stop switch Will be able to operate. A player's interest in this type of notification is generally high because it is directly related to the player's own profit (ie, the number of game medals that can be acquired), and therefore, the game's interest is further improved by devising the notification mode. Production to improve is possible.

  In recent years, an image display device is provided in a slot machine and an image is used to produce a more elaborate effect, and this type of slot machine is disclosed in, for example, Patent Document 1. As shown in the figure, on the front face of the slot machine housing, a liquid crystal display for production is provided in the center, and three reels smaller than the liquid crystal display are provided above the display to display the symbols displayed by the reels. An image in which an effect image (hereinafter referred to as an effect image) displayed on a liquid crystal display is more conspicuous than an aspect has been proposed. Further, in the slot machine disclosed in Patent Document 2, a liquid crystal display device (reel portion liquid crystal display device) is provided almost at the center of the front surface of the housing, and the reel portion liquid crystal display device produces an effect using an image. A reel display window is formed in the screen so that the design of the reel provided on the back side of the reel unit liquid crystal display device can be seen. Also, an upper liquid crystal display device and a lower liquid crystal display device are provided on the upper and lower sides of the reel portion liquid crystal display device, respectively, and the upper liquid crystal display device displays a payout table according to the gaming state performed in the slot machine. At the same time, the lower liquid crystal display device is configured so as to display symbols in accordance with the concept of the slot machine.

JP 2006-34625 A JP 2004-242879 A

  By the way, in a gaming machine such as a slot machine, as one method of performing an effect that gives an impact to a player using an image, the display area of the image display device is enlarged to display a clearer and more powerful image. It is possible. However, for example, in the case of a slot machine, in addition to displaying images on the front surface of the housing, operation sections such as a game medal slot, BET switch, start switch, stop switch, and other effects such as speakers and lamps Since it is necessary to install devices, there is a limit to increase the screen size of one image display device due to the relationship with the installation positions of these devices. Therefore, like the slot machine disclosed in Patent Document 2 described above, a plurality of image display devices are provided on the front surface of the housing, and an effect image to be displayed to the player is divided and displayed on each image display device. Or, it may be possible to provide a more graceful effect by, for example, providing a relationship between effect images that are individually displayed on each image display device.

  In this case, as disclosed in Patent Document 2, an image control circuit corresponding to each image display device is required, but these image control circuits are common in design, procurement of parts, and inventory. In view of the above, it is desirable to use a common one. Therefore, main components such as an image processing chip and a VRAM (Video RAM) constituting the image control circuit are matched with those used for the image control circuit that requires the highest performance. For this reason, for example, image control corresponding to an image display device that displays an image with a small number of pixels (that is, the resolution of an image that can be displayed is low) and an image with a small number of display colors that does not cause a problem in production. In the circuit, there is an overspec, and it may occur that the cost performance is not appropriate. Further, when it is desired to synchronize the display timing of images displayed on a plurality of image display devices, if an image control circuit for each image display device is individually provided, image display control between the image control circuits is performed. The complication of having to synchronize timing arises.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a circuit configuration suitable for the performance required to display each image when displaying images with different resolutions that can be displayed on a plurality of image display devices. Another object of the present invention is to provide a gaming machine that can easily synchronize the display timing of images displayed on each image display device.

  In order to achieve the above-mentioned object, the present invention has variable display means for variably displaying a plurality of symbols composed of a plurality of types of symbols, and the symbol is displayed when the variable display is stopped. A gaming machine that grants a privilege to a player in response, provided with a plurality of image display devices having different pixel numbers and the plurality of image display devices, each corresponding to the number of pixels of the corresponding image display device A plurality of image storage means for storing image display data for each pixel of the corresponding image display device, and corresponding to the plurality of image display devices and image storage means. In addition, according to the timing signal supplied from the outside, each generates an image signal for displaying an image based on the image display data supplied from the corresponding image storage means, and the generated image The image display data is generated based on a plurality of image signal supply means for supplying a signal to a corresponding image display device and image data to be displayed on the plurality of image display devices supplied from the outside through a data transmission path. The generated image display data is stored in the image storage unit corresponding to the image display device on which the image data is to be displayed, and the display of each image displayed on the plurality of image display devices is synchronized. And an image display control unit that generates the timing signal and supplies the timing signal to each of the plurality of image signal supply units.

  According to the present invention, each of the image storage means has a storage capacity corresponding to the number of pixels of the corresponding image display device, and the image signal supply means is configured to output an image according to the timing signal supplied from the image display control means. The image display data stored in the storage means is converted into an image signal. The timing signal is generated in the image display control means so that the display of each image displayed on the plurality of image display devices is synchronized. For this reason, the image storage means corresponding to the image display device with a small number of pixels requires less storage capacity than the image storage means corresponding to the image display device with a large number of pixels, and the image signal supply means has one screen. When an image is displayed, the processing load for converting from image display data per unit time (for example, one frame time) to an image signal is lighter than that of an image signal supply unit corresponding to an image display device having a large number of pixels. Become. That is, the image storage means and the image signal supply means can be selected according to the performance required to display each image according to the corresponding image display device. Further, since the timing signal is supplied from the image display control unit to each image signal supply unit, the timing signal can be shared or easily generated, and the display timing of the image displayed on each image display device can be synchronized. Has the effect of making it easier to remove.

  In the gaming machine according to the present invention, the data transmission path includes a plurality of transmission paths for serially transferring data, and is a data transmission path for serially transferring the image data through the plurality of transmission paths. It is said.

  According to the present invention, image data to be displayed on a plurality of image display devices is supplied to the image display control means via a data transmission path composed of a plurality of serial buses. For example, image data using a parallel bus is used. Compared with the case of supplying the data, the data transfer speed can be remarkably increased. Therefore, when the amount of image data per screen is large, or when a high processing load is applied to the image display control means, such as when displaying a 3D image, for example, within a unit time (for example, one frame time) Thus, it is possible to earn more time for these image processing.

  According to the gaming machine of the present invention, when displaying images with different displayable resolutions for a plurality of image display devices, the circuit configuration matches the performance required to display each image. In addition, it is possible to easily synchronize display timings of images displayed on the image display devices.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings, taking a slot machine as an example of a gaming machine. FIG. 1 is a front view of the slot machine 1 according to the present embodiment. A liquid crystal image display device (hereinafter referred to as a main display) using a TFT (Thin Film Transistor) having a resolution of 480 pixels (liquid crystal pixels) in the horizontal direction and 160 pixels in the vertical direction on the front surface and the top of the slot machine 1 2 is provided. The main display 2 is a normally white liquid crystal image display device. In the center of the screen, three reels 3L, 3L provided inside the casing of the slot machine 1 and on the back side of the main display 2 are provided. A reel display window 4 that can face the symbols drawn on 3C and 3R, respectively, is formed. Further, in the screen area other than the reel display window 4, an image for improving a game's expectation and interest and various information useful for the player when playing the game are displayed. Note that the structure of the main display 2 having the reel display window 4 formed on the screen is the same as that of the conventional display, and thus detailed description thereof is omitted.

  The reels 3L, 3C, 3R are rotatably provided in a horizontal row, and a plurality of symbols composed of a plurality of types of symbols are drawn at equal intervals on the outer peripheral surface of each reel. Further, the reel display window 4 is formed so that only one symbol among the symbols drawn on the reels 3L, 3C, 3R can be visually recognized by the player. In the slot machine 1, the combination of three symbols displayed on the reel display window 4 when the reels 3L, 3C, 3R rotate and then all the reels are stopped is a predetermined symbol combination. When it matches, the combination corresponding to the symbol combination is established. During the rotation of the reels 3L, 3C, 3R, in the reel display window 4, a plurality of symbols drawn on each reel are scroll-displayed from top to bottom in the figure. Thus, the reels 3L, 3C, 3R correspond to variable display means for variably displaying a plurality of symbols.

  Speakers 5L and 5R are provided on the lower side of the main display 2, and sound effects generated according to the operations performed by the player to play the game in the slot machine 1, the player's expectation and satisfaction Production sound for enhancing the performance, background music generated according to the game situation, etc. are output. A central panel 6 is disposed below the speakers 5L and 5R, and a liquid crystal image using a TFT having a resolution of 480 pixels in the horizontal direction and 480 pixels in the vertical direction at the approximate center of the central panel 6. A display device (hereinafter referred to as a sub display) 7 is provided. On the left side of the sub-display 7, in order from the top in the figure, a bonus count display unit 8, BET lamps 9a to 9c, a payout number display unit 10, a stored number display unit 11, and a game state display lamp group 12 are displayed. Is arranged. The bonus count display unit 8 comprises a three-digit seven-segment display, and is paid from the slot machine 1 during a bonus game (a special game that starts when a bonus combination is established and increases the probability that a game medal can be obtained). Displays the number of medals that have been awarded. The BET lamps 9a, 9b, and 9c indicate the number of medals inserted in one game depending on the number of lights, and when one medal is inserted, only the BET lamp 9a is lit and two are inserted. When the BET lamps 9a and 9b are turned on, all the BET lamps 9a, 9b and 9c are turned on when three sheets are inserted. The payout number display unit 10 is composed of a two-digit 7-segment display, and displays the number of medals to be paid out when winning as a result of the game. The stored number display unit 11 is composed of a three-digit 7-segment display and indicates the number of medals stored in the slot machine 1.

  The gaming state display lamp group 12 is composed of five LEDs, and in the order from the left, an insert lamp IN, a start lamp ST, a game standby display lamp WA, a re-game display lamp RE, and a winning display lamp WN are arranged. ing. Further, the current gaming state is notified to the player by the lighting state of each LED. Here, the insert lamp IN blinks to indicate that a medal can be inserted. The start lamp ST is turned on to indicate that the game can be started (start switch operation described later) is ready. Since the game standby display lamp WA is lit, since 4.1 seconds have not elapsed since the start of the previous game, the start of rotation of the reels 3L, 3C, 3R waits even if the start switch is operated. It shows that it is in a state. In this case, when 4.1 seconds elapse from the start of the previous game, the game standby display lamp WA is turned off and the reels 3L, 3C, 3R start to rotate. The re-game display lamp RE is turned on to indicate that the next game to be started is a re-game. The winning display lamp WN is turned on to indicate that a bonus combination is won by an internal lottery described later.

  A pedestal portion 13 formed so as to protrude from the surface of the slot machine 1 is provided below the central panel 6, and when playing a game with the slot machine 1, the upper surface of the pedestal portion 13 is on the right side. A medal slot 14 for inserting game medals is provided. In the slot machine 1, one game can be played when three game medals are inserted. However, when game medals are continuously inserted, a maximum of 50 game medals are inserted after the fourth game medal. Until it is stored in the slot machine 1. A BET switch 15 is provided on the left side of the upper surface of the pedestal portion 13, and when the player operates the BET switch 15 in a state where three or more game medals are stored in the slot machine 1, the stored game is stored. Of the medals, three game medals can be inserted into the slot machine 1 at a time.

  Stop switches 16L, 16C, and 16R respectively corresponding to the reels 3L, 3C, and 3R are disposed on the vertical surface of the pedestal portion 13 and substantially in the center of the front surface of the slot machine 1. These stop switches 16L, 16C, and 16R are switches for stopping the rotating reels 3L, 3C, and 3R. For example, when the player presses the stop switch 16L, the main controller described later Stop control of the left reel 3L is performed. Similarly, when the stop switch 16C is pressed, the stop control of the middle reel 3C is performed, and when the stop switch 16R is pressed, the stop control of the right reel 3R is performed. On the left side of these stop switches 16L, 16C, 16R, a start switch 17 is provided for rotating the reels 3L, 3C, 3R all at once by a tilting operation by the player. A medal discharge switch 18 for discharging game medals stored in the slot machine 1 is provided on the right side of the stop switches 16L, 16C, 16R.

  Below the pedestal portion 13 is disposed a waist panel 19 on which a model name given to the slot machine 1 and a pattern such as a character in accordance with the concept of the slot machine 1 are drawn. Further, on the lower side of the lumbar panel 19, as a result of playing the game in the slot machine 1, when winning, and when the medal discharge switch 18 is pushed in the state where the medal is stored in the slot machine 1, A medal discharge port 20 for discharging game medals from the inside of the casing of the slot machine 1 and a medal tray 21 for storing game medals discharged from the medal discharge port 20 are provided.

  Next, with reference to FIG. 2 and FIG. 3, the structure of the control part which performs control regarding the game and effect in the slot machine 1 is demonstrated. The control unit of the slot machine 1 is composed of a main control unit 30 and a sub-control unit 60. The main control unit 30 is mainly used to insert medals, rotate / stop reels, payouts at the time of winning, etc. Control related to the game performed in the machine 1 is performed. In addition, the sub-control unit 60 mainly performs control related to effects by sounds and images executed in association with games. Here, FIG. 2 is a block diagram showing a configuration of the main control unit 30 and each device controlled by the main control unit 30, and FIG. 3 is a block diagram showing a configuration of the sub-control unit 60. 2 and 3, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The main control unit 30 includes a microcomputer (hereinafter referred to as a microcomputer) 31 disposed on a circuit board as a main component, and is added with a circuit for random number sampling. The microcomputer 31 includes a main CPU 32 that performs a control operation in accordance with a preset program, a program ROM 33 that stores a program for executing a game performed in the slot machine 1 and various data, and the main CPU 32 processes the program. A control RAM 34 that temporarily stores data generated in the process and an I / O port 39 for exchanging signals with various input / output devices described later are included.

  The program ROM 33 of the microcomputer 31 stores various tables such as a symbol table, a probability lottery table, a stop table group, and a symbol combination table in addition to a program for performing game control in the slot machine 1. The symbol table associates each step of the stepping motors 53L, 53C, 53R respectively corresponding to the reels 3L, 3C, 3R with each symbol drawn on the reels 3L, 3C, 3R and the type of the symbol. It is. The main control unit 30 performs recognition of the symbols stopped and displayed on the reel display window 4 based on the symbol table and stop control of each reel. The probability lottery table defines the correspondence between each numerical value and each combination in a numerical value range 0-16383 (integer) of random numbers generated by a random number generator 37 described later, and is sampled by a sampling circuit 38 described later. This is referred to when performing internal lottery based on random values.

  The stop table group is composed of a result of the internal lottery and a plurality of stop tables determined corresponding to each of the reels 3L, 3C, 3R. Each stop table has a number of sliding frames for each symbol on the reel. The contents correspond to each other. Here, the number of sliding symbols indicates the number of symbols to be moved further from the position when a stop switch is operated while a certain symbol on the reel is displayed in the reel display window 4. For example, when the number of sliding symbols “1” is associated with a certain symbol, when the stop switch is operated while the certain symbol is displayed in the reel display window 4, the next symbol following the certain symbol is displayed. When the symbol is displayed in the reel display window 4, the reel stops. This stop table is referred to when the reel stop control is performed according to the operation of the stop switches 16L, 16C, and 16R. By performing such reel stop control, the symbol combination corresponding to the winning combination of the internal lottery is stopped and displayed on the reel display window 4 as much as possible. It should be noted that when the internal lottery is lost, a stop table is selected so that a symbol combination corresponding to any combination is not stopped and displayed on the reel display window 4.

  The symbol combination table associates each predetermined combination with a symbol combination in which each combination is established and the number of game medals to be paid out. This table is referred to when determining whether or not any combination has been established when all of the reels 3L, 3C, 3R are stopped.

  The control RAM 34 stores various information generated in the course of processing by the main CPU 32. For example, the number of medals stored in the slot machine 1, the result of internal lottery, the type of winning combination, various game states (general game (normal game not bonus game) or bonus game), etc. are stored. These pieces of information are transmitted to the sub control unit 60 via the sub control unit communication port 40. Various information exchanges between the main control unit 30 and the sub control unit 60 are performed in one direction from the main control unit 30 to the sub control unit 60, and the sub control unit 60 transfers to the main control unit 30. In contrast, no information is transmitted.

  The main CPU 32 includes a clock pulse generation circuit 35 that generates a reference clock pulse, a frequency divider 36 that divides the reference clock pulse, and a sampling circuit that samples the random numbers generated by the random number generator 37 and the random number generator 37 described above. 38 is connected. Here, the sampling circuit 38 samples the random number generated by the random number generator 37 when the start switch 17 is tilted. The main CPU 32 performs processing based on the reference clock pulse generated by the clock pulse generation circuit 35 and performs interrupt processing and the like at regular intervals based on the pulse signal generated by the frequency divider 36. Instead of using the random number generator 37 and the sampling circuit 38 described above as random number sampling means, the random number sampling may be executed on the operation program of the main CPU 32. In this case, the random number generator 37 and the sampling circuit 38 can be omitted. However, the random number generator 37 and the sampling circuit 38 may be left as they are for backup of the random number sampling operation without being omitted.

  The main output device whose operation is controlled by a control signal from the microcomputer 31 includes various indicators provided on the central panel 6 (see FIG. 1), a hopper 50 for storing game medals (a drive unit for payout) Stepping motors 53L, 53C, 53R for rotating the reels 3L, 3C, 3R. The microcomputer 31 is connected to the BET lamps 9a, 9b, 9c provided on the central panel 6 and the hit display lamps WN, the re-game display lamps RP constituting the gaming state display lamp group 12 through the lamp driving circuits 41, respectively. The game standby display lamp WT, start lamp ST, and insert lamp IN are driven and controlled. Further, the microcomputer 31 drives and controls each of the 7-segment displays of the bonus count display unit 8, the stored number display unit 10, and the payout number display unit 11 through each display unit drive circuit 42.

  Further, the microcomputer 31 drives and controls the hopper 50 by outputting a drive command to the hopper drive circuit 43, and drives the stepping motors 53L, 53C, and 53R by outputting a drive pulse signal to the motor drive circuit 44. Control. The various drive circuits described above are connected to the main CPU 32 via the I / O port 39, and each receives a control signal such as a drive command output from the main CPU 32 to control the operation of the corresponding output device. . That is, when a driving command is output from the microcomputer 31, the hopper driving circuit 43 supplies a driving current to the driving unit of the hopper 50 to pay out the game medal, and when the output of the driving command stops, The supply of the driving current is stopped, and the payout of game medals from the hopper 50 is stopped. The game medal paid out from the hopper 50 is discharged from the medal discharge port 20 to the medal tray 21. Further, each time the driving pulse signal corresponding to each stepping motor is output from the microcomputer 31, the motor driving circuit 44 rotates the corresponding stepping motor one step at a time.

  Next, as a main input device for generating an input signal necessary for the microcomputer 31 to generate a control command, a medal sensor 14S for detecting a game medal inserted into the medal slot 14, a BET switch 15, a stop switch There are switches such as 16L, 16C, 16R, start switch 17, and medal discharge switch 18. Signals output from these switches are output to the main CPU 32 via the I / O port 39. For the stop switches 16L, 16C, and 16R, a stop instruction signal corresponding to the stop switch pressed by the player is output from the reel stop signal circuit 51 and output to the main CPU 32 via the I / O port 39. The

  In addition to the switches described above, the main CPU 32 also receives signals output from photocouplers (not shown) provided corresponding to the reels 3L, 3C, 3R, respectively. These photocouplers are connected to a reel position detection circuit 45 in the main control unit 30, and when a reference position provided for each corresponding reel is detected, a reference position signal corresponding to that reel is output from the reel position detection circuit 45. Is output to the main CPU 32 via the I / O port 39. The main CPU 32 counts the number of drive pulse signals output to the motor drive circuit 44 corresponding to each stepping motor, and when the reference position signal is output from the reel position detection circuit 45 described above, The count value of the drive pulse signal output to the stepping motor driving the reel corresponding to the signal is reset. Thus, the main CPU 32 can recognize the type of symbol displayed on the reel display window 4 based on the count value of the drive pulse signal and the symbol table stored in the program ROM 33.

  Further, the main CPU 32 also receives a signal output from a medal detection unit 52 that detects a game medal paid out by the hopper 50. The medal detection unit 52 outputs a detection signal to the payout signal generation circuit 46 in the main control unit 30 every time the hopper 50 ejects one medal. Accordingly, the payout signal generation circuit 46 outputs the detection signal output from the medal detection unit 52 to the main CPU 32 via the I / O port 39, and the main CPU 32 outputs the number of detection signal outputs (the hopper 50 pays out). When the number of game medals reaches a target number of times (for example, the number of payouts corresponding to a winning combination or the number of game medals stored in the slot machine 1), the hopper driving circuit 43 Stop driving command output.

  Next, the configuration of the sub-control unit 60 will be described with reference to the block diagram shown in FIG. As described above, the sub-control unit 60 performs control related to effects by sound and images, which are executed along with the game, and the sub-CPU 61, the storage device 62, the RAM 63, the I / F circuit 64, and the sound control unit 65. The image control unit 66 and the chip set 67 are included. The storage device 62 stores various data such as an effect control program for controlling effects by sound and images, image data to be displayed on the main display 2 and the sub display 7, and audio data to be output from the speakers 5L and 5R. Has been. As this storage device 62, a mask ROM, a PROM (Programmable ROM), an EPROM (Erasable Programmable ROM), a memory made of a semiconductor chip such as a flash memory, a hard disk drive, a so-called USB (Universal Serial Bus) memory, a reader of various memory cards, Alternatively, a drive device (drive) of a removable storage medium such as a CD-ROM or DVD can be used.

  The sub CPU 61 executes the effect control program stored in the storage device 62, receives the result of the internal lottery output from the main control unit 30 received via the I / F circuit 64, the type of winning combination, various Based on information such as the game state, the contents of the effect to be executed are determined. In addition, image data and audio data corresponding to the determined contents of the presentation are read from the storage device 62 and transmitted to the audio control unit 65 and the image control unit 66, and audio and images based on the transmitted data are transmitted to the speakers 5L and 5R. , And output to the main display 2 and the sub display 7, respectively. The RAM 63 temporarily stores various information received from the main control unit 30 via the I / F circuit 64 and various data generated in the process of the sub CPU 61 executing the effect control program. Further, for example, when the power of the slot machine 1 is turned on, the presentation control program and various data stored in the storage device 62 are transferred to the RAM 63, and the sub CPU 61 accesses the RAM 63 to execute the presentation control program. Various data may be read out.

  The audio control unit 65 includes an audio signal generation unit 651 and a power amplifier 652, and the audio signal generation unit 651 generates an analog audio signal according to the audio data transferred from the storage device 62 by the sub CPU 61 and supplies the analog audio signal to the power amplifier 652. Output. The power amplifier 652 amplifies the analog audio signal output from the audio signal generation unit 651 and outputs the amplified analog audio signal to the speakers 5L and 5R. As a result, the analog audio signal amplified by the power amplifier 652 becomes audio and becomes the speaker 5L. , 5R to the outside.

  The image control unit 66 includes an image display control circuit 661, VRAM (Video RAM) 662a and 662b, and drive circuits 663a and 663b. Here, the image display control circuit 661 corresponds to image display control means, the VRAMs 662a and 662b correspond to image storage means, and the drive circuits 663a and 663b correspond to image signal supply means.

  The image display control circuit 661 converts the image data displayed on each screen of the main display 2 and the sub display 7 transferred from the storage device 62 by the sub CPU 61 into an image image, and displays the screens of the main display 2 and the sub display 7. Gradation data (corresponding to image display data) for each pixel constituting the pixel is written in the VRAMs 662a and 662b, respectively. Then, the gradation data written in the VRAMs 662a and 662b are controlled so as to be sequentially output to drive circuits 663a and 663b described later together with a display timing signal (described later).

  Each of the VRAMs 662a and 662b has an address space corresponding to the resolution of the corresponding display (VRAM 662a is the main display 2 and VRAM 662b is the sub display 7). That is, the VRAM 662a has column addresses “0” to “639” and row addresses “0” to “159”, and the VRAM 662b has column addresses “0” to “639” and “0”. ”To“ 479 ”exist. Each storage area specified by the column address and the row address corresponds to each pixel on the display. For example, when the pixel in the upper left corner is set as the origin on the display screen, the floor for this pixel is displayed. The key data is stored in a storage area designated by the column address “0” and the row address “0” in the VRAM.

  The drive circuits 663a and 663b respectively convert the gradation data output from the VRAMs 662a and 662b into analog signals (hereinafter referred to as image signals) having voltage values corresponding to the gradation data (digital data). It is applied to the pixel (liquid crystal pixel) corresponding to the storage area where the gradation data was stored. Here, the drive circuits 663a and 663b sequentially supply image signals to each pixel in units of rows, in the same manner as a known driver for driving the TFT liquid crystal image display device. That is, for example, when an image is displayed on the main display 2 (with the pixel in the upper left corner as the origin), first, gradation data having a row address of “0” and a column address of “0” to “159” is stored from the VRAM 662a. The output image signals corresponding to each gradation data are supplied to the pixels in each column in the first row (the top row) of the main display 2. Next, gradation data having a row address of “1” and column addresses of “0” to “159” are sequentially output from the VRAM 662a, and an image signal corresponding to each gradation data is displayed on the second display of the main display 2. Supplied to each column of pixels in the row. Thereafter, from the third row to the 180th row, image signals corresponding to the gradation data are sequentially supplied to the pixels in each column for each row.

  Next, the chip set 67 controls the exchange of various data and commands between the sub CPU 61, the storage device 62, the RAM 63, the I / F circuit 64, the sound control unit 65, and the image control unit 66. That is, the chip set 67 and the above-described units are connected by buses having different data transfer methods and transfer rates, and the chip set 67 is connected between the units that are performed via these different types of buses. Data and commands can be exchanged. Here, in the block diagram shown in FIG. 3, the sub CPU 61 and the chip set 67 are connected by a CPU bus 70, and the storage device 62 and the chip set 67 are connected by an IDE (Integrated Drive Electro) bus 71. The I / F circuit 64 and the audio control unit 65 and the chip set 67 are connected by a PCI (Peripheral Components Interconnect) bus 73, and the image control unit 66 and the chip set 67 are connected by a PCI-Express. (X16) Connected by a bus 74. Here, the PCI-Express bus 73 is a data transmission path having 16 lanes (transmission paths) for serially transferring data at a maximum speed of 2 gigabits / second in one direction.

  Next, the contents of processing when displaying images on the main display 2 and the sub-display 7 in the sub-control unit 60 having the above-described configuration will be described. First, the main control unit 30 outputs information such as the type of winning combination and various game states as a result of the internal lottery, and when these pieces of information are received by the I / F circuit 64, the sub CPU 61 temporarily stores them in the RAM 63. Remembered. Then, the sub CPU 61 determines the contents of effects to be executed on the main display 2 and the sub display 7 based on information from the main control unit 30 stored in the RAM 63. Next, the sub CPU 61 stores image data for the main display 2 (hereinafter referred to as “main image data”) and image data for the sub display 7 (hereinafter referred to as “sub image data”) corresponding to the determined contents of presentation. The data is read from the device 62 and transmitted to the image control unit 66. These image data are transferred to the image control unit 66 by the chip set 67 via the PCI-Express bus 74 at a transfer rate of up to about 4 gigabytes / second (one-way).

  When the image data is transferred to the image control unit 66, first, the image display control circuit 661 converts the image data into an image image based on the main image data, and the gradation for each pixel constituting the screen of the main display 2. Data is stored in a corresponding storage area of the VRAM 662a. Similarly, for the sub image data, the gradation data for each pixel constituting the screen of the sub display 7 is stored in the corresponding storage area of the VRAM 662b. As described above, when the image display control circuit 661 stores the gradation data for one screen to be displayed on the main display 2 and the sub display 7 in the VRAM 662a and the VRAM 662b, next, the gradation data stored in each VRAM is stored. And the display timing signal are output to the drive circuits 663a and 663b.

  Next, with reference to the timing chart shown in FIG. 4, the operation of each part of the image control unit 66 when displaying images on the main display 2 and the sub display 7 using the gradation data stored in the VRAM 662a and the VRAM 662b will be described. . In general, in a liquid crystal image display device, one screen is displayed in one frame, and if it is possible to display 30 frames per second, it is said that smooth movement can be expressed. That is, one frame may be displayed in 1/30 seconds. Further, in the liquid crystal image display device, in order to prevent liquid crystal deterioration, an image signal (plus voltage) is supplied to each pixel in the first half of one frame period, and each image supplied to each pixel in the second half of one frame period. AC driving is performed in which a voltage (negative voltage) obtained by reversing only the polarity of the voltage of a signal is applied to each pixel again. Here, the first half of one frame period is referred to as a positive field, and the second half is referred to as a negative field.

  The timing chart shown in FIG. 4 shows part of a display timing signal (pulse signal) transmitted from the image display control circuit 661 to the drive circuits 663a and 663b. Among the display timing signals shown in FIG. 4, the frame signal is distributed to one of the drive circuits 663a and 663b by distributing one signal generated in the image display control circuit 661. This frame signal has a period of 1/30 seconds and a duty ratio of 50%. The period from the rise of the frame signal to the fall is a positive field, and the period from the fall to the rise is negative. It is a field. Further, the synchronization signal A is transmitted to the drive circuit 663a, and the synchronization signal B is transmitted to the drive circuit 663b. Here, the synchronization signal A is generated by dividing the synchronization signal B by 3, and the synchronization signal B generates 480 pulse signals with a constant period during the positive field and the negative field. In the signal A, 160 pulse signals are generated at a constant cycle. Further, in FIG. 4, the numerical values described corresponding to the pulses of the respective synchronization signals (hereinafter referred to as synchronous pulses) represent the numerical values of the row addresses in the corresponding VRAM.

  When displaying an image on the main display 2 and the sub-display 7 by the image control unit 66, first, the image display control circuit 661 first starts the synchronization signal A after the frame signal rises (that is, the start of the positive field period). Until the sync pulse is output, the row address “0” of the VRAM 662a is designated, the column addresses “0” to “639” are designated sequentially, and the gradation data stored in each storage area are sequentially designated. , Output from the VRAM 662a to the drive circuit 663a. As a result, the drive circuit 663a converts each gradation data output from the VRAM 662a into an image signal, and holds (holds) it corresponding to each pixel column. Next, when the image display control circuit 661 outputs the first synchronization pulse to the drive circuit 663a after the rising edge of the frame signal, the drive circuit 663a displays each held image signal on the main display according to the timing of the synchronization pulse. In the two screens, the corresponding pixels in the first row are supplied. Thereby, a part of the image displayed on the main display 2 is displayed in the pixel row of the first row.

  Hereinafter, in the same manner, in the main display 2, the area of the image to be displayed is sequentially increased by one row, such as each pixel column of the second row and each pixel column of the third row, When an image in each pixel column of the 159th row is displayed, one image is displayed over the entire screen. When the frame signal falls and the negative field period starts, similar to the positive field period, gradation data for each pixel column is transmitted from the image control circuit 661 to the drive circuit 663a for each row, and during the positive field period. In addition, a signal having a voltage value obtained by inverting the polarity of the image signal supplied to each pixel is sequentially applied to each pixel. When one frame ends, image display control is performed in the same procedure for the image to be displayed in the next frame.

  The above-described image display control by the image display control circuit 661 is also performed in parallel for the VRAM 662b and the drive circuit 663b, but the image display control process performed for each row pixel on the screen of the sub display 7 is performed. The speed is three times faster than that for the main display 2. However, as can be seen from the timing chart shown in FIG. 4, the display control timings for the pixel columns in the last row are the same on each screen of the main display 2 and the sub-display 7, that is, one image on each display. The minutes display will be synchronized.

  As described above, according to the image control unit 66, the VRAMs 662 a and 662 b and the drive circuits 663 a and 663 b used for image display control have performance (for example, storage capacity, response speed, D− A conversion rate can be selected and used. In addition, since these devices are controlled by one image display control circuit 661, various timing signals for performing image display control can be shared or easily generated, so that an image to be displayed on each display can be displayed. There is an advantage that display timing can be easily synchronized.

It is a front view showing an appearance of a slot machine as an example of a gaming machine in an embodiment of the present invention. It is a block diagram which shows the structure of the main control part of the gaming machine. It is a block diagram which shows the structure of the sub-control part of the same gaming machine. 4 is a timing chart of various timing signals when an image is displayed on a display by a sub-control unit of the gaming machine.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Slot machine 2 Main display 3L, 3C, 3R Reel 4 Reel display window 7 Sub display 30 Main control part 60 Sub control part 61 Sub CPU
66 Image control unit 74 PCI-Express bus 661 Image display control circuit 662a, 662 VRAM
663a, 663 drive circuit

Claims (2)

A gaming machine that has variable display means for variably displaying a plurality of symbols composed of a plurality of types of symbols, and that grants a privilege to a player according to the stop display mode of the symbols displayed when the variable display stops There,
A plurality of image display devices having different numbers of pixels;
A plurality of image display devices provided corresponding to the plurality of image display devices, each having a storage capacity corresponding to the number of pixels of the corresponding image display device, and storing image display data for each pixel of the corresponding image display device Image storage means,
Provided corresponding to the plurality of image display devices and the image storage means, and each displays an image based on the image display data supplied from the corresponding image storage means in accordance with a timing signal supplied from the outside. A plurality of image signal supply means for generating an image signal for supplying the generated image signal to a corresponding image display device;
Each of the image display data is generated based on image data to be displayed on the plurality of image display devices supplied from the outside through a data transmission path, and the generated image display data is used as an image to display the image data. The timing signal for synchronizing the display of each image displayed on the plurality of image display devices is generated and stored in the image storage unit corresponding to the display device, to the plurality of image signal supply units An image display control means for supplying each of the game machines. 2. The gaming machine according to claim 1, wherein the data transmission path is a data transmission path that includes a plurality of transmission paths for serially transferring data, and serially transfers the image data through the plurality of transmission paths.

Images