JP2004254993A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine where the size of a picture to be displayed can be increased at low costs without spoiling game property. <P>SOLUTION: A picture display system for the game machine is provided with: one display controller 100 having a picture data distribution means 116; and a plurality of display devices 200a, 200b and 200c to be connected to this. The display controller 100 generates display data which all the display devices 200a, 200b and 200c use, and distributes the display data to each of the display devices 200a, 200b and 200c. Each of the display devices 200a, 200b and 200c display the picture by the distributed display data. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display technique which is mounted on a game machine and displays an image according to a game state. In particular, the present invention relates to a technique for efficiently displaying an image on each display device in an image display system that displays an image using a plurality of display devices (such as a liquid crystal display and a CRT).
[0002]
2. Description of the Related Art For example, in a game machine such as a pachinko machine, a display device is mounted on a game board, and various images are displayed on the display device in accordance with a game state. In this type of gaming machine, the interest of the game is enhanced by the image displayed on the display device, and the player feels fun. Therefore, a gaming machine has been developed in which a large display screen is given a large impact on a player (for example, Patent Document 1). In the gaming machine disclosed in Patent Literature 1, one large display device is mounted substantially at the center of the gaming board. One display control circuit (typically including a VDP) is connected to the display device. The display control circuit generates and outputs an image signal according to a game state. The display device displays an image based on the image signal output from the display control circuit.
[0003]
[Patent Document 1]
JP-A-10-272229
[0004]
In the technique described in Japanese Patent Application Laid-Open No. H11-163, there is a case where the display device itself becomes large, thereby impairing the game performance. In the pachinko machine described in Patent Literature 1, a large-sized display device is disposed substantially at the center of the game board, so that the pachinko balls flow only in narrow areas on both sides of the display device (both ends of the game board). Therefore, it becomes difficult to change the flow of the pachinko ball, and the fun of the movement of the pachinko ball is impaired.
Therefore, a plurality of display devices are arranged at an interval on the game board, and a game area where the pachinko balls flow down between the display devices is formed, so that the image displayed by the display device is felt large while the pachinko balls are displayed. It is conceivable to secure a flowing area. However, if a display control circuit is provided for each display device, there is a problem that the cost increases.
[0005]
The present invention has been made in view of the above points, and an object of the present invention is to provide a gaming machine capable of increasing the size of a displayed image at a low cost without impairing the game performance.
[0006]
In order to solve the above-mentioned problems, a first gaming machine of the present application has a plurality of display devices, and displays images on these display devices according to a game state. And one display control circuit connected to the plurality of display devices and outputting a group of image signals for one frame at predetermined intervals. Each display device acquires an image signal group for the display device from the image signal group periodically output from the display control circuit and displays an image.
In this gaming machine, an image signal group for displaying an image (one frame) on each display device is periodically output from one display control circuit. Each display device takes in an image signal group for the display device from an image signal group periodically output from the display control circuit and displays an image. Therefore, even if only one display control circuit is provided, an image for the display device can be displayed on each display device, and a gaming machine can be configured at low cost.
In this gaming machine, an image is displayed using a plurality of display devices, so that a large image as a whole can be displayed even if the screen of each display device is reduced. Since the screen of each display device can be reduced, the layout space can be reduced, and each display device can be disposed on the gaming machine without impairing the game performance.
[0007]
The plurality of display devices provided in the gaming machine may be display devices having the same number of pixels or display devices having different numbers of pixels. When a display device having a different number of pixels is provided, an image signal group (an image signal for one frame) periodically output from the display control circuit has a number corresponding to the number of pixels of the display device using the image signal group. Image signal. Further, the cycle of outputting the image signal group may be changed according to the difference in the number of image signals.
Alternatively, even when a display device having a different number of pixels is provided, the display control circuit outputs an image signal group including the same number of image signals, and outputs a required number of image signals from the image signal group to the display device side. May be taken in. In this case, an image signal group is constituted by image signals of the number corresponding to the display device having the largest number of pixels.
[0008]
In the above gaming machine, the display control circuit outputs a recognition signal to one display device when outputting the image signal group, and the display device that has received the recognition signal captures the image signal group and displays an image. Is preferred.
In such a configuration, since each display device captures the image signal group in response to the recognition signal output from the display control circuit, each display device is prevented from erroneously capturing the image signal group.
The frequency of outputting the recognition signal may be the same for each display device, or may be different for each display device. For example, a display device having a large number of pixels can output a recognition signal at a high frequency, and a display device having a small number of pixels can output a recognition signal at a low frequency. In this case, a display device having a large number of pixels receives an image signal in a shorter cycle and displays an image as compared with a display device having a small number of pixels.
[0009]
Each display device includes a display, a driving circuit that displays an image on the display using an input image signal group, a storage unit that stores the image signal group, and a control unit that is connected to the storage unit and the driving circuit. And a circuit. The control circuit outputs (1) the image signal group output by the display control circuit to the drive circuit when the recognition signal is received in the period in which the display control circuit outputs the image signal group, and (2) If the display control circuit does not receive the recognition signal in the cycle of outputting the image signal group, it is preferable to output the image signal group stored in the storage means to the drive circuit.
In such a configuration, an image is displayed using the captured image signal group in a cycle of capturing the image signal group, and an image is displayed using the immediately captured image signal group in a cycle in which the image signal group is not captured. For this reason, each display device displays an image at a cycle shorter than the cycle of taking in the image signal group. This makes it possible to prevent the flickering of the image of each display device even if the period of capturing the image signal group into each display device becomes long.
[0010]
Further, the second gaming machine of the present application is a gaming machine that includes N display devices and displays an image on the N display devices according to a game state, and further includes one display control circuit. The display control circuit is connected to N display devices and repeatedly outputs an image signal group for one frame of the first display device to an image signal group for one frame of the Nth display device in order. Each display device acquires an image signal group for the display device from the image signal group output from the display control circuit and displays an image.
According to this gaming machine, the same operation and effect as the gaming machine according to the first aspect can be achieved.
[0011]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the main features of the embodiments described below are listed. (Mode 1) A display control device (corresponding to a display control circuit in the claims) includes a CPU, a video display processor (hereinafter, referred to as VDP), and a distribution circuit for image signals.
(Mode 2) The VDP according to mode 1 creates image data used by a plurality of display devices and outputs the image data as an image signal. Further, a clock signal is output in synchronization with the output of the image signal.
(Mode 3) The distribution circuit according to mode 1 distributes an image signal output from a VDP so as to be output only to a display device using the image signal. Each display device displays an image using an input image signal.
(Mode 4) The distribution circuit according to mode 3 counts image signals to be output to the selected display device. When the counted number of image signals matches the number of image signals used by the selected display device, the output destination is switched to the next display device.
(Embodiment 5) Each display device has a display, a drive circuit for driving the display, and temporary storage means for temporarily storing the captured image signal group. The drive circuit repeatedly displays the image signal group stored in the temporary storage unit on the display until a new image signal group is captured.
(Mode 6) A display control device (corresponding to a display control circuit in the claims) includes a CPU, a VDP, and a recognition signal generation circuit.
(Mode 7) The recognition signal generation circuit outputs a recognition signal for designating a group of image signals to be taken into each display device. Each display device has a display, a drive circuit for driving the display, a memory for temporarily storing the captured image signal group, and a controller connected to the memory and the drive circuit. When the controller receives the recognition signal in the cycle in which the VDP outputs the image signal group, the controller outputs the image signal group output by the VDP to the drive circuit and overwrites the memory. On the other hand, if the VDP does not receive the recognition signal in the cycle of outputting the image signal group, the image signal group stored in the memory is output to the drive circuit.
[0012]
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is embodied as a pachinko machine which is a kind of a game machine will be described in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of the image display system according to the first embodiment. As shown in FIG. 1, the image display system according to the present embodiment includes a display control device 100 and a plurality (three in this embodiment) of display devices 200a, 200b, and 200c connected to the display control device 100. (The display devices 210a to 210c each have a resolution of nxm dots.)
[0013]
The display control device 100 includes a control ROM 104, a character ROM 106, a VRAM 108, a color pallet RAM 110, a VDP 112, and a distribution circuit 116, with a CPU 102 at the center. The CPU 102 is connected to the main control device 10 that controls the entire pachinko machine. When receiving the command data output from the main control device 10, the CPU 102 reads the variation pattern data (scheduler data) specified by the command data from the control ROM 104, sequentially decodes the read scheduler data, and handles the decoded scheduler data with the VDP 112. The control signal is converted into a control signal that can be output, and the converted control signal is output to the VDP 112. The scheduler data is data that defines the schedule of a series of images displayed on the display devices 200a, 200b, and 200c (for example, a special symbol stop timing).
[0014]
The VDP 112 is a known VDP of a line buffer system, and is connected to the character ROM 106, the color palette RAM 110, and the VRAM 108. The character ROM 106 stores display data (consisting of a color number designating the color of each dot) for displaying a display character (such as a number constituting a special symbol). The color palette RAM 110 stores color data for each color number. The VRAM 108 stores data designating which character number display data is to be arranged in each area set in the image creation area of the VDP 112.
When the control signal output from the CPU 102 is input, the VDP 112 performs the following processing according to the control signal. The VDP 112 first specifies the data stored in the VRAM 108 based on the input control signal, and arranges the display data stored in the character ROM 106 in each area constituting the image creation area based on the data. I do. Next, scanning lines are sequentially taken out one by one from the image forming area where the display data is arranged, and the display data (color number) constituting the scanning line is converted into an image signal using the data of the color palette RAM 110. . When the image signals have been output for all the scanning lines, the process ends.
As is apparent from the above, the VDP 112 outputs an image signal for one image (one frame) based on one control signal input from the CPU 102. Since control signals are sequentially input to the VDP 112 from the CPU 102, an image signal for one frame is output from the VDP 112 each time the control signal is input.
[0015]
FIG. 2 schematically shows how an image signal output from the VDP 112 is distributed to the display devices 200a, 200b, and 200c. As shown in FIG. 2, when the VDP 112 outputs the image signal group a (n × m dots) for the display device 200a, the VDP 112 outputs the image signal group b (n × m dots) for the display device 200b. An image signal group c (n × m dots) for the device 200c is output, and similarly, an image signal group for the display device 200a is repeatedly output in order from the image signal group for the display device 200a. Therefore, the VDP 112 periodically outputs a group of image signals for the display devices 200a to 200c in a predetermined order.
The VDP 112 outputs a vertical synchronization clock signal each time an image signal of one image (one frame) is output, and outputs a horizontal synchronization clock signal each time an image signal for one scanning line is output. The horizontal synchronization clock signal is output in synchronization with the output of the first image signal of the scanning line. The output synchronous clock signals are input to the distribution circuit 116 and the display devices 200a to 200c.
[0016]
Distribution circuit 116 outputs the image signal group output from VDP 112 to a display device (any of display devices 200a to 200c) using the image signal group. In the example of FIG. 2, the image signal group a is output to the display device 200a, the image signal group b is output to the display device 200b, and the image signal group c is output to the display device 200c. That is, each of the display devices 200a, 200b, and 200c is a display device of nxm dots, and one image (one frame) is composed of n scanning lines. When the distribution circuit 116 starts outputting the image signal to one display device, the distribution circuit 116 starts counting the horizontal synchronization clock signal triggered by the vertical synchronization clock signal output from the VDP 112. When the counted number becomes n, the image signal from the VDP 112 is output to the next display device. At this time, the value of the counter is reset and counting is started again. Thus, the distribution circuit 116 distributes the image signal to each of the display devices 200a to 200c.
[0017]
As shown in FIG. 1, the display device 200a includes a controller 202a, a liquid crystal display 206a (n × m dots), and an LCD driver circuit 204a that outputs a drive signal to the liquid crystal display 206a to display an image. .
The controller 202a includes a memory 201a for temporarily storing an image signal (n × m dots) for displaying one image (one frame) on the liquid crystal display 206a. The controller 202a has a function of outputting an input image signal to the LCD driver circuit 204a, temporarily storing the image signal in the memory 201a, and outputting the image signal temporarily stored in the memory 201a to the LCD driver circuit 204a at a predetermined timing. Prepare. The LCD driver circuit 204a is a drive circuit for displaying an image on the liquid crystal display 206a using an image signal output from the controller 202a.
When an image signal is input from the distribution circuit 116 to the display device 200a, the input image signal is temporarily stored in the memory 201a of the controller 202a and output to the LCD driver circuit 204a. On the other hand, when no image signal is input from the distribution circuit 116 to the display device 200a, the image signal stored in the memory 201a is output to the LCD driver circuit 204a. When an image signal for one image (one frame) is input from the controller 202a, the LCD driver circuit 204a displays an image on the liquid crystal display 206a using the input image signal. When a new image signal is input to the display device 200a, the image signal is overwritten on the memory 201a of the controller 202a.
In this embodiment, the cycle at which the LCD driver circuit 204a displays an image on the liquid crystal display 206a is the same as the cycle at which the VDP 112 outputs one frame of image signal. Therefore, the image is displayed on the liquid crystal display 206a even while the image signal is being output to the display devices 200b and 200c. During this time, since no new image signal is input to the display device 200a, the same image is displayed on the display device 206a by repeatedly using the image signal stored in the memory 201a of the controller 202a. The VDP 112 according to the present embodiment outputs an image signal for 60 frames per second, and the image signal is distributed by the distribution circuit 116 to the three liquid crystal displays 206a, 206b, and 206c by 20 frames. Therefore, since the screen of the liquid crystal display 206a is updated even while no image signal is input from the display control device 100, flickering of the screen of the liquid crystal display 206a is prevented, and high-quality display is possible.
Although the flickering of the screen can be improved by increasing the frame rate of the VDP, when the conventional VDP is used, the flicker exceeds the specification range. Even if the frame rate of the VDP can be increased within the operable range (for example, even if the VDP has the ability to superimpose and display five images as one frame image), a frame is created at high speed. For this reason, the superposition process cannot be performed in time, and the performance cannot be sufficiently exhibited.
[0018]
The display devices 200b and 200c have the same configuration as the display device 200a, and display images on the liquid crystal displays 206b and 206c using image signals input from the distribution circuit 116. As is apparent from the above description, different image signals are input to the liquid crystal displays 206a, 206b, and 206c, and different images are displayed.
[0019]
FIG. 3 shows a state where the above-mentioned liquid crystal displays 206a, 206b, 206c are mounted on a game board. As shown in FIG. 3, three liquid crystal displays 206a, 206b, and 206c are mounted side by side on the game board 20. As is clear from the figure, each of the liquid crystal displays 206a, 206b, and 206c has a smaller display area than the liquid crystal display mounted on a normal pachinko machine. For this reason, an area 22a where pachinko balls can flow down is formed between the liquid crystal display 206a and the liquid crystal display 206b, and an area 22b where pachinko balls can flow down between the liquid crystal display 206b and the liquid crystal display 206c. Is formed. Therefore, the pachinko balls can flow down the game area 22 of the game board 20 without bias.
[0020]
As is clear from the above description, in the present embodiment, since an image is displayed using a plurality of display devices, it is possible to display a large image as a whole even if the screen of each display device is small. In particular, since the display devices are arranged at intervals, it is possible to give the player an illusion that a larger image is displayed. Further, since the pachinko ball can flow down between the respective display devices, the pachinko ball can flow down without biasing the game area, thereby preventing the fun of the movement of the pachinko ball from being spoiled.
Further, display data (image signals) of a plurality of display devices is generated from one VDP. Since the VDP only periodically generates and outputs one display screen display data, a conventional general-purpose VDP can be used. Therefore, the display control device can be configured at low cost.
Furthermore, since only the image signal used by the display device is input to each display device by the distribution circuit, the display device can display using the input image signal as it is.
[0021]
Second Embodiment Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing the configuration of the image display system according to the second embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will not be repeated. As is apparent from FIG. 4, also in the second embodiment, the basic configurations of the display control device 120 and the display devices 210a to 210c are substantially the same as those in the first embodiment. However, in the first embodiment, only the image signal for the display device is output to each of the display devices 200a, 200b, and 200c by providing the distribution circuit 116, but in the second embodiment, each of the display devices 200a, 200b, and 200c is output to the display device 200a, 200b, and 200c. All the image signals generated by the display control device 120 are output, and each of the display devices 200a to 200c outputs only the image signal for the display device based on the recognition signal separately output from the display control device 120 to the controllers 208a to 208c. It differs in that it takes in. Hereinafter, only different points from the first embodiment will be described.
[0022]
As shown in FIG. 4, the display control device 120 of the second embodiment is provided with a recognition signal generation circuit 122 instead of the distribution circuit of the first embodiment. The recognition signal generation circuit 122 is connected to the VDP 112 and the controllers 208a to 208c of the respective display devices 210a to 210c. A clock signal output from the VDP 112 is input to the recognition signal generation circuit 122, and a recognition signal indicating which display device the image signal output from the VDP 112 is based on the clock signal is displayed on each display. Output to the devices 210a to 210c.
FIG. 5 schematically illustrates the states of the clock signal, the recognition signal, and the image signal displayed on the display device output from the display control device 120 according to the second embodiment. As is clear from FIG. 5, the VDP 112 repeatedly outputs the image signal group a for the display device 210a to the image signal group c for the display device 210c in order, as in the first embodiment. When the image signal group a for the display device 210a is being output from the VDP 112, the recognition signal a output from the recognition signal generation circuit 122 to the display device 210a is ON. When the image signal group b for the display device 210b is being output from the VDP 112, the recognition signal b output from the recognition signal generation circuit 122 to the display device 210b is in the ON state. Similarly, when the image signal group c for the display device 210c is being output from the VDP 112, the recognition signal c output from the recognition signal generation circuit 122 to the display device 210c is in the ON state. Each of the display devices 210a to 210c determines that the clock signal is valid only when the input recognition signal is in the ON state, and stores the image signal input from the VDP 112 in the controllers 208a to 208c. As a result, only the image signals for the display devices are taken into the controllers 208a to 208c of the display devices 210a to 210c. The processing of each of the display devices 210a to 210c after the image signal is captured is the same as in the first embodiment.
[0023]
The switching of the state of the recognition signal output from the recognition signal generation circuit 122 to each of the display devices 210a to 210c can be performed based on a clock signal input from the VDP 112. That is, in each of the display devices 210a, 210b, and 210c, one image (one frame) is composed of n scanning lines. The VDP 112 outputs a vertical synchronization clock signal each time an image signal of one image (one frame) is output, and outputs a horizontal synchronization clock signal each time an image signal for one scanning line is output. Therefore, the recognition signal generation circuit 122 can count the clock signal output from the VDP 112 and switch the state of the recognition signal based on the count value.
[0024]
As is apparent from the above description, also in the second embodiment, image signals used in a plurality of display devices are generated from one VDP of one display control device, and each display device is generated by a recognition signal output from the display control device. Are distributed to the image signal. Therefore, different images can be displayed on each display device with an inexpensive configuration, and the same operation and effect as in the first embodiment can be obtained.
Note that the recognition signal output from the display control device to each display device is not limited to the form shown in FIG. 5, and for example, a recognition signal as shown in FIG. 6 may be output. That is, in the example shown in FIG. 6, at t1 'immediately before the image signal group a for the display device 210a is output from the VDP 112, a pulse-like recognition signal is output from the recognition signal generation circuit to the display device 210a. When detecting the edge change of the recognition signal, the display device 210a captures the image signal into the controller 208a for a predetermined number of scanning lines (that is, n lines). The recognition signals for the display device 210b and the display device 210c can have the same form as the recognition signal for the display device 210a. That is, the recognition signal output from the recognition signal generation circuit is used as a vertical synchronization clock signal for each of the display devices 210a to 210c. Even with such a configuration, the image signal output from the VDP 112 can be distributed to each of the display devices 210a to 210c.
[0025]
As mentioned above, although the specific example of this invention was demonstrated in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and alterations of the specific examples illustrated above.
For example, in the above-described embodiment, an example in which the line buffer type VDP is used has been described. However, the technology of the present invention is not limited to the line buffer type VDP, but can be applied to a frame buffer type VDP. Further, in the above-described embodiment, the example in which the image display system according to the present invention is attached to a pachinko machine has been described. is there.
In the above-described embodiment, the plurality of display devices provided in the gaming machine are all display devices having the same number of pixels. However, display devices having different numbers of pixels may be provided. Further, in the above-described embodiment, the image signal group (image signal for one frame) is uniformly output from the VDP to each display device, but the frequency of the image signal group output from the VDP to each display device is determined by the display device. It may be changed every time.
The technical elements described in the present specification or the drawings exhibit technical usefulness either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology illustrated in the present specification or the drawings simultaneously achieves a plurality of objects, and has technical utility by achieving one of the objects.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of an image display system according to a first embodiment.
FIG. 2 is a diagram schematically illustrating a state in which image data created by a display control device (VDP) of the first embodiment is distributed to each display device.
FIG. 3 is a view showing a state in which each display constituting the image display system of the first embodiment is mounted on a game board;
FIG. 4 is a block diagram illustrating a configuration of an image display system according to a second embodiment.
FIG. 5 is a diagram schematically illustrating a relationship between image data created by a display control device (VDP) according to a second embodiment, a recognition signal, and image data used in each display device.
FIG. 6 is a view for explaining a modification of the second embodiment.
[Explanation of symbols]
100, 120 ··· display control device
102 CPU
106 Character ROM
108 VRAM
110 color RAM
112 VDP
116 ··· Distribution circuit
122 ·· Recognition signal generation circuit
200a, 200b, 200c-display device
202a, 202b, 202c controller
204a, 204b, 204c LCD driver circuit
206a, 206b, 206c ... liquid crystal display

Claims (1)

A gaming machine comprising a plurality of display devices, and displaying an image on these display devices according to a game state,
A display control circuit that is connected to a plurality of display devices and outputs an image signal group for one frame every predetermined period;
A gaming machine wherein each display device takes in an image signal group for the display device from an image signal group periodically output from a display control circuit and displays an image.

Images