JP2008205717A - Distributed type pulse polarity modulation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a distributed type pulse polarity modulation circuit a small in circuit scale, reduced in offset and wide in band. <P>SOLUTION: The distributed type pulse polarity modulation circuit connects a plurality of unit cells 14-1, 14-2 and 14-n. Each unit cell has pulse generating circuits 15-1, 15-2 and 15-n generating pulse signals having unipolarity and pulse polarity modulation circuits 16-1, 16-2 and 16-n generating the pulse signals having bipolarity according to data from pulse signals outputted from the pulse generating circuits. The pulse polarity modulation circuit 16-n for one unit cell 14-n in the plurality of unit cells has an offset canceling circuit 17 canceling the offset of the whole distributed type pulse polarity modulation circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a distributed pulse circuit that generates a pulse in a wide band, and more particularly to a distributed pulse polarity modulation circuit that generates a bipolar pulse.

  A distributed pulse circuit is used as a circuit for generating a pulse signal having a short pulse width. A distributed pulse circuit is described in Patent Document 1, for example. FIG. 1 is a diagram showing a configuration of a conventional distributed AND circuit that uses a one-stage AND circuit as a unit cell. As shown in FIG. 1, this circuit includes n AND circuits 4-1, 4-2, 4-3,..., 4-n and impedances 2-1, 2-2, 2-3,. 2-n, 3-1, 3-2, 3-3,..., 3-n and 5-1, 5-2, 5-3,. Thus, the half width of the pulse of the output Q is narrowed to the limit (wide band). One clock signal B of two clock signal inputs (which may be the same signal here) A and B is delayed by the delay circuit 1 and input to one end of the first stage impedances 2-1 and 3-1. The pulse width of the pulse signal output Q is defined by the delay amount of the delay circuit 1. With such a configuration, an ultra-wideband logic operation circuit is realized.

  FIG. 2 shows a detailed internal configuration of a circuit unit (here, the second stage) 6-2 for one stage of the distributed logical product circuit of FIG. Input clock signals A and B are complementary signals A, NA, B, and NB, respectively. A unit cell (AND circuit) 4-2 in a circuit unit is a vertically stacked two-stage differential circuit, and two complementary clock signals A, NA, B, and NB are input to a transistor pair, respectively. The impedances 7-2, 8-2, and 9-2 are divided into front and rear at the connection node with the AND circuit 4-2, and the first half is one of the impedances 2-2, 3-2, and 5-2 in FIG. The second half corresponds to a part of the impedances 2-3, 3-3, and 5-3 in FIG.

  The conventional distributed AND circuit of FIGS. 1 and 2 has only a function of generating a pulse, and cannot modulate its polarity (generate a biphase pulse).

  Inventor of the present application discloses a pulse polarity modulation circuit that modulates a unipolar pulse into a bipolar pulse in Patent Document 2. FIG. 3 is a diagram showing a configuration of a conventional pulse polarity modulation circuit described in Patent Document 2. In FIG. As shown in FIG. 3, the pulse polarity modulation circuit includes a pulse polarity conversion unit 10 and a switching noise cancellation unit 20. The pulse polarity converter 10 includes transistor pairs 11 and 12, 13 and 14, transistor pairs 15 and 16 connected to two transistor pairs, a constant current source 17 connected in common to the transistor pairs 15 and 16, and transistors Resistors 18 and 19 connected to 11 and 12 are provided. Data signals D and / D for selecting polarity are applied to the gates of the transistor pairs 11 and 12, and complementary pulse signals P and nP are applied to the gates of the transistor pairs 15 and 16. Outputs Q and nQ are obtained from connection nodes of the transistor pairs 11 and 12, 13 and 14, and resistors 18 and 19. The pulse polarity converter 10 is a widely known circuit called a Gilbert mixer circuit, and a description thereof will be omitted.

  In the pulse polarity converter 10, the transistor 15 is not completely turned off and a minute leak current flows. When the data signals D and / D change, the current flows through the transistor 12 and an offset occurs in the output NQ. . This offset is canceled by the switching noise canceling unit 20.

  The switching noise canceling unit 20 includes transistor pairs 21 and 22 and a transistor 23 commonly connected thereto. Since the offset is caused by a minute current flowing through the transistor 12 via the resistor 19 when the data signal is switched, the offset is canceled so that the same current flows through the resistor 19 even before the data signal is switched by the transistor 22.

  Since the operation of the pulse polarity converter 10 in FIG. 3 is described in detail in Patent Document 2, further description thereof is omitted.

JP-A-10-224207 JP 2006-157649 A

  When the distributed AND circuit described in FIGS. 1 and 2 has a pulse polarity modulation function for outputting a bipolar pulse, the pulse polarity modulation circuit of FIG. 3 is used instead of the AND circuit 4-2. Can be considered. Since the offset of the pulse polarity modulation circuit of FIG. 3 is small, a distributed pulse polarity modulation circuit with good characteristics can be realized by such a combination.

  However, when the pulse polarity modulation circuit of FIG. 3 is applied to the distributed AND circuit described in FIGS. 1 and 2, there is a problem that the circuit scale becomes large.

  3 has a switching noise canceling unit (offset canceling circuit unit) in order to reduce the offset, but the switching noise canceling unit works as a load capacitance. There is a problem of shortening the band and narrowing the band. This problem will be described with reference to FIG.

  FIG. 4A shows the pulse polarity modulation circuit of FIG. 3, but attention is paid to the portion surrounded by a dotted line. If attention is paid only to the capacitance component of the offset cancel circuit section, it can be considered that the parasitic capacitance Cf is hung from the load as shown in FIG. Due to this Cf, the operation cutoff frequency fcout when the inside of the circuit is viewed from the output (Vout) is lowered by Cf as shown in FIG. In order to generate a wider-band pulse (a pulse with a narrow half width), it is necessary to increase the cutoff frequency fcout of the circuit, and it is effective to remove the offset cancel circuit. However, if the offset cancel circuit is removed, an offset is generated at the logic midpoint level, and this offset is amplified by unit cells connected in multiple stages, so that the offset of the logic midpoint level of the final output waveform becomes large. Cause problems.

  As described above, a bi-phase pulse generation circuit that only combines conventional techniques has a problem that it is difficult to reduce both the half-value width of the obtained pulse and increase the waveform quality (offset). It was.

  An object of the present invention is to solve such problems and to realize a distributed pulse polarity modulation circuit having a small circuit scale, a small offset, and a wide band.

  In order to achieve the above object, according to the present invention, an offset cancel circuit is provided only in one unit cell of a plurality of unit cells of a distributed pulse polarity modulation circuit, and an offset is provided in the other unit cell. The cancel circuit is not provided, and the offset of the entire distributed pulse polarity modulation circuit, that is, the offset in the output is canceled by the offset cancel circuit of the single unit cell.

  The offset cancel circuit is provided in the pulse polarity modulation circuit of the last unit cell, for example.

  According to the present invention, a pulse having a narrow half-value width is generated in a unit cell not provided with an offset cancel circuit, and the offset of the entire distributed pulse polarity modulation circuit is canceled by the pulse polarity modulation circuit of one unit cell. Thus, both the waveform quality of the biphase pulse and the shortening of its half width are compatible.

  According to the present invention, a distributed pulse polarity modulation circuit that generates a pulse with a narrow half-value width and no offset can be realized with a small circuit scale.

  FIG. 5 is a diagram showing the configuration of the distributed pulse polarity modulation circuit according to the embodiment of the present invention. This circuit is a circuit in which the pulse polarity modulation circuit of FIG. 3 is applied to the distributed AND circuit described in FIGS. 1 and 2, but the offset cancel circuit 17 has one stage (here, the last stage) unit cell. It is provided only in the other unit cells, and is not provided in other unit cells.

  The distributed pulse polarity modulation circuit of this embodiment includes n unit cells 14-1, 14-2, 14-3,..., 14-n and impedances 12-1, 12-2, 12-3,. , 12-n, 13-1, 13-2, 13-3,..., 13-n and 19-1, 19-2, 19-3,. Thus, the half width of the pulse of the output Q is narrowed to the limit (wide band). The n unit cells 14-1, 14-2, 14-3,..., 14-n are pulse generation units (AND circuits) 15-1, 15-2, 15-3,. , (Pulse) polarity modulation units 16-1, 16-2, 16-3,..., 16-n, and the unit cell 14-n at the final stage further offsets to the polarity modulation unit 16-n. A circuit 17 is attached.

  As shown in the figure, one clock signal B of two clock signal inputs (which may be the same signal here) A and B is delayed by the phase φ by the delay circuit 11 and is one end of the first stage impedances 12-1 and 13-1. Is input. The pulse generation unit (AND circuit) generates a pulse by taking the logical product of two clock signals A and B having a phase difference φ, and the polarity modulation unit modulates the polarity of the pulse according to the data signal D. The data signal D is also supplied to each polarity modulation section via a distributed constant line composed of impedances 18-1, 18-2, 18-3, 18-4.

  FIG. 6 shows a detailed internal configuration of the circuit unit (here, the second stage) 20-2 from the first stage to the (n-1) th stage of the distributed pulse polarity modulation circuit of the embodiment of FIG. The circuit units from the first stage to the (n-1) th stage have the same circuit configuration. Impedances 21-2, 22-2, and 24-2 correspond to 7-2, 8-2, and 9-2 in FIG. 2, respectively. The first half of the impedance 23-2 corresponds to a part of the impedance 18-2 in FIG. 5, and the second half corresponds to a part of the impedance 18-3 in FIG.

  The pulse generation circuit 15-2 includes transistor pairs 31 and 32, 33 and 34, 35 and 36, a transistor 37, and resistors 38 and 39 connected as illustrated. The polarity modulation circuit 16-2 includes transistor pairs 41 and 42, 43 and 44, 45 and 46, and a transistor 47 that are connected as illustrated.

  Input clock signals A and B are complementary signals A, NA, B, and NB, respectively. Both the pulse generation circuit and the polarity modulation circuit of the unit cell 14-2 are two-stage differential circuits that are vertically stacked. Two differential clock signals A, NA and B, NB having a phase difference are input to differential transistor pairs 31 and 32, 35 and 36 of the pulse generation circuit, respectively. The upper right differential transistor pairs 33 and 34 are fixedly biased on and off, respectively, as shown. The pulse generated from the pulse generation circuit is input to the lower differential transistor pair of the polarity modulation circuit, and the differential data D and ND are input to the upper differential transistor pair 41 and 42 of the polarity modulation. Further, both the upper right transistor pair 43 and 44 are biased to Vm (the midpoint level of logic “High” and “Low”). The output polarity modulation pulse is added in phase with the output waveform from the subsequent unit cell via the output transmission line 24-2.

  The configuration and operation of the unit cell are the same as the configuration and operation of the circuit described in Patent Document 2 except that the offset cancel circuit is not provided.

  FIG. 7 shows a detailed internal configuration of the n-th circuit unit 20-n of the distributed pulse polarity modulation circuit of the embodiment of FIG. The n-th circuit unit 20-n is a circuit from the first stage to the (n-1) -th stage except that the transistor pair 51 and 52 and the transistor 53 constituting the offset cancel circuit are provided in the polarity modulation circuit. It has the same circuit configuration as the unit.

  FIG. 8 is a time chart showing the operation of the distributed pulse polarity modulation circuit according to the embodiment of the present invention. As shown in the figure, the polarity of the pulse is selected according to the value of the data signal D. In the pulse waveform to be output, the amplitude of the pulse grows from the first stage to the (n−1) th stage in order, but at the point where the data signal D switches (at the logic midpoint level of the waveform), there is also a small voltage offset. You can see that it grows gradually. Since this minute offset is finally greatly amplified by the output amplifier, it becomes a factor of deteriorating the output waveform quality. In the distributed pulse polarity modulation circuit of this embodiment, the gate voltage Voff of the transistor 53 is appropriately set so that this offset is canceled by the offset cancel circuit 17 of the unit cell at the final stage. Thereby, the output of the last stage becomes a signal without an offset.

  As described with reference to FIG. 4, the offset cancel circuit has a load capacity and causes a problem that the half width of the pulse does not become thin. However, the present invention solves this problem. The effect of the present invention varies depending on the transistor used and its design parameters (size, etc.), but as a transistor constituting the circuit of the present invention, an indium phosphide-based high electron mobility transistor (InP-HEMT) of a compound semiconductor device is used. Assuming use, the capacitance value (Cf) predicted from a typical transistor size, the transconductance gm, the gate-source capacitance (Cgs), and the cutoff frequency definition formula shown in FIG. When the offset cancel circuit is provided as such, the cutoff stage frequency is about 80 GHz. When the offset cancellation circuit is provided only at the final stage as in the present invention, the cutoff stage frequency is about 120 GHz. This is merely an example, but the band of the unit cell varies greatly depending on the presence or absence of the offset cancel circuit.

  FIG. 9 shows a configuration of the present invention in which an offset cancel circuit is provided only in the final stage in a biphase circuit three-stage configuration, and an offset cancel circuit is provided in all stages in a biphase circuit three-stage configuration. It is a figure which shows the pulse shape in the structure of a prior art example. It can be seen that the pulse width is narrower in the present invention.

  FIG. 10 is a diagram showing the effect of the offset cancellation circuit by simulation, and it can be seen that no offset occurs.

  In the above embodiment, the offset cancellation circuit is provided in the final unit cell, but as shown in FIG. 11, the offset cancellation circuit may be provided in another unit cell. In this case, the gate voltage of the transistor of the offset cancel circuit is set so that there is no offset at the output of the last unit cell.

  Although the embodiments of the present invention have been described above, it goes without saying that various modifications are possible.

  The present invention is applicable to any distributed pulse polarity modulation circuit.

It is a figure which shows the structure of the conventional distributed AND circuit. It is a figure which shows the detail of the circuit of each stage of FIG. It is a figure which shows the structure of the conventional pulse polarity modulation circuit. It is a figure explaining increase of both loads by the offset cancellation circuit in the pulse polarity modulation circuit of FIG. It is a figure which shows the structure of the distributed pulse polarity modulation circuit of the Example of this invention. FIG. 6 is a diagram showing details of a first to n−1 stage circuit of the distributed pulse polarity modulation circuit of FIG. 5. FIG. 6 is a diagram showing details of an nth stage circuit of the distributed pulse polarity modulation circuit of FIG. 5. It is a time chart which shows the offset cancellation in the distributed pulse polarity modulation circuit of an Example. It is a figure which shows the difference in the pulse waveform of the distributed pulse polarity modulation circuit of a prior art example and an Example. It is a figure which shows the effect of the offset cancellation in the distributed pulse polarity modulation circuit of this invention. It is a figure which shows the modification of the distributed pulse polarity modulation circuit of this invention.

Explanation of symbols

12-1, ..., 12-n Distributed constant line 14-1, ..., 14-n Unit cell 15-1, ..., 15-n Pulse generation circuit (AND circuit)
16-1, ..., 16-n Pulse polarity modulation circuit 17 Offset cancellation circuit

Claims (3)

A distributed pulse polarity modulation circuit in which a plurality of unit cells are connected,
Each unit cell
A pulse generation circuit for generating a unipolar pulse signal;
A pulse polarity modulation circuit that generates a bipolar pulse signal according to data from the pulse signal output by the pulse generation circuit,
The pulse polarity modulation circuit of any one of the plurality of unit cells includes an offset cancellation circuit that cancels the offset of the entire distribution type pulse polarity modulation circuit. .   The distributed pulse polarity modulation circuit according to claim 1, wherein the offset cancel circuit is provided in a pulse polarity modulation circuit of a unit cell in a final stage. A differential clock signal supply unit for supplying a differential clock signal to the pulse generation circuit of each unit cell;
The distributed pulse polarity modulation circuit according to claim 1, wherein the differential clock signal supply unit includes a delay circuit that delays one of the differential clock signals.

Images