JP2008205341A - Wafer, semiconductor device and analysis method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a desired cross-section by means of FIB(Focused Ion Beam) processing. <P>SOLUTION: Two or more markers 16, together with a lower layer wiring 13, an upper wiring 14 and a via 15, are formed with a predetermined topography to the via 15 in an analysis region 10. The markers 16 are so formed that its appearance in cross section differs according to the distance between the cross section and the via 15, when the cross-section in the direction F of the FIB processing is formed in the analysis region 10. From the difference in appearance of the markers 16 at FIB processing, the formed cross section and the distance between the formed cross-section and the via 15 can be distinguished, and based on the distinction result, the desired cross section with precision can be obtained easily. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wafer, a semiconductor device, and an analysis method, and more particularly, to a wafer and a semiconductor device provided with an analysis pattern, and an analysis method for such a wafer or semiconductor device.

In the development and manufacturing stages of semiconductor devices, various inspections and analyzes are performed for the purpose of evaluating the performance of semiconductor devices and elucidating the causes of defects.
For example, multi-layer wiring is widely used in current semiconductor devices, but in order to investigate the presence or absence of embedding defects in vias connecting between upper and lower layer wirings, resistance measurement between upper and lower wirings via Then, a cross-sectional analysis is performed in which a cross section of the via portion is observed with an electron microscope such as a TEM (Transmission Electron Microscope) or an SEM (Scanning Electron Microscope). In particular, the following samples as shown in FIGS. 11 and 12 are often used for the resistance measurement and the cross-sectional analysis of the via portion.

11 is a schematic plan view of a sample, and FIG. 12 is a schematic cross-sectional view taken along the line XX of FIG. In FIG. 11, the interlayer insulating film shown in FIG. 12 is not shown.
The samples shown in FIGS. 11 and 12 are samples used in a so-called four-terminal measurement method, and a plane L-shaped lower layer wiring 102 and an upper layer wiring 103 are formed in an interlayer insulating film 101 formed on a substrate 100. The bent portions are connected by vias 104. Pads 105 a and 105 b exposed from the interlayer insulating film 101 are connected to both end portions of the lower layer wiring 102 through a plurality of vias 106, and both end portions of the upper layer wiring 103 are connected to the both end portions from the interlayer insulating film 101. The exposed pads 103a and 103b are formed. A voltage is applied between one pad 103b on the upper layer wiring 103 side of such a sample and one pad 105a on the lower layer wiring 102 side, so The current flowing between one pad 103a and the other pad 105b on the lower wiring 102 side is measured, and the resistance (contact resistance) of the via 104 portion between the upper and lower wirings 103, 102 is measured.

  Further, when there is a problem in the resistance of the via 104 part, a cross section of this sample is formed in order from one end toward the via 104 part using, for example, a focused ion beam (FIB). Then, the section of the via 104 as shown in FIG. 12 may be obtained and analyzed. Since this sample has one via 104 to be analyzed, there is an advantage that its position can be easily specified and its cross section can be easily obtained.

Conventionally, when performing such an analysis, in a semiconductor device in which the same pattern such as a CMP (Chemical Mechanical Polishing) dummy pattern is repeatedly arranged on the uppermost layer, the uppermost layer is viewed from a plane. In order to make it easier to find a specific pattern position at the time, a method of forming a reference pattern at a predetermined position on the uppermost layer has been proposed (for example, see Patent Document 1).
JP 2005-51230 A

However, with the miniaturization of semiconductor devices, the following problems may occur when performing cross-sectional analysis.
For example, when the cross-sectional analysis is performed on the via portion between the upper and lower wirings as described above, the following problem may occur. That is, with the miniaturization of the semiconductor device, the wiring width is reduced and the via diameter is also reduced. Usually, when performing a cross-sectional analysis of a via portion, a cross-section is sequentially formed using FIB from one end of the object toward the via portion. However, when the via diameter is reduced, it is difficult to complete such FIB processing at the via portion.

  For example, if the interval of FIB processing is wide, the portion where such a small via is formed may pass between the FIB processing performed first and the FIB processing performed next. Also, the FIB processing interval can be narrowed near the via portion, but in that case, it takes a longer time to obtain a cross section of the via portion. Furthermore, even if the cross section of the via portion is obtained by FIB processing, it is the cross section of the via portion, for example, the cross section of the end portion close to the side surface of the via, or the cross section of the central portion, Such a situation cannot be clearly identified.

  Here, the via portion between the upper and lower wirings has been described as an example. However, the above-described problem that it is difficult to efficiently obtain a desired cross section is not limited to such a via portion, but other patterns. However, when trying to perform the cross-sectional analysis, it can occur in the same way.

  In order to develop and manufacture highly reliable fine semiconductor devices, it is possible to perform appropriate performance evaluation on the wafer on which the semiconductor device is formed or the semiconductor device itself, and to easily perform cross-sectional analysis at a predetermined position. The importance of being able to do it accurately increases.

The present invention has been made in view of such a point, and an object thereof is to provide a wafer and a semiconductor device capable of easily and accurately performing a cross-sectional analysis.
Another object of the present invention is to provide a method for analyzing the cross section of such a wafer or semiconductor device.

  In the present invention, in order to solve the above-described problem, a pattern formed in an insulating film, and a pattern formed in the insulating film together with the pattern, and a cross section is formed with respect to the insulating film on which the pattern is formed And a marker having a different appearance in the cross section depending on the positional relationship between the cross section and the pattern.

  According to such a wafer, the pattern and the marker are formed in the insulating film, and when the cross section is formed, the positional relationship between the cross section and the pattern is determined by the appearance of the marker in the cross section.

  In the present invention, in order to solve the above-mentioned problem, a pattern formed in an insulating film, and a cross-section is formed in the insulating film together with the pattern, and the insulating film on which the pattern is formed. Then, there is provided a semiconductor device characterized by having a marker whose appearance in the cross section differs depending on the positional relationship between the cross section and the pattern.

According to such a semiconductor device, the positional relationship between the cross section and the pattern is determined based on the appearance of the marker in the formed cross section.
According to the present invention, in order to solve the above problems, in the method for analyzing a cross section, an analysis region in which a pattern and a marker are formed in an insulating film is formed, and a cross section is formed with respect to the formed analysis region. And determining the positional relationship between the cross-section and the pattern based on the appearance of the marker in the formed cross-section, and analyzing the cross-section when the positional relationship is determined to be a predetermined positional relationship. A featured analysis method is provided.

  According to such an analysis method, the positional relationship between the cross section and the pattern is determined based on the appearance of the marker in the formed cross section, and a predetermined cross section is analyzed based on the positional relationship.

  In the present invention, a pattern and a marker are formed in the insulating film, and the positional relationship between the cross section and the pattern can be determined from the difference in the appearance of the marker in the cross section when the cross section is formed. This makes it possible to easily obtain a desired cross section when forming the cross section, and to analyze the desired cross section with high accuracy.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Here, an explanation will be given focusing on an analysis region provided with a pattern for analysis and a marker provided on a wafer or a semiconductor device.

First, the first embodiment will be described.
FIG. 1 is a schematic plan view of an analysis region according to the first embodiment. 2 is a schematic cross-sectional view of the analysis region of the first embodiment, (A) is a schematic cross-sectional view of P1-P1 in FIG. 1, (B) is a schematic cross-sectional view of P2-P2 in FIG. (C) is a P3-P3 cross-sectional schematic diagram of FIG. 1, (D) is a P4-P4 cross-sectional schematic diagram of FIG. 1, and (E) is a P5-P5 cross-sectional schematic diagram of FIG. In FIG. 1, the interlayer insulating film shown in FIG. 2 is not shown.

The analysis region 10 of the first embodiment has a structure that can perform resistance measurement by a four-terminal measurement method.
In the analysis region 10, for example, as shown in FIG. 2E, an interlayer insulating film 12 is formed on a substrate 11, for example, and a lower layer wiring 13 and an upper layer wiring 14 are formed in the interlayer insulating film 12. Has been. As shown in FIG. 1, the lower layer wiring 13 and the upper layer wiring 14 are formed in a planar L shape, and their bent portions are connected by vias 15. By applying a voltage between one end side of the upper layer wiring 14 and one end side of the lower layer wiring 13 and measuring the current flowing between the other end side of the upper layer wiring 14 and the other end side of the lower layer wiring 13, 15 contact resistances can be measured.

  In the analysis region 10 having such a configuration, a plurality of markers 16 are further formed in the interlayer insulating film 12. Here, a total of six markers 16a, 16b, 16c, 16d, 16e, and 16f are formed.

  Each of the markers 16a, 16b, 16c, 16d, 16e, and 16f is formed in a line shape extending in the FIB processing direction F of the analysis region 10, and the marker 16a is on a straight line that is orthogonal to the FIB processing direction F when viewed from the plane. , 16b, 16c, 16d, 16e, and 16f and the center of the via 15 are disposed. In the layer where the lower layer wiring 13 is formed, three markers 16a, 16b and 16c are arranged in parallel, and in the layer where the upper layer wiring 14 is formed, three markers 16d, 16e and 16f. Are arranged in parallel. The markers 16 a, 16 b, 16 c and the markers 16 d, 16 e, 16 f formed in each of these layers are formed with different lengths with their centers aligned at predetermined positions, and become longer as they move away from the via 15.

  The lower layer wiring 13, the upper layer wiring 14, and the via 15 are formed in the interlayer insulating film 12 by using a damascene process, or by using a process such as deposition of a conductive material, patterning, and filling of a via hole. Can do. The markers 16a, 16b, and 16c can be formed of the same material as the lower layer wiring 13 simultaneously with the lower layer wiring 13, for example. The markers 16d, 16e, and 16f can be formed simultaneously with the upper layer wiring 14, for example. Can be made of the same material.

Subsequently, the FIB processing of the analysis region 10 will be described.
The FIB processing of the analysis region 10 is a cross-sectional analysis of the via 15 portion using a TEM or SEM, for example, when the contact resistance of the via 15 is high, or when the resistance measurement result suspects that the via 15 is embedded poorly. Done to implement.

  When the cross section is formed toward the via 15 with respect to the analysis region 10 according to the FIB processing direction F shown in FIG. 1, at the initial stage of the FIB processing, as shown in FIG. A portion extending in the FIB processing direction F appears in the plane L-shaped lower layer wiring 13.

  When the cross-section formation by FIB processing is further advanced from the position of FIG. 2A toward the via 15, the cross-section shows the most from the via 15 in addition to the lower layer wiring 13 as shown in FIG. The longest lower layer side marker 16c and the upper layer side marker 16f which are far away from each other appear.

  When cross-section formation by FIB processing further proceeds from the position of FIG. 2B, the cross-section is closer to the via 15 in addition to the lower layer wiring 13 and the markers 16c and 16f, as shown in FIG. A marker 16b on the lower layer side and a marker 16e on the upper layer side having an intermediate length appear.

  Similarly, when cross-section formation by FIB processing further proceeds from the position of FIG. 2C, the cross-section includes, in addition to the lower layer wiring 13 and markers 16b, 16c, 16e, and 16f, as shown in FIG. The lower layer side marker 16a and the upper layer side marker 16d that are closest to and shortest to the via 15 appear.

  When the cross section is formed by FIB processing at the position of the via 15, as shown in FIG. 2E, the cross section includes the lower layer wiring 13, the upper layer wiring 14, the via 15, and all the markers 16a, A state in which 16b, 16c, 16d, 16e, and 16f appear can be obtained.

  As described above, in the analysis region 10, the appearance of the marker 16 appearing on the cross section changes as the cross-section formation by FIB processing proceeds toward the via 15. That is, the appearance of the marker 16 appearing on the cross section differs depending on the positional relationship between the formation cross section and the via 15, and from the state where the marker 16 does not exist on the cross section as shown in FIG. As shown in D), as the cross section approaches the via 15, the inner marker 16 appears from the outside, and the number of markers 16 appearing in the cross section increases.

  Therefore, the cross-section is formed by FIB processing, and from which part of the analysis region 10 the cross-section is currently formed due to the difference in the appearance of the marker 16 as shown in FIGS. Further, it can be easily and accurately determined how much FIB processing is performed to obtain the state shown in FIG.

Next, a second embodiment will be described.
FIG. 3 is a schematic plan view of an analysis region according to the second embodiment. 4 and 5 are cross-sectional schematic views of the analysis region of the second embodiment. FIG. 4A is a schematic cross-sectional view taken along the line Q1-Q1 in FIG. 3, and FIG. 4B is a cross-sectional view in FIG. 4C is a schematic cross-sectional view taken along the line Q3-Q3 in FIG. 3, FIG. 4D is a schematic cross-sectional view taken along the line Q4-Q4 in FIG. 3, and FIG. Q5 cross-sectional schematic diagram, FIG. 5B is a Q6-Q6 cross-sectional schematic diagram of FIG. 3, FIG. 5C is a Q7-Q7 cross-sectional schematic diagram of FIG. 3, and FIG. 5D is a Q8-Q8 cross-sectional diagram of FIG. It is a schematic diagram. In FIG. 3, illustration of the interlayer insulating film shown in FIGS. 4 and 5 is omitted.

  As shown in FIGS. 3 to 5, in the analysis region 20 of the second embodiment, the interlayer insulating film 22 formed on the substrate 21, for example, as in the analysis region 10 of the first embodiment. Inside, a lower-layer wiring 23 and an upper-layer wiring 24 having a planar L shape are formed, and bent portions thereof are connected by vias 25. Further, in the analysis region 20, a plurality of linear markers 26 extending in the FIB processing direction F of the analysis region 20 are formed in the interlayer insulating film 22. Five markers 26a, 26b, 26c, 26d, and 26e are arranged in parallel in the layer in which the lower layer wiring 23 is formed, and five markers 26f are disposed in the layer in which the upper layer wiring 24 is formed. , 26g, 26h, 26i, and 26j are arranged in parallel.

  As shown in FIG. 3, the lower layer side and upper layer side markers 26a, 26b, 26c, 26d, 26e, 26f, 26g, 26h, 26i, and 26j are all formed to have the same length. Also, the lower layer side markers 26a, 26b, 26c, 26d, and 26e are arranged closer to the front side as viewed in the FIB processing direction F as the one closer to the via 25, and the upper layer side markers 26f, 26g, 26h, and 26i. , 26j are arranged closer to the rear as viewed in the FIB processing direction F as the one closer to the via 25.

  On the lower layer side, as shown in FIG. 3, the marker 26a closest to the via 25 has an end surface (an end surface on the rear side in the FIB processing direction F) as viewed from the plane, and a side surface (FIB processing) of the via 25. It is arranged in accordance with the position of the front side surface when viewed in the direction F. The adjacent marker 26b is arranged so that its end surface (the end surface on the rear side when viewed in the FIB processing direction F) is aligned with the center position of the via 25 when viewed from the plane. Furthermore, the marker 26c has an end surface (an end surface on the rear side when viewed in the FIB processing direction F), as viewed from the plane, aligned with a position of a side surface of the via 25 (a rear side surface when viewed in the FIB processing direction F). Has been placed. Further, the marker 26d has an end surface (an end surface on the rear side when viewed in the FIB processing direction F) as viewed from the plane, and a side surface of the lower layer wiring 23 and the upper layer wiring 24 (a side surface on the rear side when viewed in the FIB processing direction F). It is arranged according to the position. The marker 26 e farthest from the via 25 is arranged so that its end surface (the end surface on the rear side when viewed in the FIB processing direction F) is behind the upper layer wiring 24 when viewed from the plane.

  The same applies to the upper layer side. As shown in FIG. 3, the end surfaces on the front side of the markers 26f, 26g, and 26h as viewed in the FIB processing direction F are viewed in the FIB processing direction F of the via 25 as viewed from the plane. The rear side surface as viewed, the center of the via 25, and the position of the side surface on the near side when viewed in the FIB processing direction F of the via 25 are arranged. Further, the end face on the near side when viewed in the FIB processing direction F of the marker 26i is arranged in accordance with the position of the side surface on the near side when viewed in the FIB processing direction F of the lower layer wiring 23 and the upper layer wiring 24 when viewed from the plane. In addition, the end face on the near side as viewed in the FIB processing direction F of the marker 26j is arranged so as to come closer to the lower layer wiring 23.

  For the markers 26a, 26b, 26c, 26d, 26e, 26f, 26g, 26h, 26i, and 26j arranged in this way, for the lower markers 26a, 26b, 26c, 26d, and 26e, for example, At the same time, it is possible to form the same material as that of the lower layer wiring 23. For example, the upper layer side markers 26f, 26g, 26h, 26i, and 26j are formed of the same material as that of the upper layer wiring 24 simultaneously with the upper layer wiring 24. It is possible.

Subsequently, the FIB processing of the analysis region 20 will be described.
For example, if a cross section is formed toward the via 25 with respect to the analysis region 20 in accordance with the FIB processing direction F shown in FIG. 3, the cross section is shown in FIG. A portion extending in the FIB processing direction F of the lower layer wiring 23 appears.

When cross-section formation by FIB processing further proceeds from the position shown in FIG. 4A, a lower layer side marker 26a appears in the cross section as shown in FIG. 4B.
When the cross-section formation by FIB processing is further advanced from the position of FIG. 4B, markers 26b, 26c, and 26d appear in order on the cross-section as shown in FIG. , The lower layer wiring 23 and all the markers 26a, 26b, 26c, 26d, and 26e on the lower layer side appear.

  When cross-section formation by FIB processing proceeds from the position shown in FIG. 4C, the cross-section includes the lower-layer wiring 23 and all the lower-layer-side markers 26a, 26b, 26c, 26d, as shown in FIG. 26e and an upper layer marker 26j farthest from the via 25 appear.

  When cross-section formation by FIB processing proceeds from the position of FIG. 4D, the cross-section further includes a direction orthogonal to the FIB processing direction F of the lower layer wiring 23 and the upper layer wiring 24 as shown in FIG. And an upper layer side marker 26i appear.

  When cross-section formation by FIB processing proceeds from the position of FIG. 5A, the cross-section further includes a side surface of the via 25 (a front side surface as viewed in the FIB processing direction F) as shown in FIG. 5B. Then, the upper layer side marker 26h appears, and at the same time, the lower layer side marker 26a closest to the via 25 disappears.

  Similarly, when the cross-section formation by FIB processing proceeds from the position in FIG. 5B, the center of the via 25 and the marker 26g on the upper layer side appear in the cross-section as shown in FIG. 5C. At the same time, the lower marker 26b closest to the via 25 disappears.

  When cross-section formation by FIB processing proceeds from the position of FIG. 5C, the cross-section further includes the side surface of the via 25 (the side surface on the rear side as viewed in the FIB processing direction F) as shown in FIG. 5D. Then, the upper layer side marker 26f closest to the via 25 appears, and at the same time, the lower layer side marker 26c disappears.

  As described above, in the analysis region 20, as the cross-section formation by FIB processing proceeds toward the via 25, until the cross-section reaches the via 25, FIGS. 4A to 4D and FIG. As shown, the lower layer side markers 26 appear to gradually increase in number from the inside to the outside, and the upper layer side markers 26 appear to gradually increase in number from the outside to the inside from a certain stage. . After reaching the via 25 in the cross section, as shown in FIGS. 5B to 5D, the upper layer side markers 26 appear to gradually increase in number from the outside to the inside, and the lower layer The marker 26 on the side gradually disappears from the inner one.

  As described above, each marker 26 in the analysis region 20 is arranged at a predetermined position with respect to the lower layer wiring 23, the upper layer wiring 24, and the via 25. Therefore, the cross-section is formed by FIB processing, and it is easy to determine which section of the analysis region 20 is being cross-sectioned from the difference in the appearance of the marker 26 as shown in FIGS. It can be determined with high accuracy.

  Among the markers 26 in the analysis region 20, the lower-layer markers 26 a, 26 b, 26 c and the upper-layer markers 26 f, 26 g, 26 h are arranged in such a manner that their end surfaces are aligned with the side surfaces and the center of the via 25. ing.

  Therefore, as shown in FIG. 5B, when the upper layer side marker 26h appears and the marker 26g does not appear, it can be determined that the side surface on the near side of the via 25 appears in the cross section. it can. As shown in FIG. 5C, when the lower layer side marker 26b disappears and both the lower layer side marker 26c and the upper layer side marker 26g appear, the center of the via 25 appears in the cross section. Can be determined. Further, as shown in FIG. 5D, when the lower marker 26c disappears and the upper marker 26f appears, it is determined that the side surface on the rear side of the via 25 appears in the cross section. Can do.

  Further, as shown in FIGS. 5B and 5D, even when the shape of the via 25 in the cross section looks the same, the cross section is in front of the center of the via 25 because of the appearance of the marker 26 in the cross section. It is possible to determine whether it is the rear side or the rear side. Therefore, when attempting to obtain a cross section in which the central portion of the via 25 exists by FIB processing, it is possible to determine whether the FIB processing is insufficient or excessive from the appearance of the marker 26 on the cross section. .

  In the above description of the second embodiment, the case where the FIB processing is performed in the FIB processing direction F shown in FIG. 3 has been described as an example. However, the FIB processing is performed in the opposite FIB processing direction G. In any case, the lower layer side and upper layer side markers 26 appear in the same manner as described above, and thus the same effect as described above can be obtained.

Next, a third embodiment will be described.
FIG. 6 is a schematic plan view of an analysis region according to the third embodiment. 7 is a schematic cross-sectional view of the analysis region of the third embodiment, in which (A) is a schematic cross-sectional view of R1-R1 in FIG. 6, and (B) is a schematic cross-sectional view of R2-R2 in FIG. 6C is an R3-R3 cross-sectional schematic diagram of FIG. 6, FIG. 6D is an R4-R4 cross-sectional schematic diagram of FIG. 6, and FIG. 6E is an R5-R5 cross-sectional schematic diagram of FIG. In FIG. 6, illustration of the interlayer insulating film shown in FIG. 7 is omitted. In FIGS. 6 and 7, the same elements as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

  As shown in FIGS. 6 and 7, the analysis region 30 of the third embodiment is that the marker 36 is further formed in addition to the marker 16, and therefore the analysis region 10 of the first embodiment. Is different. In the analysis region 30, markers 36a, 36b, and 36c are formed along with the markers 16a, 16b, and 16c on the lower layer side, and markers 36d, 36e, and 36f are formed along with the markers 16d, 16e, and 16f on the upper layer side.

  As shown in FIG. 6, the marker 36 has the same arrangement and configuration as the marker 16. That is, each of the markers 36a, 36b, 36c, 36d, 36e, and 36f is formed in a line shape extending in a direction orthogonal to the FIB processing direction F of the analysis region 30, and extends in the FIB processing direction F when viewed from the plane. The centers of the markers 36a, 36b, 36c, 36d, 36e, and 36f and the center of the via 15 are arranged on the straight line. The markers 36 a, 36 b, 36 c and the markers 36 d, 36 e, 36 f are centered at predetermined positions, are formed with different lengths, and become longer as they move away from the via 15.

  The markers 36a, 36b, and 36c can be formed of the same material simultaneously with the lower layer wiring 13 and the markers 16a, 16b, and 16c, for example, and the markers 36d, 36e, and 36f are, for example, the upper layer wiring 14 and the markers 16d, 16e, and The same material can be formed simultaneously with 16f.

Subsequently, the FIB processing of the analysis region 30 will be described.
In order to perform a cross-sectional analysis of the via 15 portion, for example, when a cross-section is formed toward the via 15 with respect to the analysis region 30 in accordance with the FIB processing direction F shown in FIG. As shown in FIG. 7A, the lower layer wiring 13 and the upper layer side marker 36e appear.

  When the cross-section formation by FIB processing is advanced from the position of FIG. 7A, the cross-section includes the lower layer wiring 13, the lower layer side marker 16c, and the upper layer side marker 16f as shown in FIG. 7B. , 36d appear.

  When cross-section formation by FIB processing proceeds from the position in FIG. 7B, a lower layer side marker 16b and an upper layer side marker 16e appear on the cross section, as shown in FIG. 7C.

  When cross-section formation by FIB processing proceeds from the position of FIG. 7C, as shown in FIG. 7D, a lower layer side marker 16a and an upper layer side marker 16d appear on the cross section, and at the same time, the upper layer The side marker 36d disappears.

  When the cross section is formed by FIB processing at the position of the via 15, as shown in FIG. 7E, the cross section includes the lower layer wiring 13, the upper layer wiring 14, the via 15, and the markers 16a, 16b, 16c. 16d, 16e, and 16f appear.

  As described above, in the analysis region 30, the position of the formation cross section is determined from the difference in appearance of the markers 16 and 36 as shown in FIGS. 7A to 7D, and is shown in FIG. Such a cross section can be obtained easily and accurately.

  Further, markers 16 and 36 are arranged in the analysis region 30 in the arrangement relationship as shown in FIG. Therefore, when the FIB processing is performed in the FIB processing directions G, H, and I, the lower layer side and upper layer markers 16 and 36 appear in the same manner as in the FIB processing direction F described above. . Therefore, even if FIB processing is performed in any of the FIB processing directions F, G, H, and I, the position of the formed cross section can be determined, and a desired cross section can be obtained easily and accurately.

Next, a fourth embodiment will be described.
FIG. 8 is a schematic plan view of the analysis region of the fourth embodiment, and FIG. 9 is a schematic cross-sectional view taken along the line S-S in FIG. In FIG. 8, the interlayer insulating film shown in FIG. 9 is not shown.

  As shown in FIGS. 8 and 9, the analysis region 40 of the fourth embodiment includes, for example, a line-like lower layer wiring 43 and an upper layer extending in the same direction in an interlayer insulating film 42 formed on a substrate 41. Wirings 44a and 44b are formed. The upper wirings 44a and 44b are connected to the lower wiring 43 by vias 45a and 45b, respectively. Further, the analysis region 40 has a line-like shape extending in a direction orthogonal to the lower layer wiring 43 and the upper layer wirings 44a and 44b in the same layer as the layer in which the upper layer wirings 44a and 44b are formed in the interlayer insulating film 42. A marker 46 is formed. Here, a configuration in which three markers 46a, 46b, and 46c are formed is shown.

  As shown in FIG. 8, the markers 46a, 46b, and 46c are arranged at predetermined positions, respectively. That is, when viewed from the plane, the marker 46a has an end surface (an end surface on the near side when viewed in the FIB processing direction F) at a position of a side surface (a side surface on the near side when viewed in the FIB processing direction F) of the vias 45a and 45b. Are arranged together. In addition, the end face of the marker 46b (the end face on the near side when viewed in the FIB processing direction F) when viewed from the plane is arranged in accordance with the center position of the vias 45a and 45b. Further, when viewed from the plane, the marker 46c has an end surface (an end surface on the near side as viewed in the FIB processing direction F) at a position of a side surface of the vias 45a and 45b (a rear side surface when viewed in the FIB processing direction F). Are arranged together.

  In order to perform a cross-sectional analysis of the vias 45a and 45b in such an analysis region 40, when the cross-section is formed in accordance with the FIB processing direction F shown in FIG. 8, the FIB processing is performed on the front side of the vias 45a and 45b. When the side surface is reached, the marker 46a appears. Further, when the cross-section formation by the FIB processing proceeds and the FIB processing reaches the center of the vias 45a and 45b, in addition to the marker 46a, the adjacent marker 46b appears as shown in FIG. When the FIB processing reaches the rear side surface of the vias 45a and 45b, all the markers 46a, 46b and 46c appear.

In the analysis region 40, the position of the formed cross section during FIB processing can be determined from the difference in the appearance of the marker 46, and a desired cross section can be obtained easily and accurately.
Next, a fifth embodiment will be described.

FIG. 10 is a schematic plan view of an analysis region according to the fifth embodiment. In FIG. 10, the same elements as those shown in FIGS. 8 and 9 are denoted by the same reference numerals.
The analysis region 50 of the fifth embodiment shown in FIG. 10 is adjacent to the lower layer wiring 43, the upper layer wirings 44a and 44b, and the vias 45a and 45b described in the fourth embodiment, and is similar to them. The lower layer wiring 53, the upper layer wirings 54a and 54b, and the vias 55a and 55b having the structure are formed. And it has the structure by which the linear marker 56 extended in the direction orthogonal to them was formed in the same layer as the layer in which upper wiring 44a, 44b, 54a, 54b is formed. Here, a configuration in which three markers 56a, 56b, and 56c are formed is shown.

  As shown in FIG. 10, the marker 56a has one end surface (an end surface on the near side when viewed in the FIB processing direction F) on the side surface (the front side when viewed in the FIB processing direction F) of the vias 45a and 45b when viewed from the plane. The other end surface (the end surface on the rear side when viewed in the FIB processing direction F) is the side surface (the side surface on the near side when viewed in the FIB processing direction F). It is arranged according to the position. Further, the marker 56b has one end surface (an end surface on the near side when viewed in the FIB processing direction F) as viewed from the plane aligned with the center position of the vias 45a and 45b, and the other end surface (FIB processing). The end face on the rear side when viewed in the direction F) is arranged at the center position of the vias 55a and 55b. The marker 56c has one end face (an end face on the near side in the FIB processing direction F) aligned with the position of the side surface of the vias 45a and 45b (the rear side face in the FIB processing direction F) when viewed from the plane. The other end surface (the end surface on the rear side when viewed in the FIB processing direction F) is disposed in accordance with the position of the side surface (the side surface on the rear side when viewed in the FIB processing direction F) of the vias 55a and 55b. .

  Thus, in the analysis region 50, the markers 56a, 56b, and 56c are formed so as to straddle two adjacent wiring connection patterns. When the cross section is formed in accordance with the FIB processing direction F shown in FIG. 10, the FIB processing is performed on the front side surface of the vias 45a and 45b in the same manner as the markers 46a, 46b, and 46c of the fourth embodiment. Markers 56a, 56b, and 56c appear in this order in the cross section as the center and rear side surfaces are advanced.

  Further, in the analysis region 50, when the FIB processing is performed in the opposite FIB processing direction G, the FIB processing is viewed in the FIB processing direction G, and the FIB processing is performed on the side surface, the center, Markers 56c, 56b, and 56a appear in this order in the cross section as the rear side surface is advanced.

  In the analysis region 50, regardless of the FIB machining direction F or G, the position of the formed cross section during the FIB machining is determined from the difference in the appearance of the marker 56, and the desired cross section can be easily formed. And can be obtained with high accuracy.

  As described above in the first to fifth embodiments, according to the analysis regions 10, 20, 30, 40, 50, the difference in appearance of the markers 16, 26, 36, 46, 56 is as follows. Therefore, it is possible to easily and accurately obtain a desired cross section to be analyzed by determining the position of the formed cross section during the FIB processing.

  The analysis regions 10, 20, 30, 40, and 50 can be formed on the wafer on which the chip is formed or on the chip itself. For example, on the wafer, a TEG (Test Element Group) such as a resistor or a capacitor can be formed in a scribe line region where the formed chip is diced. Similarly, the analysis regions 10, 20, 30, 40, and 50 can be formed in the scribe line region as one of such TEGs. Further, the analysis regions 10, 20, 30, 40, and 50 can be formed on all or some of the chips formed on the wafer, for example, in the multilayer wiring of the chip. Regardless of whether it is formed on a wafer or a chip, the analysis regions 10, 20, 30, 40, and 50 can be formed on the wafer or chip in parallel with the process of forming the chip. The substrates 11, 21, 41 in the analysis regions 10, 20, 30, 40, 50 may be replaced with another interlayer insulating film or the like according to the applied wafer or chip form.

  Further, the shape, number, arrangement, etc. of the markers 16, 26, 36, 46, 56 in the above description are merely examples, and how they appear in accordance with the progress of FIB processing until a desired cross section to be analyzed is obtained. Is not limited to the above example, as long as the positional relationship between the formed cross section and the desired cross section can be determined.

  In the above description, the case where the cross-sectional analysis of the via 15 or the like is performed is described as an example. However, the target pattern of the cross-sectional analysis is, of course, not limited to such a via pattern. The present invention can be similarly applied to cross-sectional analysis of various other patterns.

  Of course, in addition to being formed on a wafer or chip, each structure composed of the analysis regions 10, 20, 30, 40, and 50 may be formed and subjected to inspection, cross-sectional analysis, or the like.

(Appendix 1) A pattern formed in the insulating film;
Markers that are formed in the insulating film together with the pattern, and that appear differently in the cross section depending on the positional relationship between the cross section and the pattern when the cross section is formed with respect to the insulating film on which the pattern is formed,
A wafer characterized by comprising:

  (Supplementary note 2) The wafer according to supplementary note 1, wherein the marker is formed so that a position or a number of the marker appearing on the cross section differs depending on a positional relationship between the cross section and the pattern.

  (Additional remark 3) The said marker is formed so that it can discriminate | determine which part of the said pattern exists in the said cross section by the appearance in the formed said cross section. 2. The wafer according to 2.

  (Additional remark 4) The said marker is formed so that it can be discriminate | determined whether the center part of the said pattern exists in the said cross section by the appearance in the formed said cross section. Wafers.

  (Additional remark 5) The said marker is formed so that it can be discriminate | determined whether the edge part of the said pattern exists in the said cross section by the appearance in the formed said cross section. Additional remark 3 characterized by the above-mentioned. Wafers.

  (Additional remark 6) The said pattern and the said marker are formed in the scribe line area | region where the dicing of the formed semiconductor device is performed, The wafer in any one of Additional remark 1 to 5 characterized by the above-mentioned.

(Supplementary note 7) The wafer according to any one of supplementary notes 1 to 6, wherein the pattern is a via.
(Appendix 8) A pattern formed in the insulating film;
Markers that are formed in the insulating film together with the pattern, and that appear differently in the cross section depending on the positional relationship between the cross section and the pattern when the cross section is formed with respect to the insulating film on which the pattern is formed,
A semiconductor device comprising:

  (Supplementary note 9) The semiconductor device according to supplementary note 8, wherein the marker is formed so that a position or a number of the marker appearing in the cross section differs depending on a positional relationship between the cross section and the pattern.

  (Additional remark 10) The said marker is formed so that it can discriminate | determine which part of the said pattern exists in the said cross section by the appearance in the formed said cross section. 9. The semiconductor device according to 9.

  (Additional remark 11) The said marker is formed so that it can be discriminate | determined whether the center part of the said pattern exists in the said cross section by the appearance in the formed said cross section. Semiconductor device.

  (Additional remark 12) The said marker is formed so that it can be discriminate | determined whether the edge part of the said pattern exists in the said cross section by the appearance in the formed said cross section. Semiconductor device.

(Supplementary note 13) The semiconductor device according to any one of Supplementary notes 8 to 12, wherein the pattern is a via.
(Supplementary note 14) In the analysis method of the cross section,
Form an analysis area where patterns and markers are formed in the insulating film,
Forming a cross section with respect to the formed analysis region;
Determine the positional relationship between the cross section and the pattern by the appearance of the marker in the formed cross section,
An analysis method, comprising: analyzing the cross section when the positional relationship is determined to be a predetermined positional relationship.

(Supplementary Note 15) When determining the positional relationship between the cross section and the pattern according to the appearance of the marker in the formed cross section,
The analysis method according to claim 14, wherein the positional relationship between the cross section and the pattern is determined based on the number of the markers appearing in the cross section.

(Supplementary Note 16) When determining the positional relationship between the cross section and the pattern according to the appearance of the marker in the formed cross section,
16. The analysis method according to appendix 14 or 15, wherein which part of the pattern is present in the cross section is determined based on the appearance of the marker in the formed cross section.

  (Supplementary note 17) The analysis method according to supplementary note 16, wherein whether or not a central portion of the pattern exists in the cross section is determined based on how the marker appears in the formed cross section.

  (Additional remark 18) The analysis method of additional remark 16 characterized by determining whether the edge part of the said pattern exists in the said cross section by the appearance of the said marker in the formed said cross section.

It is a plane schematic diagram of the analysis field of a 1st embodiment. It is a cross-sectional schematic diagram of the analysis region of the first embodiment, (A) is a schematic cross-sectional view of P1-P1 in FIG. 1, (B) is a schematic cross-sectional view of P2-P2 in FIG. 1, (C) is a diagram 1 is a P3-P3 cross-sectional schematic diagram of FIG. 1, (D) is a P4-P4 cross-sectional schematic diagram of FIG. 1, and (E) is a P5-P5 cross-sectional schematic diagram of FIG. It is a plane schematic diagram of the analysis area | region of 2nd Embodiment. FIGS. 3A and 3B are schematic cross-sectional views (part 1) of the analysis region of the second embodiment, where FIG. 3A is a schematic cross-sectional view taken along the line Q1-Q1 in FIG. (C) is a Q3-Q3 cross-sectional schematic diagram of FIG. 3, and (D) is a Q4-Q4 cross-sectional schematic diagram of FIG. FIGS. 3A and 3B are schematic cross-sectional views (part 2) of the analysis region of the second embodiment, in which FIG. 3A is a schematic cross-sectional view taken along Q5-Q5 in FIG. 3, and FIG. C) is a schematic cross-sectional view taken along Q7-Q7 in FIG. 3, and (D) is a schematic cross-sectional view taken along Q8-Q8 in FIG. It is a plane schematic diagram of the analysis area | region of 3rd Embodiment. It is a cross-sectional schematic diagram of the analysis region of the third embodiment, (A) is a schematic cross-sectional view of R1-R1 in FIG. 6, (B) is a schematic cross-sectional view of R2-R2 in FIG. 6, (C) is a diagram 6 is a schematic cross-sectional view of R3-R3 in FIG. 6, (D) is a schematic cross-sectional view of R4-R4 in FIG. 6, and (E) is a schematic cross-sectional view of R5-R5 in FIG. It is a plane schematic diagram of the analysis area | region of 4th Embodiment. It is a SS cross-sectional schematic diagram of FIG. It is a plane schematic diagram of the analysis area | region of 5th Embodiment. It is a plane schematic diagram of a sample. It is XX cross-sectional schematic diagram of FIG.

Explanation of symbols

10, 20, 30, 40, 50 Analysis area 11, 21, 41 Substrate 12, 22, 42 Interlayer insulating film 13, 23, 43, 53 Lower layer wiring 14, 24, 44a, 44b, 54a, 54b Upper layer wiring 15, 25 45a, 45b, 55a, 55b Via 16, 16a, 16b, 16c, 16d, 16e, 16f, 26, 26a, 26b, 26c, 26d, 26e, 26f, 26g, 26h, 26i, 26j, 36, 36a, 36b , 36c, 36d, 36e, 36f, 46, 46a, 46b, 46c, 56, 56a, 56b, 56c Marker

Claims (7)

A pattern formed in the insulating film;
Markers that are formed in the insulating film together with the pattern, and that appear differently in the cross section depending on the positional relationship between the cross section and the pattern when the cross section is formed with respect to the insulating film on which the pattern is formed,
A wafer characterized by comprising:   The wafer according to claim 1, wherein the marker is formed so that a position or a number of the markers appearing on the cross section differs depending on a positional relationship between the cross section and the pattern.   3. The marker according to claim 1, wherein the marker is formed so as to be able to determine which part of the pattern exists in the cross section based on how the marker appears in the formed cross section. Wafers.   The wafer according to claim 3, wherein the marker is formed so as to be able to determine whether or not a central portion of the pattern exists in the cross section based on how the marker appears in the formed cross section.   5. The wafer according to claim 1, wherein the pattern and the marker are formed in a scribe line region where dicing of the formed semiconductor device is performed. A pattern formed in the insulating film;
Markers that are formed in the insulating film together with the pattern, and that appear differently in the cross section depending on the positional relationship between the cross section and the pattern when the cross section is formed with respect to the insulating film on which the pattern is formed,
A semiconductor device comprising: In the analysis method of the cross section,
Form an analysis area where patterns and markers are formed in the insulating film,
Forming a cross section with respect to the formed analysis region;
Determine the positional relationship between the cross section and the pattern by the appearance of the marker in the formed cross section,
An analysis method, comprising: analyzing the cross section when the positional relationship is determined to be a predetermined positional relationship.

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