JP2013038271A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can simply evaluate an influence on a wiring structure exerted by dishing and erosion occurring in groove wiring.SOLUTION: A TEG 200 is provided in a multi-wiring layer. Further, the TEG 200 comprises lower groove wiring 1 buried in a first insulation film in the multi-wiring layer. The TEG 200 comprises: a lower conductor pattern 1 buried in a surface layer of a first insulation film 80 (not shown); a second insulation film 20 formed on the first insulation film 80 and on the lower conductor pattern 1; and a plurality of upper conductor patterns 10 which are opposed to the same lower conductor pattern 1. Note that, the upper conductor pattern 10 may be buried in a surface layer of the second insulation film 20 and may be formed on the second insulation film 20.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In an LSI (Large Scale Integration), Cu wiring is increasingly used for wiring of a multilayer wiring layer. The Cu wiring is embedded in a groove formed in the insulating film by using a CMP (Chemical Mechanical Polishing) method.

  Patent Documents 1 and 2 disclose an evaluation substrate or an evaluation method for evaluating CMP conditions for trench wiring in a semiconductor device. In Patent Document 1, the influence of overplating can be evaluated. In this method, a plurality of types of patterns for checking a short circuit between wires in the L / S pattern are formed. Then, the yield of electrical characteristics is evaluated while changing the polishing time under CMP conditions in the over direction. In Patent Document 2, the thickness of an insulating film arranged between two wiring grooves near the center of a TEG (Test Element Group) is optically measured. Thus, the erosion generated in the dense wiring trench is evaluated.

JP 2007-201124 A JP 2000-58611 A

  There is a need for a semiconductor device that can easily evaluate the influence of dishing and erosion generated in the trench wiring on the wiring structure.

The following is a brief description of an outline of typical inventions disclosed in the present application.
A semiconductor device according to a representative embodiment includes a TEG provided in a multilayer wiring layer, and the TEG includes:
A lower conductor pattern embedded in a surface layer of the first insulating film in the multilayer wiring layer;
A second insulating film formed on the first insulating film and on the lower conductor pattern;
A plurality of upper-layer conductor patterns embedded in the surface layer of the second insulating film or formed on the second insulating film, each facing the same lower-layer conductor pattern.

According to another embodiment of the present invention, according to the present invention, a TEG provided in a multilayer wiring layer,
A lower trench wiring embedded in the first insulating film in the multilayer wiring layer;
With
The TEG is
A lower conductor pattern embedded in a surface layer of the first insulating film;
A second insulating film formed on the first insulating film and on the lower conductor pattern;
A plurality of upper layer conductor patterns embedded in the surface layer of the second insulating film or formed on the second insulating film, each facing the same lower layer conductor pattern;
A via located in the second insulating film, provided for each of the plurality of upper layer conductor patterns, and connecting the upper layer conductor pattern to the lower layer conductor pattern;
A semiconductor device is provided.

According to another embodiment of the present invention, the lower conductor pattern embedded in the surface layer of the first insulating film in the multilayer wiring layer,
A second insulating film formed on the first insulating film and on the lower conductor pattern;
A plurality of upper layer conductor patterns embedded in the surface layer of the second insulating film or formed on the second insulating film, each facing the same lower layer conductor pattern;
Including
Each of the upper conductor patterns provides a semiconductor device in which different capacitive elements are formed by the lower conductor pattern and the second insulating film.

According to another embodiment of the present invention, the step of embedding a lower layer conductor pattern located in the scribe line and a lower layer trench wiring located in the chip region in the first insulating film;
Forming an interlayer insulating film on the lower conductor pattern and on the lower groove wiring;
Forming a plurality of upper layer conductor patterns on the interlayer insulating film or in the interlayer insulating film so as to face the lower layer conductor pattern;
Using the lower conductor pattern formed in the scribe line, the interlayer insulating film, and the upper conductor pattern as a TEG, and evaluating the lower groove wiring by inspecting the TEG, to manufacture a semiconductor device A method is provided.

According to another embodiment of the present invention, the step of embedding a lower layer conductor pattern located in the scribe line and a lower layer trench wiring located in the chip region in the first insulating film;
Forming an interlayer insulating film on the lower conductor pattern and on the lower groove wiring;
Providing a plurality of vias in the interlayer insulating film;
Forming a plurality of upper layer conductor patterns connecting the lower layer conductor patterns with the plurality of vias; and
Using the lower conductor pattern formed in the scribe line, the plurality of vias, and the plurality of upper conductor patterns as a TEG, and evaluating the lower groove wiring by inspecting the TEG. A manufacturing method is provided.

  According to the present invention, the distribution of the distance between the upper conductor pattern and the lower trench wiring can be obtained by using the TEG. At this time, the lower layer groove wiring provided in the TEG and the lower layer groove wiring provided in the semiconductor chip are formed at the same time and provided in the same layer. Therefore, by evaluating the TEG, it is possible to know the tendency of the depth of dishing formed in the lower layer trench wiring.

  According to the present invention, it is possible to easily evaluate the influence of dishing and erosion generated in the trench wiring on the wiring structure.

(A) is a figure which shows an example of the wiring evaluation method which concerns on this embodiment, (b) is an enlarged view of A area | region shown to (a). It is sectional drawing of TEG concerning this embodiment. It is a top view of TEG concerning this embodiment. It is sectional drawing for demonstrating the wiring connection of TEG which concerns on this embodiment. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on this embodiment. It is sectional drawing of TEG concerning this embodiment. It is a top view of TEG concerning this embodiment. It is sectional drawing for demonstrating the wiring connection of TEG which concerns on this embodiment. It is sectional drawing of the semiconductor device which concerns on this embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
1A is a diagram illustrating an example of a wiring evaluation method according to the present embodiment, and FIG. 1B is an enlarged view of a region A illustrated in FIG.
As shown in FIG. 1A, the semiconductor wafer is provided with a plurality of chip regions 30. A scribe line 50 is provided between the chip regions 30. The TEG 200 is disposed in the scribe line 50.

  In the semiconductor device according to the present embodiment, the multilayer wiring layer is disposed on the transistor installed on the substrate. In addition, the upper part of the multilayer wiring layer has a plurality of electrode pads (PAD).

  Further, as shown in FIG. 1B, the lower layer trench wiring 2 having the same layer structure as the lower layer conductor pattern 1 is also provided in the chip region 30. The lower layer trench wiring 2 is provided in the same layer as the lower layer conductor pattern 1. Thus, when the electrical characteristics of the TEG 200 are inspected, it can be evaluated whether or not the wiring structure in the lower-layer trench wiring 2 arranged in the chip region 30 is formed normally. Furthermore, the lower conductor pattern 1 preferably has a wiring structure having the same width as the lower groove wiring 2.

FIG. 2 is a cross-sectional view of the TEG 200 according to the present embodiment.
The TEG 200 is provided in the multilayer wiring layer. Further, the lower conductor pattern 1 embedded in the first insulating film 80 in the multilayer wiring layer is provided. The TEG 200 includes a lower conductor pattern 1 embedded in the surface layer of the first insulating film 80, a second insulating film 20 formed on the first insulating film 80 and the lower conductor pattern 1, and the same lower conductor pattern. 1 and a plurality of upper layer conductor patterns 10 facing each other. The upper conductor pattern 10 may be embedded in the surface layer of the second insulating film 20 or may be formed on the second insulating film 20.

  One upper layer conductor pattern 10, the lower layer conductor pattern 1, and the second insulating film 20 form one capacitor element. Since the TEG 200 includes a plurality of upper conductor patterns 10, the TEG 200 includes a plurality of capacitive elements. The plurality of capacitive elements are connected to electrode pads provided in the multilayer wiring layer. A plurality of TEGs 200 may be formed in the same layer. At this time, each upper layer conductor pattern 10 provided at the same position in each of the plurality of TEGs 200 is connected to the same electrode pad. Further, the plurality of TEGs 200 are preferably connected in parallel to the electrical pads.

  FIG. 3 is a plan view of the TEG according to the present embodiment. In FIG. 3, the second insulating film 20 is omitted, and the upper layer conductor pattern 10 and the lower layer conductor pattern 1 are illustrated so as to understand the positional relationship in plan view. The depth of the dishing shape formed in the lower layer conductor pattern 1 is smaller as it is closer to the end of the lower layer conductor pattern 1 and often increases as it approaches the center (arrow in FIG. 2). Further, the maximum depth of the dishing shape generated in the lower conductor pattern 1 increases as the width of the lower conductor pattern 1 increases. Therefore, in the TEG 200, the plurality of upper layer wirings 10 are preferably provided along a straight line passing through the center of the lower layer groove wiring 1 in plan view.

  FIG. 4 is a cross-sectional view for explaining the wiring connection of the TEG according to the present embodiment. The plurality of TEGs 200 are connected in parallel to the electric pad. In each TEG 200, the same electric signal is input to the upper conductor pattern 10 disposed in the same place. Further, in order to output a signal output from each upper layer conductor pattern 10, the lower layer conductor pattern 1 in each TEG 200 is connected in parallel to PAD_L.

  By connecting the TEGs 200 in parallel, the capacitances of the capacitive elements located at the same place among the plurality of TEGs 200 are integrated. As the number of TEGs 200 increases, the measurement sensitivity improves. This is because the sum of the electric capacities of the individual TEGs 200 is increased by integration.

FIGS. 5-8 is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on this embodiment.
5 in FIG. 5 indicates a partial region in the chip, and 50 indicates only the vicinity of the TEG 200. As shown in FIG. 5, first, a base interlayer film 60 is formed, and a trench wiring etching stopper film 70 and a first insulating film 80 are sequentially formed thereon. The TEG 200 may be arranged in a chip or formed in a scribe region.

  Next, as shown in FIG. 6, lithography and dry etching are performed on the first insulating film 80. As a result, a wiring groove is formed.

  Next, as shown in FIG. 7, a thin barrier metal (seed metal) is formed inside each wiring trench and on the first insulating film 80, and the lower conductor pattern 1 is formed by plating using this film. A metal film is formed. As the metal film used here, copper or the like is used.

  Next, the metal film located on the first insulating film 80 is removed using a CMP method. Thereby, the lower layer conductor pattern 1 in the TEG 200 shown in the region 50 and the lower layer trench wiring 2 in the partial region 30 in the chip are formed. The lower layer trench wiring 2 in the chip is used as a wiring in the chip.

Next, as shown in FIG. 8, a second insulating film 20 is formed on the entire surface including the lower conductor pattern 1 and the lower groove wiring 2. At this time, CMP polishing is performed on the second insulating film 20 as necessary so that the surface layer of the second insulating film 20 becomes flat. As a material for forming the second insulating film 20, a silicon substrate (SiO ₂ ), a carbon-doped silicon oxide film (SiOC), or the like is used.

  Next, the upper conductor pattern 10 is formed on the second insulating film 20 located in the scribe line 50 or so as to be embedded in the second insulating film. The upper conductor pattern 10 may be formed by a damascene method, or may be formed by patterning an Al layer, for example.

  Next, the necessary number of wiring layers and electrode pads are formed on the upper conductor pattern 10 and the second insulating film 20. At this time, electrode pads are formed in the uppermost wiring layer.

  Next, the electric capacitance between each lower layer conductor pattern 1 and each upper layer conductor pattern 10 between the electrode pads (between PAD_L and PAD_1, between PAD_L and PAD_2, between PAD_L and PAD_3, etc.) is measured.

  Next, each interlayer distance between the lower layer conductor pattern 1 and the upper layer conductor pattern 10 is obtained from the measured electric capacitance of each capacitor element. This can be obtained from the relationship of electric capacity C = (dielectric constant ε × surface area S of measurement site) / (interlayer distance D between lower layer conductor pattern 1 and upper layer conductor pattern 10). That is, if the electric capacity between the lower layer conductor pattern 1 and each upper layer conductor pattern 10 is known, the interlayer distance between an arbitrary portion where the upper layer conductor pattern 10 is disposed and the lower layer conductor pattern 1 can be obtained. Therefore, by determining the interlayer distance between each of the plurality of upper layer conductor patterns 10 and the lower layer conductor pattern 1, the tendency of the interlayer distance between the lower layer conductor pattern 1 and the upper layer conductor pattern 10 can be understood. That is, the dishing shape generated in the lower conductor pattern 1 can be seen. Thereby, it is evaluated whether or not the lower layer trench wiring 2 disposed in the chip region 30 forms a correct wiring structure.

  The thickness of the second insulating film 20 on the lower conductor pattern 1 cannot be evaluated by a normal interlayer insulating film thickness evaluation apparatus (for example, lambda ace). This is because the size of the target lower conductor pattern 1 is about tens of μm or less, and the spatial resolution in the plane space is insufficient.

  Next, effects of the semiconductor device according to the present embodiment will be described.

  By checking the electric capacity of each capacitive element forming the TEG 200, the interlayer distance between each upper-layer conductor pattern 10 and lower-layer conductor pattern 1 forming the capacitive element is obtained. At this time, the tendency of the interlayer distance is known from each of the determined interlayer distances. For this reason, the tendency of the depth of dishing formed in the lower conductor pattern 1 can be seen. As a result, it is evaluated whether the lower layer trench wiring 2 arranged in the semiconductor chip 30 forms a correct wiring structure.

(Second Embodiment)
FIG. 9 is a cross-sectional view of the TEG according to the present embodiment.
As shown in FIG. 9, the semiconductor device according to this embodiment is different from the first embodiment in that each upper layer conductor pattern 10 and the lower layer conductor pattern 1 are connected via vias 40. The via 40 is embedded in the second insulating film. For this reason, in the present embodiment, unlike the first embodiment, the via 40 functions as a resistance element, not a capacitive element.

FIG. 10 is a plan view of the TEG according to the present embodiment.
As shown in FIG. 10, also in the present embodiment, the plurality of upper layer conductor patterns 10 are preferably provided along a straight line passing through the center of the lower layer conductor pattern 1 in plan view. However, in the present embodiment, unlike the first embodiment, the two upper-layer conductor patterns 10 are arranged as one set in order to handle the two resistance elements as one set. This is because wiring connection is performed so that a signal is input from the upper conductor pattern 10a and a signal is output from the upper conductor pattern 10b.

  Next, a method for forming the via 40 and a wiring structure evaluation process using the via 40 in the method for manufacturing the semiconductor device of the present embodiment will be described.

  First, a base interlayer film 60 is formed in the scribe line 50, and a trench wiring etching stopper film 70 and a first insulating film 80 are sequentially formed thereon. At this time, also in the chip region 30, the base interlayer film 60, the trench wiring etching stopper film 70, and the first insulating film 80 are sequentially formed.

  Next, a wiring groove is formed in the scribe line 50. At this time, wiring grooves are also formed in the chip region 30.

  Next, a metal film to be the lower conductor pattern 1 is formed inside each wiring groove and on the first insulating film 80.

  Next, the metal film located on the first insulating film 80 is removed using a CMP method. Thereby, the lower conductor pattern 1 and the lower groove wiring 2 are formed, respectively.

  Next, the second insulating film 20 is formed on the entire surface including the lower conductor pattern 1 and the lower trench wiring 2.

  These forming methods are the same as those in the first embodiment. Next, a via hole is formed in the second insulating film 20. A via 40 is formed by embedding metal in the formed via hole. At this time, for example, tungsten is used as the metal buried in the via hole.

  Next, by forming the upper layer conductor pattern 10 as shown in FIG. 10, the lower layer conductor pattern 1 and the upper layer conductor pattern 10 are electrically connected via the via 40. The via 40 is provided from the upper conductor pattern 10 to the lower conductor pattern 1, that is, between the second insulating film 20 surface and the lower conductor pattern 1. When the damascene method is used, the via 40 and the upper conductor pattern 10 may be formed in the same process.

  Next, the evaluation process of the wiring structure using the via 40 will be described.

FIG. 11 is a cross-sectional view for explaining the wiring connection of the TEG 200 according to the present embodiment.
As shown in FIG. 11, a plurality of TEGs 200 are connected in series to the electrode pads. These TEGs 200 are provided in the same layer in the multilayer wiring layer. Specifically, in each TEG 200, wiring connection is performed so that the same signal is input to each resistance element. That is, a signal output from PAD_2n (n is an integer equal to or greater than 1) is input to the upper layer conductor pattern 10a, and is output from the upper layer conductor pattern 10b via the lower layer conductor pattern 1. Next, the signal output from the upper layer conductor pattern 10 b is input to the upper layer conductor pattern 10 a disposed at the same location in the other TEG 200. Such wiring connection is performed for all the TEGs 200. Finally, the upper layer conductor pattern 10b and PAD_2n-1 are connected so that a signal output from the upper layer conductor pattern 10b is input to PAD_2n-1 (n is an integer of 1 or more).

  Also in this embodiment, when measuring the resistance value of each via 40 connected to each upper layer conductor pattern 10, the greater the number of resistance elements, the higher the measurement sensitivity. This is because the sum of the resistance values of the vias 40 in each TEG 200 is increased by integration.

  Next, in the TEG 200 connected by wiring as shown in FIG. 11, the resistance of each via 40 arranged at a different position is measured. Thereby, each interlayer distance from the surface of the second insulating film 20 to the lower conductor pattern 1 can be obtained. This can be obtained from the relationship of resistance R = (resistivity ρ × length L) / (cross-sectional area A of via 40). That is, if the resistance of each of the plurality of vias 40 is known, the interlayer distance between each upper layer conductor pattern 10 and lower layer conductor pattern 1 connected to the via 40 can be obtained. For this reason, the tendency of the interlayer distance can be understood by obtaining the interlayer distance from the lower conductor pattern 1 in each of the plurality of upper conductor patterns 10. Thereby, the tendency of the depth of dishing formed in the lower conductor pattern 1 can be understood. Thereby, it is evaluated whether or not the lower layer trench wiring 2 disposed in the chip region 30 forms a correct wiring structure.

(Third embodiment)
FIG. 12 is a cross-sectional view of the semiconductor device according to the present embodiment.
As shown in FIG. 12, in the semiconductor device according to the present embodiment, a plurality of capacitive elements 100 are formed by one lower conductor pattern 1, a plurality of upper conductor patterns 10, and a second insulating film 20. The plurality of capacitive elements 100 have slightly different capacitances. At this time, the lower conductor pattern 1 forms a wiring structure. In addition, the semiconductor device according to the present embodiment has the same structure as the TEG 200. However, at least one of the capacitive elements is used as a capacitance of an electric circuit.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

DESCRIPTION OF SYMBOLS 1 Lower layer conductor pattern 2 Lower layer groove | channel wiring 10 (10a, 10b) Upper layer conductor pattern 20 2nd insulating film 30 Chip area | region 40 Via 50 Scribe line 60 Underlayer interlayer film 70 Groove wiring etching stopper film 80 1st insulating film 100 Capacitance element 200 TEG

Claims (8)

A multilayer wiring layer;
A TEG provided in the multilayer wiring layer;
With
The TEG is
A lower conductor pattern embedded in a surface layer of the first insulating film in the multilayer wiring layer;
A second insulating film formed on the first insulating film and on the lower conductor pattern;
A plurality of upper conductor patterns embedded in a surface layer of the second insulating film or formed on the second insulating film, each facing the same lower conductor pattern;
A semiconductor device. The multilayer wiring layer is provided with electrode pads,
The semiconductor device according to claim 1, wherein the plurality of different TEGs are connected in parallel to the electrode pads. A multilayer wiring layer;
A TEG provided in the multilayer wiring layer;
With
The TEG is
A lower conductor pattern embedded in a surface layer of the first insulating film in the multilayer wiring layer;
A second insulating film formed on the first insulating film and on the lower conductor pattern;
A plurality of upper conductor patterns embedded in a surface layer of the second insulating film or formed on the second insulating film, each facing the same lower conductor pattern;
A via located in the second insulating film, provided for each of the plurality of upper layer conductor patterns, and connecting the upper layer conductor pattern to the lower layer conductor pattern;
A semiconductor device. The multilayer wiring layer is provided with electrode pads,
The semiconductor device according to claim 3, wherein the plurality of different TEGs are connected in series to the electrode pads.   5. The semiconductor device according to claim 1, wherein the plurality of upper layer conductor patterns are arranged along a straight line passing through a center of the lower layer conductor pattern in a plan view. A lower conductor pattern embedded in the surface layer of the first insulating film in the multilayer wiring layer;
A second insulating film formed on the first insulating film and on the lower conductor pattern;
A plurality of upper conductor patterns embedded in a surface layer of the second insulating film or formed on the second insulating film, each facing the same lower conductor pattern;
Including
Each of the upper conductor patterns is a semiconductor device in which different capacitive elements are formed by the lower conductor pattern and the second insulating film. Burying a lower layer conductor pattern located in the scribe line and embedding a lower layer trench wiring located in the chip region in the first insulating film;
Forming an interlayer insulating film on the lower conductor pattern and on the lower groove wiring;
Forming a plurality of upper layer conductor patterns on the interlayer insulating film or in the interlayer insulating film so as to face the lower layer conductor pattern;
Using the lower conductor pattern formed in the scribe line, the interlayer insulating film, and the upper conductor pattern as a TEG, and evaluating the lower trench wiring by inspecting the TEG, to manufacture a semiconductor device Method. Burying a lower layer conductor pattern located in the scribe line and embedding a lower layer trench wiring located in the chip region in the first insulating film;
Forming an interlayer insulating film on the lower conductor pattern and on the lower groove wiring;
Providing a plurality of vias in the interlayer insulating film;
Forming a plurality of upper layer conductor patterns connecting the lower layer conductor patterns with the plurality of vias;
Using the lower layer conductor pattern formed in the scribe line, the plurality of vias, and the plurality of upper layer conductor patterns as a TEG, and evaluating the lower layer trench wiring by inspecting the TEG. Manufacturing method.

Images