JP2008197427A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably operate a scanning electrode driving circuit, even in a transient period during power source on or power source off and to obviate the occurrence of faults, such as damaging of a scanning electrode drive circuit even for energizing of a connector in a disconnected state. <P>SOLUTION: The scanning electrode driving circuit of the plasma display apparatus includes a first switching element for outputting a reference potential, a second switching element outputting the voltage superimposed on the reference potential, a controller for controlling the first switching element and the second switching element, based on a control signal, and the connector 12 detachably connecting a signal transmission member for supplying the control signal to the controller. In addition, the control signal is pulled up or pulled down, in such a manner that the first switching element is turned on or off, and the second switching element is made turn off or on by the connection state of the signal transmission member 23 to or from the connector 212. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a plasma display device which is an image display device using a plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other.

  A plurality of pairs of display electrodes, each consisting of a pair of scan electrodes and sustain electrodes, are formed in parallel on the front plate, and a plurality of parallel data electrodes are formed on the back plate. Then, the front plate and the rear plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other.

  The plasma display device using such a panel is a subfield method, that is, a subfield for lighting a discharge cell after a single field period is composed of a plurality of subfields having an initialization period, an address period, and a sustain period. A method of performing gradation display by combination is common. In the address period, a scan pulse is applied to the scan electrode and an address pulse is selectively applied to the data electrode to generate an address discharge in the discharge cells.

  A circuit that generates a scan pulse is configured using a switching element that outputs a high voltage and a switching element that outputs a low voltage, and is often realized as an IC in which a large number of these switching elements are integrated. When using such an IC, in order to prevent a large through current from flowing because the above-mentioned switching elements are simultaneously turned on in a transition period when the power source of the plasma display device is turned on or off, Need to control.

  In many cases, a plasma display apparatus is configured such that a circuit for generating a scanning pulse is mounted on a dedicated circuit board and a control signal for a switching element is supplied via a connector. In such a plasma display device, a connection failure of the connector may occur due to an operation mistake in the manufacturing process or carelessness at the time of maintenance, and the power may be supplied without being noticed.

A protection circuit that detects a connection failure of the connector and stops the operation of the scan electrode drive circuit when the connector is disconnected so that the circuit does not generate heat or the circuit element does not deteriorate even in such a case. (For example, refer patent document 1).
JP 2004-317609 A

  However, the above-mentioned image display device needs to be newly provided with a detection circuit for detecting the disconnection of the connector and a protection circuit for stopping the operation of the scan electrode driving circuit, and there are problems such as an increase in the circuit and an associated increase in cost. It was.

  The present invention has been made in view of these problems, and allows the scan electrode drive circuit to operate stably even during a transitional period when the power is turned on or when the power is turned off, without significantly adding or changing the circuit. An object of the present invention is to provide a plasma display device that does not cause a problem such as damage to a scan electrode driving circuit even if the power is supplied with the connector disconnected.

  The present invention relates to a panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, a scan electrode drive circuit that drives the scan electrode, a sustain electrode drive circuit that drives the sustain electrode, and a data electrode A scanning electrode driving circuit, a first switching element that outputs a reference potential, a second switching element that outputs a voltage superimposed on the reference potential, a first switching element, A control unit that controls the second switching element based on the control signal; and a connector that removably connects a signal transmission member that supplies the control signal to the control unit. Pull up or pull down the control signal so that one switching element is turned on or off and the second switching element is turned off or on Characterized by being configured to down. With this configuration, the scan electrode drive circuit can be operated stably even during a transition period when the power is turned on or off, without adding or changing the circuit significantly, and the power is turned on when the connector is disconnected. Even in such a case, it is possible to provide a plasma display device that does not cause problems such as damage to the scan electrode driving circuit.

  Further, the plasma display device of the present invention pulls up or pulls down the control signal using a resistor connected in series, and at the potential of the connection point of the resistor connected in series via the signal transmission member connected to the connector. May be used to pull down or pull up the control signal. With this configuration, the scan electrode drive circuit can be operated stably even in the transition period when the power is turned on or off, by simply adding a resistor and a wiring for applying a potential thereto, and the connector has been disconnected. It is possible to provide a plasma display device that does not cause problems such as damage to the scan electrode drive circuit even when the power is supplied in the state.

  According to the present invention, the scan electrode driving circuit is stably operated even in a transition period when the power is turned on or off, without significantly adding or changing the circuit, and the connector is disconnected. Therefore, it is possible to provide a plasma display device that does not cause problems such as damage to the scan electrode driving circuit even when the power is supplied.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing a structure of a panel 10 used in the embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. A discharge gas is sealed in the discharge space. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. As shown in FIG. 1 and FIG. 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is a large interelectrode capacitance Cp.

  Next, the configuration and operation of the plasma display device in the present embodiment will be described.

  FIG. 3 is a circuit block diagram of plasma display device 100 in accordance with the exemplary embodiment of the present invention. The plasma display apparatus 100 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit that supplies necessary power to each circuit block. 46 and a power switch 47 for supplying power to the power supply circuit 46 from the commercial power supply AC100 (V).

  The image signal processing circuit 41 converts the image signal into an image signal having the number of pixels and the number of gradations that can be displayed on the panel 10, and the light emission / non-light emission in each of the subfields is set to “1” of each bit of the digital signal, The image data is converted to image data corresponding to “0”. The data electrode drive circuit 42 converts the image data into address pulses corresponding to the data electrodes D1 to Dm and applies them to the data electrodes D1 to Dm.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to each circuit block. Scan electrode drive circuit 43 and sustain electrode drive circuit 44 create drive voltage waveforms based on the respective timing signals and apply them to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn.

  The power supply circuit 46 includes various power supplies to be supplied to each circuit block. In particular, the power supply supplied to the scan electrode drive circuit 43 includes a power supply VSUS that generates a positive sustain pulse voltage Vsus and a positive voltage Vset. A power supply VSET for generating, a power supply VAD for generating a negative voltage Vad, a power supply VSCN for generating a voltage Vscn superimposed on the power supply VAD, and a floating power supply V5V for generating a control voltage 5 (V) are provided.

  FIG. 4 is a circuit diagram showing details of scan electrode driving circuit 43 in the embodiment of the present invention. Scan electrode driving circuit 43 includes a scan pulse generating circuit 50 for generating a scan pulse, and a voltage setting circuit 60 for setting a reference potential Vfl of scan pulse generating circuit 50 to a predetermined voltage described later.

  Scan pulse generation circuit 50 has a bootstrap unit 51 serving as a power source for voltage Vscf superimposed on reference potential Vfl, and scan pulse output having switch units OUT1 to OUTn that output scan pulse voltages to scan electrodes SC1 to SCn, respectively. And a resistor R51 for applying the voltage Vscf to the switch units OUT1 to OUTn of the scan pulse output unit 52. The bootstrap unit 51 includes a capacitor C51 and a diode D51, and draws up the voltage Vscn supplied from the power supply VSCN of the power supply circuit 46. Each of the switch units OUT1 to OUTn of the scan pulse output unit 52 outputs the voltage Vscf superimposed on the switching elements QL1 to QLn, which are first switching elements for outputting the reference potential Vfl, and the reference potential Vfl. It has switching elements QH1 to QHn which are second switching elements.

  Voltage setting circuit 60 generates a switching waveform Q61 for clamping reference potential Vfl of scan pulse generating circuit 50 to negative voltage Vad, sustain pulse generating unit 70 for generating a sustain pulse, and a ramp waveform voltage. And an initialization waveform generator 80.

  Sustain pulse generator 70 includes switching element Q71 and switching element Q72 for clamping the scan electrode to sustain pulse voltage Vsus, switching element Q73 for clamping the scan electrode to 0 (V), and switching elements Q71, Q72, and Q73. Each has diodes D71, D72, and D73 connected in parallel. Further, it has a capacitor C74 for collecting power, switching elements Q75 and Q76, diodes D75 and D76 for backflow prevention, and inductors L75 and L76 for resonance. The capacitor C74 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to about Vsus / 2, which is about half of the sustain pulse voltage Vsus described later. The initialization waveform generator 80 includes a field effect transistor Q81, a capacitor C81, a resistor R81, a Zener diode D81, a Miller integrating circuit connected to the power source of the voltage Vset, a field effect transistor Q82, a capacitor C82, and a resistor R82. A Miller integrating circuit connected to the common voltage Vad ′ and a separating circuit using the switching element Q83.

  Using the voltage setting circuit 60 configured as described above, the reference potential Vfl of the scan pulse generation circuit 50 can be set to the negative voltage Vad, the voltage 0 (V), or other voltage as described later. .

  When the panel 10 is driven, a very large peak current flows through the switching elements Q75, Q76, Q71, Q73, Q83, Q61, and the diodes D75, D76, D72. In FIG. 4, each of these elements is shown by using one element symbol. Usually, these switching elements and diodes are connected in parallel by connecting several to a dozen or so elements having the same specifications. We are using it lowered.

  Next, a driving method for driving the panel 10 will be described. The panel 10 performs gradation display by dividing the one-field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address discharge are formed on each electrode. The initializing operation at this time includes an all-cell initializing operation for generating an initializing discharge in all discharge cells and a selective initializing operation for generating an initializing discharge in a discharge cell that has generated a sustain discharge. In the address period, a scan pulse is applied to the scan electrode as an address voltage, and an address pulse is selectively applied to the data electrode, so that an address discharge is selectively generated in the discharge cells to emit light to form wall charges. In the sustain period, a number of sustain pulses corresponding to the luminance weight are alternately applied to the display electrode pairs, and a sustain discharge is generated in the discharge cells that have generated the address discharge to emit light.

  FIG. 5 is a drive voltage waveform diagram applied to each electrode in the embodiment of the present invention. The first subfield is a subfield that performs an all-cell initialization operation, and the second subfield is a subfield that performs a selective initialization operation. The drive voltage waveform of each subfield is shown as a field.

  In the first half of the initialization period in the first subfield, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively. Then, the switching elements Q73 and Q83 are turned on to set the reference potential Vfl to 0 (V), the switching elements QH1 to QHn of the switch portions OUT1 to OUTn are turned on, and the voltage Vscf is applied to the scan electrodes SC1 to SCn. Next, the switching element Q73 is turned off and the field effect transistor Q81 is turned on to operate the Miller integrating circuit. Then, the reference potential Vfl rises gradually toward the voltage Vset after the voltage rises by the Zener voltage Vz of the Zener diode D81. In this way, a ramp waveform voltage that gently rises toward voltage Vscf + Vset is applied to scan electrodes SC1 to SCn. While this ramp waveform voltage rises, a weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, and wall voltages are accumulated on the respective electrodes. . Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn. Then, field effect transistor Q81 is turned off, switching elements Q71 and Q72 are turned on to set reference potential Vfl to voltage Vsus, and voltage Vsus + Vscf is applied to scan electrodes SC1 to SCn. Next, the switching elements QH1 to QHn of the switch units OUT1 to OUTn are turned off, the switching elements QL1 to QLn are turned on, and the voltage Vsus is applied to the scan electrodes SC1 to SCn. Thereafter, switching element Q83 is turned off and field effect transistor Q82 is turned on to operate the Miller integrating circuit. Then, the reference potential Vfl gradually falls toward the voltage Vad ′. In this way, a ramp waveform voltage that gently falls toward voltage Vad 'is applied to scan electrodes SC1 to SCn. Then, a weak initializing discharge occurs again during this period, and the wall voltage on each electrode is adjusted to a value suitable for the address operation.

  As described above, in the initializing period of the first subfield, the all-cell initializing operation for generating the initializing discharge in all the discharge cells is performed.

  In the address period, voltage Ve2 is applied to sustain electrodes SU1 to SUn. Then, the switching element Q61 is turned on to set the reference potential Vfl to the negative voltage Vad and the switching elements QH1 to QHn are turned on, whereby the voltage Vad + Vscf is applied to the scan electrodes SC1 to SCn.

  Next, the switching element QH1 is turned off and the switching element QL1 is turned on, so that the negative scan pulse voltage Vad is applied to the scan electrode SC1 in the first row. Then, a positive address pulse Vd is applied to the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. Then, in the discharge cells in the first row, address discharge occurs in the discharge cells to which the address pulse is applied, and an address operation for accumulating wall voltage on each electrode is performed. On the other hand, no address discharge occurs in the discharge cells to which the address pulse voltage Vd is not applied. In this way, the write operation is selectively performed. Thereafter, switching element QH1 is turned on and switching element QL1 is turned off.

  Next, the switching element QH2 is turned off, the switching element QL2 is turned on, the scan pulse voltage Vad is applied to the scan electrode SC2 in the second row, and the discharge cell to be emitted in the second row among the data electrodes D1 to Dm. An address pulse Vd is applied to the data electrode Dk. Then, address discharge occurs selectively in the discharge cells in the second row. The above address operation is performed up to the discharge cell in the nth row.

  Thereafter, the switching elements QH1 to QHn and the switching elements QL1 to QLn of the switch units OUT1 to OUTn are turned off, and the outputs of the switch units OUT1 to OUTn are set in a high impedance state. During this time, switching element Q61 is turned off, switching element Q83 and switching element Q73 are turned on, and reference potential Vfl is set to 0 (V). Thereafter, the switching elements QL1 to QLn of the switch units OUT1 to OUTn are turned on, and 0 (V) is applied to the scan electrodes SC1 to SCn.

  In the subsequent sustain period, 0 (V) is applied to sustain electrodes SU1 to SUn, and sustain pulse voltage Vsus is applied to scan electrodes SC1 to SCn. In order to apply sustain pulse voltage Vsus to scan electrodes SC1 to SCn, switching element Q73 is turned off and switching elements Q75, Q72, and Q83 are turned on. Then, current starts to flow from switching capacitor Q75, diode D75, inductor L75, switching element Q72 or diode D72, switching element Q83, and switching elements QL1 to QLn from power recovery capacitor C74, and the voltages of scan electrodes SC1 to SCn Begins to rise. Since the inductor L75 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrodes SC1 to SCn rises to the vicinity of the voltage Vsus after the time ½ of the resonance period has elapsed. Then, the switching element Q71 is turned on. Then, scan electrodes SC1 to SCn are connected to the power supply through switching element Q71, so that the voltages of scan electrodes SC1 to SCn are forcibly increased to voltage Vsus. Then, a sustain discharge occurs in the discharge cell in which the address discharge has occurred.

  Subsequently, 0 (V) is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vsus is applied to sustain electrodes SU1 to SUn. To apply 0 (V) to scan electrodes SC1 to SCn, switching elements Q76 and Q83 are turned on. Then, current begins to flow from scan electrodes SC1 to SCn to switching element QL1 to QLn, switching element Q83, inductor L76, diode D76, and switching element Q76, and to capacitor C74 for power recovery, and the voltage of scan electrodes SC1 to SCn It begins to fall. Since the inductor L76 and the interelectrode capacitance Cp also form a resonance circuit, the voltage of the scan electrodes SC1 to SCn drops to near 0 (V) after the time ½ of the resonance period has elapsed. Then, the switching element Q73 is turned on. Then, scan electrodes SC1 to SCn are connected to the ground potential through switching element Q73, so that the voltages of scan electrodes SC1 to SCn are forcibly lowered to 0 (V). Then, sustain pulse voltage Vsus is applied to sustain electrodes SU1 to SUn. As a result, the sustain discharge occurs again in the discharge cell in which the sustain discharge has occurred.

  Similarly, the address discharge is applied in the address period by applying sustain pulses of the number corresponding to the luminance weight alternately to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and applying a potential difference between the electrodes of the display electrode pair. The sustain discharge is continuously performed in the discharge cell that has caused the failure.

  In the subsequent initialization period of the second subfield, the same operation as in the latter half of the initialization period of the first subfield is performed. That is, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, and a ramp waveform voltage that gently falls toward voltage Vad 'is applied to scan electrodes SC1 to SCn. Then, initializing discharge is generated in the discharge cells that have undergone sustain discharge in the sustain period of the first subfield. As described above, during the initializing period of the second subfield, the selective initializing operation for generating the initializing discharge in the discharge cells in which the sustain discharge has been performed is performed.

  The subsequent address period and sustain period are substantially the same as the address period and sustain period of the first subfield, and thus description thereof is omitted. The same applies to the subsequent subfields except for the number of sustain pulses.

  In this embodiment, the voltage values applied to the electrodes are, for example, voltage Vset = 330 (V), voltage Vsus = 200 (V), voltage Vscf = 145 (V), voltage Vad = −105 (V). The voltage Ve1 = 165 (V) and the voltage Ve2 = 170 (V). However, these voltage values are merely an example, and it is desirable to set them to optimum values as appropriate in accordance with the characteristics of the panel 10, the specifications of the plasma display device 100, and the like.

  FIG. 6 is a circuit block diagram showing details of scan pulse output unit 52 in the embodiment of the present invention. The scan pulse output unit 52 includes the switch units OUT1 to OUTn that output the scan pulse voltage as described above. In addition, the scan pulse output unit 52 controls the switching elements QH1 to QHn and QL1 to QLn of the switch units OUT1 to OUTn. The scanning pulse control unit 53 is provided. Scan pulse control unit 53 includes shift registers SR for supplying binary signals having different phases to output control units RG1 to RGn and output control units RG1 to RGn.

  The shift register SR has a data input DT, a clock input CK, and n outputs O1 to On, and sequentially shifts and outputs binary data input from the data input DT every time the clock input CK is input. The shift register SR receives one pulse from the data input DT during the writing period, and sequentially shifts the pulse to thereby transfer n binary data as the basis of the scanning pulse to each of the output control units RG1 to RGn. Output.

  Each of the output control units RG1 to RGn receives two control signals C1 and C2 and one corresponding output of the shift register SR, and outputs one of the switching elements QH1 to QHn and QL1 to QLn of the switch units OUT1 to OUTn. The corresponding switching element is controlled.

  Electric power is supplied to the shift register SR and the output control units RG1 to RGn from a floating power source V5V that generates a control voltage 5 (V).

  FIG. 7 is a diagram showing the control of the output control units RG1 to RGn in the embodiment of the present invention, and controls the outputs of the switch units OUT1 to OUTn as follows according to the two control signals C1 and C2. To do. When the control signals C1 and C2 are both at a low level (hereinafter abbreviated as “L”) with respect to the output control unit RGi, both the switching elements QHi and QLi are turned off to set the output to a high impedance state. When the control signal C1 is “L” and the control signal C2 is at a high level (hereinafter abbreviated as “H”), the switching elements QHi and QLi are controlled according to the output of the corresponding shift register SR. In the present embodiment, if the output Oi of the shift register SR is “H”, the switching element QHi is turned on, the switching element QLi is turned off, and if the output Oi of the shift register SR is “L”, the switching element QHi is turned on. Off, switching element QLi is turned on. When the control signal C1 is “H” and the control signal C2 is “L”, the switching element QHi is turned off and the switching element QLi is turned on regardless of the output of the corresponding shift register SR, and the reference potential Vfl is output. When the control signals C1 and C2 are both “H”, the switching element QHi is turned on and the switching element QLi is turned off regardless of the output of the corresponding shift register SR, and the voltage Vscf superimposed on the reference potential Vfl is set. Output.

  Note that the plurality of switch units, the plurality of output control units, and the corresponding portions of the shift register of the scan pulse output unit 52 are integrated into an IC. Hereinafter, this IC is referred to as “scanning IC”. In the present embodiment, 64 scan electrodes are combined into one scan IC, and 12 scan ICs are used to supply scan pulses to each of n = 768 scan electrodes. In this way, by forming the scanning pulse output unit 52 having a large number of outputs as an IC, the circuit can be made compact and the mounting area can be reduced.

  FIG. 8 is a timing chart showing details of the operation of the scan pulse generation circuit 50 in the embodiment of the present invention, and shows the operation in the writing period. FIG. 8 also shows control signals for switching elements Q73 and Q83 and switching element Q61.

  Since the switching element Q61 is on during the writing period, the reference potential Vfl is the voltage Vad. Next, “L” is input as the data input DT of the shift register SR, the clock input CK is input, and the first output O1 of the shift register SR is set to “L”. Then, the output control unit RG1 turns off the switching element QH1, turns on the switching element QL1, and applies the scan pulse voltage Vad to the scan electrode SC1.

  Next, “H” is input to the data input DT of the shift register SR, and further, the clock input CK is input, the first output O1 of the shift register SR is set to “H”, and the second output O2 is set to “L”. To do. Then, the output control unit RG1 turns on the switching element QH1, turns off the switching element QL1, and applies the voltage Vad + Vscn to the scan electrode SC1, and the output control unit RG2 turns off the switching element QH2, turns on the switching element QL2, and turns on the scan electrode SC2. A scan pulse voltage Vad is applied to.

  Thereafter, by sequentially inputting the clock input CK while inputting “H” as the data input DT of the shift register SR, the scan pulses can be sequentially applied to the scan electrodes SC3 to SCn. In this embodiment, the control signal C1 is provided with an “H” period in synchronization with the input of the clock input CK, and a time interval is provided between successive scanning pulses. It is not necessary and may be omitted.

  Thereafter, the writing period ends and the sustain period starts. At this time, the reference potential Vfl is switched from the voltage Vad to 0 (V), and the outputs of the switch units OUT1 to OUTn are switched to the high voltage side via the switching elements QH1 to QHn. To the low voltage side via the switching elements QL1 to QLn.

  FIG. 9 is an exploded perspective view showing an example of the structure of the plasma display device 100 according to the embodiment of the present invention. The plasma display device 100 includes a panel 10, a front frame 91 and a back cover 92 that house the panel 10, a chassis 93 that holds the panel 10, and a heat conductive sheet 94 that releases heat generated in the panel 10 to the chassis 93. Prepare. The plasma display device 100 further includes a circuit board group 95 on which drive circuits for driving the panel 10 such as the scan electrode drive circuit 43, the sustain electrode drive circuit 44, the timing generation circuit 45, and the power supply circuit 46 are mounted. These circuit board groups 95 are arranged on the chassis 93.

  Here, the scan electrode drive circuit 43 is divided and mounted on the circuit boards 210a and 210b and the circuit board 220, and half of the scan pulse output unit 52 is mounted on the circuit board 210a, and the circuit board 210b is scanned. The remaining half of the pulse output unit 52 is mounted, and the circuit board 220 is mounted with the scan electrode drive circuit 43 excluding the scan pulse output unit 52.

  The circuit board 220 has card edge connectors 221a and 221b. By connecting the circuit boards 210a and 210b to the card edge connectors 221a and 221b, respectively, the circuit boards 210a and 210b have the reference potential Vfl and the reference potential Vfl. A superimposed voltage Vscf and a control voltage 5 (V) superimposed on the reference potential Vfl are supplied. Furthermore, the circuit board 220 has connectors 222a and 222b for supplying control signals and the like to the circuit boards 210a and 210b.

  The circuit board 210a has a connector 212a, and a data input DT, a clock input CK, and two control signals C1 and C2 are supplied from the connector 222a to the connector 212a via an FPC 232a which is a signal transmission member. Similarly, the circuit board 210b is supplied with the data input DT, the clock input CK, and the two control signals C1 and C2 from the connector 222b to the connector 212b via the FPC 232b. A reference potential Vfl and a control voltage 5 (V) are also supplied.

  FIG. 10 is a wiring diagram of the connectors 212a and 222a and the scan pulse output unit 52 in the embodiment of the present invention, and shows a state in which each control signal is pulled up and pulled down on the circuit board 210a. The data input DT and the clock input CK of the shift register SR are pulled down to the reference potential Vfl via the resistors R213 and R214, respectively, and the control signal C1 is pulled up to the voltage Vfl + 5 (V) via the resistor R215. The control signal C2 is pulled down to the reference potential Vfl via two resistors R216 and R217 connected in series. A voltage Vfl + 5 (V) is applied to the connection point between the two resistors R216 and R217 from the circuit board 220 via the connector 222a, the FPC 232a, and the connector 212a.

  By connecting in this way, when the connector 212a and the connector 222a are connected by the FPC 232a, the control signal C2 is also pulled up to the voltage Vfl + 5 (V) via the resistor R216. However, when a connection failure such as disconnection of the FPC 232a occurs, the control signal C2 is pulled down to the reference potential Vfl via the resistors R216 and R217.

  By connecting in this way, the scan pulse generating circuit can be operated stably, and even if energized with the connector disconnected, the scan electrode driving circuit is not damaged. The reason will be described below.

  FIG. 11 is a diagram showing a transient operation during a period after the power switch 47 of the plasma display device 100 is turned on until normal operation is started in the embodiment of the present invention. The voltages of the control signals C1 and C2 pulled up to the power supply are shown. If the voltage of the floating power supply V5V is 0 (V), the switching elements QL1 to QLn and the switching elements QH1 to QHn of the switch units OUT1 to OUTn are both off. Since the voltages of the control signals C1 and C2 rise after the power switch 47 is turned on, the switching elements QH1 to QHn are turned on while the switching elements QL1 to QLn are turned off. This state is a normal standby state of the switch units OUT1 to OUTn. Thereafter, when each of the power supplies output from the power supply circuit 46 starts up normally, the plasma display apparatus 100 starts an image display operation.

  On the other hand, a connection failure such as disconnection of the FPC 232a connecting the connector 212a and the connector 222a occurs due to an operation mistake in the manufacturing process of the plasma display device 100 or carelessness at the time of maintenance. It can happen. At this time, assuming that the control signal C2 is pulled up to 5 (V), a sustain pulse or the like is applied to the scan electrodes SC1 to SCn via the capacitor C51, the resistor R51, and the switching elements QH1 to QHn. A large current for charging and discharging the inter-capacitance Cp flows. However, these circuit elements are not designed to allow a large charge / discharge current to flow, which causes the circuit elements to generate heat or deteriorate.

  However, in the present embodiment, when the connection failure of the connector 212a occurs, the control signal C2 is automatically pulled down, so that the switching elements QH1 to QHn are turned off and the switching elements QL1 to QLn are turned on. Since the switching elements QL1 to QLn are designed to allow a large current to flow due to the sustain discharge, there is no possibility that the circuit element generates heat or deteriorates even when energized without noticing the connection failure.

  Similarly, the control signal is pulled up and pulled down for the circuit board 210b, and there is no possibility that the circuit element generates heat or deteriorates even when the power is supplied without noticing the connection failure of the connector 212b.

  In the present embodiment, the control signal C2 is pulled down using the resistors R216 and R217 connected in series, and the resistor connected in series via the FPC 232 that is a signal transmission member connected to the connector 212. In the above description, the voltage Vfl + 5 (V) is applied to the connection point between R216 and R217 to pull up the control signal C2. However, the present invention is not limited to this, and depending on the control signal for controlling the switching element and its logic, the pull-up or pull-down state of the corresponding control signal is switched according to the connection state of the signal transmission member. A similar effect can be obtained by adopting a different configuration.

  Further, the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the values appropriately according to the characteristics of the panel, the specifications of the plasma display device, and the like.

  The present invention makes it possible to stably operate the scan electrode drive circuit even during a transition period when the power is turned on and when the power is turned off without adding or changing the circuit significantly, and in the unlikely event that the connector is disconnected. However, since it does not cause problems such as damage to the scanning electrode driving circuit, it is useful as a plasma display device.

The exploded perspective view which shows the structure of the panel used for embodiment of this invention Electrode arrangement diagram of panel used in the embodiment of the present invention Circuit block diagram of plasma display device in accordance with exemplary embodiment of the present invention The circuit diagram which shows the detail of the scanning electrode drive circuit in embodiment of this invention Drive voltage waveform diagram applied to each electrode in the embodiment of the present invention The circuit block diagram which shows the detail of the scanning pulse output part in embodiment of this invention The figure which shows control of the output control part in embodiment of this invention Timing chart showing details of operation of scan pulse generation circuit in the embodiment of the present invention 1 is an exploded perspective view showing an example of the structure of a plasma display device in an embodiment of the present invention. Wiring diagram of connector and scan pulse output unit in the embodiment of the present invention The figure which shows the transient operation | movement of a period after turning on the power switch of a plasma display apparatus in embodiment of this invention until it starts normal operation | movement.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50 Scan pulse generation circuit 52 Scan pulse output part 60 Voltage setting circuit 100 Plasma display device 210 Circuit board 212a, 212b, 222a, 222b connector 220 (mounted with a scanning pulse output unit) Circuit board 221a, 221b Card edge (mounted with a scanning electrode driving circuit other than the scanning pulse output unit) Card edge Connectors 232a, 232b FPC (signal transmission member)
OUT1-OUTn switch part Q61, Q71, Q72, Q73, Q83 Switching element QL1-QLn (first) switching element QH1-QHn (second) switching element Vfl Reference potential

Claims (2)

A plasma display panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, a scan electrode drive circuit for driving the scan electrode, a sustain electrode drive circuit for driving the sustain electrode, and the data electrode A data electrode driving circuit for driving,
The scan electrode driving circuit includes: a first switching element that outputs a reference potential; a second switching element that outputs a voltage superimposed on the reference potential; and the first switching element and the second switching element. A control unit that performs control based on a control signal; and a connector that removably connects a signal transmission member that supplies the control signal to the control unit, and the connection state of the signal transmission member to the connector determines the first 1. A plasma display device, wherein one switching element is turned on or off, and the control signal is pulled up or pulled down so that the second switching element is turned off or on. The control signal is pulled up or pulled down using a resistor connected in series, and the control is performed by applying a potential to a connection point of the resistor connected in series via the signal transmission member connected to the connector. The plasma display apparatus according to claim 1, wherein the signal is pulled down or pulled up.

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