JP2008183432A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the misfetch of information transmitted from a main control board to a putout control board in a Pachinko game machine. <P>SOLUTION: When there is an INT interruption during a residual processing to be executed after a processing at the time of power supply, an interruption inhibition is released (S13), and then the processing is jumped to the interruption (INT) processing to perform the main processing. When there is an entry to a winning port after the processing for the time of the power supply, though putout can not be immediately performed, the presence of the entry can be detected and stored by the main control board 10. Since a prize ball command is transmitted after the start of the putout control CPU 21 of the putout control board 20, the putout control board 20 does not misfetch it. Thus, a player does not suffer from the drawback that prize balls are not put out though there is the entry. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention belongs to the technical field of gaming machines.

  In gaming machines such as pachinko machines, CPUs with different processing speeds have been installed on main control boards that have to perform various types of processing in recent years and on payout control boards that control payout of game media such as game balls and medals. is doing.

  This is because the processing speed is varied in consideration of the processing amount required for each CPU. However, since the difference in processing speed is reflected in the price difference of the CPU, the unit price of the slower processing speed is reduced. It can be lowered, and there is an effect in terms of cost.

  In general, when the main control board and the payout control board are compared, the main control board performs more processing, and therefore a CPU with a higher processing speed is mounted on the payout control board.

  For this reason, when power supply is detected by the power supply detection circuit when the power is turned on, a reset signal is first transmitted to a CPU with a slow processing speed, and a reset signal is sent to a CPU with a fast processing speed after a predetermined time has elapsed. There has been an invention in which both CPUs are configured to rise at approximately the same timing by transmission.

  However, in order to delay the transmission of the reset signal for a predetermined time, it is necessary to provide a delay circuit on the board having the power supply detection circuit or the main control board, and the cost effect obtained by changing the processing speed of the CPU can be reduced. It will be countered.

Therefore, if a startup operation is performed at the same timing as a configuration without a delay circuit, a CPU with a high processing speed will start up first, so the main control board starts normal processing and sends some information to the payout control board. Even if it is transmitted, the CPU with a slow processing speed of the payout control board does not start up, and the transmitted information may not be received. There was a wait state without executing.
JP 2001-327664 A

  The present invention eliminates the state in which the main control board waits without executing the normal process until the rise of the payout control board while maintaining the above-described cost advantage as a configuration without a delay circuit. The object is to prevent the transmission of information transmitted from the board to the payout control board.

The gaming machine according to claim 1 is:
A main control board having a game control CPU for controlling the progress of the game, a payout control board having a payout control CPU for controlling a payout device for paying out game media, and a power source for supplying power to the main control board and the payout control board In a gaming machine comprising a board and a power feeding detection circuit for detecting the presence or absence of the power feeding by the power board,
A CPU having a higher processing speed than the payout control CPU is mounted on the main control board as the game control CPU,
On the main control board,
Security check execution means 1 for executing a security check of the game control CPU when notified that the power supply detection circuit has detected the power supply;
A startup process execution means 1 for executing a power-on process after the security check by the security check execution means 1 is completed;
Timer means for starting timing during the power-on process by the startup process execution means 1;
Game processing execution means for executing normal processing consisting of the main processing and the remaining processing after the power-on processing by the startup processing execution means 1 is completed,
The main control board
Even when the time measured by the timer means passes a predetermined time set in advance, the normal time processing is executed and the data obtained by the normal time processing is stored,
The payout data relating to the payout of the game medium in the stored data is transmitted to the payout control board after the time measured by the timer means has passed the predetermined time.

When the main control board is notified that the power supply detection circuit has detected power supply, the security check execution means 1 executes a security check of the game control CPU.
After the security check by the security check execution means 1 is completed, the startup process execution means 1 executes a power-on process.

The timer means starts measuring time during the power-on process by the activation process execution means 1.
Then, the game process execution means executes the normal process composed of the main process and the remaining process after the power-on process by the activation process execution means 1 is completed.

  In addition, the main control board stores the data obtained by the normal time process while executing the normal time process even when the time measured by the timer means passes a predetermined time set in advance. The payout data relating to the payout of the game medium in the stored data is transmitted to the payout control board after the time measured by the timer means has passed a predetermined time.

  Even if the game control CPU of the main control board starts the normal process immediately after executing the security check and the power-on process, the payout data obtained during the normal process is not immediately sent to the payout control board. Since the information is transmitted to the payout control board after a predetermined time has elapsed, it is possible to eliminate the waiting state without executing the normal process after the security check and the power-on process.

  For example, if a momentary power failure occurs while playing with a ball game machine such as a pachinko machine, that is, when there are many game balls on the surface of the game board, the main control board and payout from the power supply board when power is restored When power is supplied to the control board and the power supply detection circuit detects this power supply, as described above, the security check by the security check execution means 1 and the power-on processing by the start-up process execution means 1 are executed, and the game control CPU is in a normal state. Start processing operation.

  In the main control board of the conventional configuration, it is not uniform depending on the processing speed of the game control CPU, but approximately 750 ms (security check 94 ms + standby time 650 ms) from when the reset signal accompanying power recovery is received until normal processing is executed I needed time before and after.

  Therefore, if a momentary power failure occurs during a game, even if the game ball on the surface of the game board passes through the detection switch for jackpot lottery or the detection switch for paying out a prize ball during that 750 ms, the main control board Since the normal processing is not executed, the player is given a disadvantage that no game reward such as a big win lottery or prize ball payout is performed.

  By eliminating the waiting time by using the present invention, the period during which the game ball passes the detection switch and the corresponding reward is not performed is approximately 100 ms (security check 94 ms + power-on processing 5 ms). It can be shortened, and it is possible to suppress the player from suffering a disadvantage as much as possible.

The gaming machine according to claim 2 is the gaming machine according to claim 1,
When the power supply detection circuit is notified that the power supply detection circuit has detected the power supply, the payout control board performs security check execution means 2 for executing a security check of the payout control CPU, and security check by the security check execution means 2 And a startup process execution means 2 for executing a power-on process after the completion.
The predetermined time is set to be equal to or longer than the time required for the security check of the payout control CPU by the security check execution means 2 minus the time required for the security check of the game control CPU by the security check execution means 1. It is characterized by that.

  The payout sent from the main control board to the payout control board by setting the predetermined time as described above in consideration of the difference between the time required for the security check of the game control CPU and the time required for the security check of the payout control CPU. Data can be more reliably prevented from being missed by the payout control board.

  The gaming machine according to claim 3 is the gaming machine according to claim 1 or 2, wherein the power supply detection circuit is provided on the power supply board, and the power supply board detects a power supply detection signal when the power supply detection circuit detects the power supply. Is transmitted to the main control board and the payout control board.

  Since a power supply detection circuit is provided on the power supply board and a power supply detection signal is simultaneously transmitted from the power supply board to the main control board and the payout control board, the game control CPU and the payout control CPU start the start-up operation at the same timing. Can do. Thereby, the effect of Claim 1 or 2 improves.

  The gaming machine according to claim 4 is the gaming machine according to claim 1 or 2, wherein the power supply detection circuit is provided on the power supply board, and the power supply board detects a power supply detection signal when the power supply detection circuit detects the power supply. To the main control board, and when the main control board receives the power supply detection signal, the main control board sends a signal notifying that the power supply detection circuit has detected the power supply before executing the normal processing. It transmits to the payout control board.

  A power supply detection circuit is provided on the power supply board and a power supply detection signal is transmitted from the power supply board to the main control board, but the power supply detection signal is not sent to the payout control board, and the main control board receiving the power supply detection signal Before the process is executed, the power supply detection circuit transmits a signal notifying that power supply has been detected, so that the game control CPU and the payout control CPU do not start the start-up operation at the same timing. Even if there is a difference between the rising timings of both CPUs, the main control board is performing normal processing, so there is an effect that the game is not affected.

Next, embodiments of the present invention will be described based on examples of the present invention. The present invention is not limited to the following examples and the like, and it goes without saying that the present invention can be implemented in various ways without departing from the gist of the present invention.
[Example 1]
An example in which the invention of the present application is applied to a pachinko machine that is a gaming machine will be described as a first embodiment.
Note that the configuration of the pachinko machine other than the main control board, the payout control board, and the power supply board, which will be described below, is in accordance with a publicly known technique, and thus illustration and description thereof are omitted.

As shown in FIG. 1, the main control board 10 is equipped with a game control CPU 11, a ROM 12, a RAM 13, and the like.
On the main control board 10, a game ball detection signal from a detection switch installed in a prize opening, a passage opening provided in the game board, various areas provided in the prize opening, and a switch provided in the frame device A signal from a class is input.

  The game control CPU 11 operates in accordance with a program stored in the ROM 12 and manages the progress of the game. Specifically, based on the above detection signals, etc., a lottery such as jackpots is performed, the display of a special symbol display device that displays the results of the jackpot lottery is controlled, and opening and closing of variable prize openings such as attackers and electric tulips are opened and closed. Control, generate various commands and data related to the progress of the game, and output to the sub-control board including the payout control board 20.

The payout control board 20 is equipped with a payout control CPU 21, ROM 22, RAM 23, and the like.
The payout control CPU 21 operates in accordance with a program stored in the ROM 22 and operates a payout device (not shown) in accordance with commands and data sent from the main control board 10 to play game balls as prize balls. To pay out. When a prepaid card unit (CR unit) is attached to the pachinko machine, a ball lending dispensing device is controlled to pay out a game ball as a lending ball.

  The power supply board 30 is supplied with AC 24V power from the outside of the pachinko machine. The power supply board 30 rectifies this to, for example, DC 12V, and the main control board 10, the payout control board 20, and other parts of the pachinko machine. Power to

The power supply board 30 is provided with a RAM clear switch 31, a power supply detection circuit 32, a power failure detection circuit 33, and the like.
When the RAM clear switch 31 is turned on, the power supply board 30 outputs a RAM clear signal. This signal is input to the main control board 10.

  The power supply detection circuit 32 detects the presence / absence of power supply from the power supply board 30 to the main control board 10 and the payout control board 20 and outputs a power supply detection signal when power is supplied from the power supply board 30 to the main control board 10 and the like. This signal is input to the main control board 10 and the payout control board 20 as a reset signal.

  The power failure detection circuit 33 is a circuit for detecting a power failure, and outputs a power failure detection signal when a power failure is detected (strictly, when the voltage supplied from the power supply board 30 to the main control board 10 or the like falls below a threshold value). . This signal is input to the main control board 10.

  The power supply detection circuit 32 and the power failure detection circuit 33 may be provided on a board other than the power supply board 30. Power supply from the power supply board 30 to the payout control board 20 may be performed via the main control board 10. The power failure detection signal may be given to the payout control board 20 via the main control board 10.

Next, the operation of the game control CPU 11 of the main control board 10 will be described.
When the power of the pachinko machine is turned on (or restored from a power failure), the power supply detection circuit 32 detects power supply by the power supply substrate 30 and outputs a power supply detection signal. When this power supply detection signal is input to the main control board 10 as a reset signal, a security check program is activated and a security check of the game control CPU 11 is executed (security check execution means 1).

After this security check, the game control CPU 11 executes power-on processing, main processing, remaining processing, power failure processing, and the like shown in FIGS.
The power supply detection signal (reset signal) is also input to the payout control board 20. When this reset signal is input, the security check program operates to execute a security check of the payout control CPU 21 (security check execution means 2). The payout control CPU 21 executes the power-on process after the security check is completed (start-up process execution means 2), and then performs the normal process.

Hereinafter, the operation of the game control CPU 11 of the main control board 10 will be described in detail.
As shown in FIG. 2, after the security check by the security check execution means 1 is completed, the game control CPU 11 first executes a power-on process (activation process execution means 1).

  Here, after the RAM initial setting process (S1) is performed, it is determined whether or not the RAM clear signal is input, that is, whether or not the RAM is erased (S2). If the determination is affirmative, the RAM is erased (S6).

If the determination is negative, it is determined whether or not the RAM guarantee value is 1 (S3).
If the RAM guarantee value is not 1 (S3: NO), RAM erasure (S6) is performed.
If the RAM guarantee value is 1 (S3: YES), a SUM value creation process (S4) is performed to determine whether the SUM value is 0 (S5).

If the SUM value is not 0 (S5: NO), RAM erase (S6) is performed.
If the SUM value is 0 (S5: YES), a power recovery process (S7) is performed.
Execution of S6 or S7 ends the power-on process, and the remaining process starts.

Here, interrupts are prohibited (S8), and it is determined whether the NMI flag is 0 (S9).
If the NMI flag is 0 (S9: YES), the initial value random number update process 1 (S10), the initial value random number update process 2 (S11), and the initial value random number update process 3 (S12) are executed to cancel the prohibition of interrupt. (S13).

If there is an INT interrupt during the remaining process, the interrupt prohibition is canceled (S13), and then the process jumps to the interrupt (INT) process shown in FIG.
In this process, various random numbers used for jackpot lottery etc. are updated (S21), the count of the timer is updated (S22), and a game ball detection signal and a frame device from a detection switch installed at a winning opening etc. (S23), a special symbol game process (S24) related to the jackpot lottery and the execution of the jackpot game, the normal symbol lottery and the normal symbol related to the control of the electric utility For game processing (S25), presentation control command transmission processing to sub-control board that controls display of presentation images, lighting, voice output, etc. (S26), display control of special symbol display device and opening / closing control of variable prize opening The data output process (S27) is performed.

  Then, the interrupt counter is incremented by 1 (S28), and it is determined whether or not the interrupt count exceeds a predetermined number (S29). Since the INT interrupt is periodically performed by a timer, counting the number of interrupts is the same as measuring the elapsed time after the power-on process (see FIG. 2) is performed. That is, the processes of S28 to S29 correspond to timer means.

  If the number of interruptions exceeds the predetermined number (S29: YES), that is, “the time measurement by the timer means has passed the predetermined time”. This predetermined time (predetermined number of times) is set to be equal to or longer than the time required for the security check of the game control CPU 11 subtracted from the time required for the security check of the payout control CPU 21.

  If the number of interruptions exceeds the predetermined number (S29: YES), a prize ball command is transmitted to the payout control board 20 (S30). The prize ball command is a command generated based on a game ball detection signal (see S23) from a detection switch installed at a winning opening, and has a data configuration that can specify the number of payouts (number of prize balls). This corresponds to the payout data.

When a prize ball command is sent from the main control board 10, the payout control CPU 21 of the payout control board 20 activates the payout device to pay out the number of prize balls specified by the prize ball command.
When the number of interruptions does not exceed the predetermined number (S29: NO), the prize ball command generated as described above is stored in, for example, the RAM 13 (S31). Here, instead of storing the prize ball command, the number of prize balls may be stored. In that case, a plurality of winning ball numbers may be added and stored.

When S30 or S31 is executed, the process returns from the interrupt (INT) process to the remaining process.
On the other hand, when the power failure detection circuit 33 detects a power failure and outputs a power failure detection signal, and this signal is input to the main control board 10, an NMI signal is given to the game control CPU 11.

When there is an NMI signal during the remaining process, the game control CPU 11 immediately interrupts the current program and jumps to the interrupt (NMI) process shown in FIG.
In this interrupt (NMI) process, the address of the current program is stored in the register (S35), the NMI flag is set to 1 (S36), and the remaining process is resumed from the address stored in the register (S37). ).

  As shown in FIG. 2, when S9 is executed in the remaining process after resumption, since the NMI flag is 1 (S9: NO), the process proceeds to a power failure process and a SUM value is created (S14). The guaranteed RAM value is set to 1 (S15), and RAM writing is prohibited by the RAM write protect process (S16).

  If power is restored after the power failure process is performed in this way, the power-on process is performed. However, since the RAM guarantee value is 1 (S3: YES), the above-described S4 and S5 are executed. Further, since the SUM value is not 0 (S5: YES), the power supply recovery process (S7) is performed.

  If there is an INT interrupt during the remaining process executed after the power-on process, the interrupt prohibition is canceled (S13) and the process jumps to the interrupt (INT) process and performs this process. If there is a prize at the prize opening after the completion of the, the main control board 10 can store the prize by detecting that there is a prize, although it cannot be paid out immediately. With respect to the detected winning, since the prize ball command is transmitted from the main control board 10 to the payout control board 20 after the time required for the payout control CPU 21 of the payout control board 20 to rise, the prize ball command is paid out. The substrate 20 is not missed. Therefore, the player does not suffer the disadvantage that the winning ball is not paid out even though the player has won.

The operations of the main control board 10 and the payout control board 20 associated with power-on (or power recovery) of the pachinko machine are shown in timing charts as shown in FIGS.
5 shows the case where the RAM clear switch 31 is not turned on, and FIG. 6 shows the case where the RAM clear switch 31 is turned on. In either case, the reset signal of the power supply detection circuit 32 is sent to the main control board 10. When a security check (required time is 92 ms) of the game control CPU 11 is executed and power-on processing (required time is 4 ms) is executed, normal processing is performed on the main control board 10, and the above-described processing is performed. It is possible to detect and memorize the winning as follows.

  On the other hand, in accordance with the prior art, a delay circuit that delays the timing at which the reset signal from the power supply detection circuit 32 is input to the main control board 10 is provided, and the timing at which normal processing is started in the main control board 10 (game control CPU 11). And the payout control board 20 (payout control CPU 21) are aligned with the timing at which the normal process is started, as shown in FIG. Can be done.

Similarly, according to the prior art, a standby time is provided during the power-on process of the main control board 10 (game control CPU 11), and the timing and payout of the normal process on the main control board 10 (game control CPU 11). Even when the control board 20 (payout control CPU 21) is aligned with the timing at which the normal process is started, as shown in FIG. 8, there is a period in which a winning cannot be detected after the power is turned on for the standby time.
[Example 2]
In the first embodiment, the power failure detection signal and the RAM clear signal are not input to the payout control board 20, but these signals may be input to the payout control board 20 as shown in FIG. The RAM clear switch 31 may be provided on the power supply board 30 (FIG. 9A) or on the main control board 10 (FIG. 9B).

  As illustrated in FIG. 9, when the RAM clear signal is input from the main control board 10 to the payout control board 20, the startup process executed by the game control CPU 11 of the main control board 10 will be described with reference to FIGS. In addition, about the same process as FIG. 2, FIG. 3, the description is abbreviate | omitted using the same code | symbol.

  As shown in FIG. 10, if the RAM is erased (S2: YES), the payout control CPU 21 of the payout control board 20 performs a delay process (S41) to transmit a RAM clear signal after starting the normal process. Thereafter, a RAM clear signal is transmitted (S42), and RAM erasure (S6) is performed. Then, the RAM clear flag is set to 1 (S43).

  Residual processing (S8 to S13) and power failure processing (S14 to S16) are the same as those in the first embodiment (FIG. 2). Further, the interrupt (NMI) processing when there is an NMI signal during the residual processing is the same as that in the first embodiment (FIG. 4).

If there is an INT interrupt during the remaining process, the interrupt (INT) process executed after the interrupt prohibition is canceled (S13) is as shown in FIG.
S21 to S28 are the same as those in the first embodiment.

In this embodiment, following S28, it is determined whether or not the RAM clear flag is 0 (S45).
If the determination is affirmative, it is determined whether or not the number of interrupts exceeds a predetermined number a (S46). The determination process of S45 has the same role as S29 of the first embodiment, and corresponds to timer means for measuring the elapsed time after the power-on process (see FIG. 10) is performed.

  On the other hand, when a negative determination is made, that is, when the RAM clear switch 31 is turned on, it is determined whether or not the number of interruptions is equal to or less than the predetermined number b (S47). This process is also a kind of timer means, and measures the elapsed time after the power-on process (FIG. 10) is performed.

  If the number of interruptions is less than or equal to the predetermined number b (S47: YES), the time required for rising of the payout control CPU 21 has not elapsed, so S31 is executed, and if the number of interruptions exceeds the predetermined number of times b (S47). : NO), since the payout control CPU 21 is up, S30 is executed.

  In the second embodiment, the operations of the main control board 10 and the payout control board 20 when the RAM clear switch 31 is turned on at power-on (or power recovery) are shown in a timing chart as shown in FIG. When the RAM clear switch 31 is not turned on, the operation is the same as that in the first embodiment (FIG. 5).

  When the RAM clear switch 31 is turned on when the power is turned on to execute the RAM clear, the operation of the RAM clear switch 31 should be performed by a game clerk, and it is unlikely that a game ball exists on the game board surface. There is no need to execute the normal processing of the game control CPU 11 early, and there is no problem even if a delay time is provided.

Even when configured as in the present embodiment, the same effects as in the first embodiment can be obtained.
[Example 3]
In the first embodiment, the power supply detection signal is input from the power supply board 30 to the payout control board 20, but as shown in FIG. 13, this signal can be input from the main control board 10 to the payout control board 20. . In this case, the power supply detection circuit 32 may be provided on the power supply board 30 (FIGS. 13A to 13C), or may be provided on the main control board 10 (FIG. 13C). The RAM clear switch 31 and the RAM clear signal are as described in the second embodiment.

  As illustrated in FIG. 13, when a power supply detection signal (reset signal) and a RAM clear signal are input from the main control board 10 to the payout control board 20, the startup process executed by the game control CPU 11 of the main control board 10 is shown in FIG. 14. As shown. That is, the power supply signal transmission process (S49) is performed prior to the RAM initial setting process (S1), and the power supply detection signal (reset signal) is transmitted to the payout control board 20 here. The following processing is the same as that of the second embodiment including the interrupt (INT) processing and the interrupt (NMI) processing.

The operations of the main control board 10 and the payout control board 20 associated with power-on (or power recovery) in the third embodiment are shown in timing charts as shown in FIGS.
FIG. 15 is a timing chart when the RAM clear switch 31 is not turned on. The payout control CPU 21 of the payout control board 20 starts a security check in response to a reset signal from the main control board 10. For this reason, the timing at which the payout control CPU 21 starts the normal process is delayed by 96 ms in comparison with the first embodiment (FIG. 5). However, by setting the predetermined number a of S46 and the predetermined number b of S47 shown in FIG. 11 corresponding to this delay, a negative determination is made in S46 or S47 until the payout control CPU 21 starts normal processing. Therefore, as described in the first embodiment, there is no possibility that the player suffers a disadvantage that the winning ball is not paid out even though the player has won a prize.

  FIG. 16 is a timing chart when the RAM clear switch 31 is turned on. As described in the second embodiment, when the RAM clear switch 31 is turned on when the power is turned on to execute the RAM clear, the RAM clear is performed. The operation of the switch 31 should be performed by a game clerk, and it is unlikely that there is a game ball on the game board surface, so there is no need to execute the normal processing of the game control CPU 11 early, and a delay time is provided. There is no problem.

  Even when configured as in the present embodiment, the same effects as in the first embodiment can be obtained.

The block diagram of the principal part of the pachinko machine of Example 1. FIG. The flowchart of the starting process which the game control CPU of Example 1 performs. The flowchart of the interruption (INT) process which the game control CPU of Example 1 performs. The flowchart of the interruption (NMI) process which the game control CPU of Example 1 performs. 6 is a timing chart of the operation of the main control board and the payout control board when the pachinko machine according to the first embodiment is turned on (without RAM clear). 6 is a timing chart of operations of the main control board and the payout control board when the power of the pachinko machine according to the first embodiment is turned on (with RAM clear). The timing chart (the 1) of operation | movement of the main control board and payout control board accompanying the power activation of the pachinko machine of a prior art example. The timing chart (the 2) of operation | movement of the main control board and payout control board accompanying power activation of the pachinko machine of a prior art example. The block diagram of the principal part of the pachinko machine of Example 2. FIG. The flowchart of the starting process which the game control CPU of Example 2 performs. The flowchart of the interruption (INT) process which the game control CPU of Example 2 performs. 9 is a timing chart of operations of the main control board and the payout control board when the power of the pachinko machine of Embodiment 2 is turned on (with RAM clear). The block diagram of the principal part of the pachinko machine of Example 3. FIG. The flowchart of the starting process which the game control CPU of Example 3 performs. 9 is a timing chart of operations of the main control board and the payout control board when the pachinko machine according to the third embodiment is turned on (without RAM clear). 9 is a timing chart of operations of the main control board and the payout control board when the power of the pachinko machine of Embodiment 3 is turned on (with RAM clear).

Explanation of symbols

10 ... Main control board,
11 ... Game control CPU,
20 ... Dispensing control board,
21 ... Dispensing control CPU,
30 ... power supply board,
31 ... RAM clear switch,
32... Feed detection circuit,
33: Power failure detection circuit.

Claims (4)

A main control board equipped with a CPU (hereinafter referred to as “game control CPU”) that controls the progress of the game;
A payout control board equipped with a CPU (hereinafter referred to as “payout control CPU”) for controlling a payout device for paying out game media;
A power supply board for supplying power to the main control board and the payout control board;
In a gaming machine comprising a power supply detection circuit for detecting the presence or absence of the power supply by the power supply board,
A CPU having a higher processing speed than the payout control CPU is mounted on the main control board as the game control CPU,
On the main control board,
Security check execution means 1 for executing a security check of the game control CPU when notified that the power supply detection circuit has detected the power supply;
A startup process execution means 1 for executing a power-on process after the security check by the security check execution means 1 is completed;
Timer means for starting timing during the power-on process by the startup process execution means 1;
Game processing execution means for executing normal processing consisting of the main processing and the remaining processing after the power-on processing by the startup processing execution means 1 is completed,
The main control board
Even when the time measured by the timer means passes a predetermined time set in advance, the normal time processing is executed and the data obtained by the normal time processing is stored,
A gaming machine characterized in that payout data related to payout of the game medium in the stored data is transmitted to the payout control board after the time measured by the timer means passes the predetermined time. The gaming machine according to claim 1,
The payout control board includes
Security check execution means 2 for executing a security check of the payout control CPU when notified that the power supply detection circuit has detected the power supply;
A startup process execution means 2 for executing a power-on process after the security check by the security check execution means 2 is completed,
The predetermined time is set to be equal to or more than a time obtained by subtracting the time required for the security check of the game control CPU by the security check execution means 1 from the time required for the security check of the payout control CPU by the security check execution means 2. A gaming machine characterized by that. In the gaming machine according to claim 1 or 2,
The power supply detection circuit is provided on the power supply board,
The game machine according to claim 1, wherein the power supply board transmits a power supply detection signal to the main control board and the payout control board when the power supply detection circuit detects the power supply. In the gaming machine according to claim 1 or 2,
The power supply detection circuit is provided on the power supply board,
The power supply board transmits a power supply detection signal to the main control board when the power supply detection circuit detects the power supply,
When receiving the power supply detection signal, the main control board transmits a signal notifying that the power supply detection circuit has detected the power supply to the payout control board before executing the normal processing. A gaming machine.

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