JP2008182727A - Transmission circuit, reception circuit, differential interface apparatus, display controller and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transmission circuit, a reception circuit, a differential interface apparatus and a display controller which can obtain a transfer rate capable of coping with the increase of a display data amount caused by the extension of a screen size of a liquid crystal panel in future with low power consumption, and to provide a display unit and an electronic device using the display controller. <P>SOLUTION: The transmission circuit comprises: a means which is connected to a receiving means for converting a current of a differential signal line into a voltage via the differential signal line, and transmits transmission data by controlling currents of signal lines of the differential signal line in accordance with the transmission data; and a means which stops power supply to the means for transmitting the transmission data. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a transmission circuit, a reception circuit, a differential interface device, a display controller, a display unit using the same, and an electronic apparatus.

  With the recent development of communication technology and mounting technology, not only character characters such as numbers and characters but also various data that is highly informative for users such as still images and moving images can be displayed on the display unit of portable electronic devices. became.

  Various data formats have been proposed for data displayed on such electronic devices. For example, taking a mobile phone as an example, a technique for receiving or transmitting display data compressed and encoded according to the MPEG (Moving Picture Experts Group) standard has been proposed.

  In this case, for example, a liquid crystal panel is provided as a display unit of the mobile phone. The liquid crystal panel is driven to display based on display data corresponding to a moving image or a still image by a display controller.

  However, in order to display a moving image without a sense of incongruity on the liquid crystal panel, it is necessary to supply display data at a high transfer rate to a display controller for driving the liquid crystal panel.

  Such display data transfer has been performed by an interface using a CMOS (Complimentary Metal Oxide Semiconductor) circuit that can be realized at low cost. However, since the current consumption of this CMOS circuit increases in proportion to the frequency, when trying to realize a transfer rate required to display a moving image without a sense of incongruity, it is necessary to use a portable electronic device such as a mobile phone. Battery drive time will be shortened. In addition, with an interface using a CMOS circuit, it is difficult to realize a transfer rate that can cope with future increases in the screen size of the liquid crystal panel and an increase in the number of gradation bits.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to reduce a transfer rate that can cope with an increase in the amount of display data due to a future increase in the screen size of a liquid crystal panel. It is an object of the present invention to provide a transmission circuit, a reception circuit, a differential interface device, a display controller, a display unit using the same, and an electronic device that can be realized with power consumption.

  In order to solve the above-mentioned problems, the present invention is connected to a receiving means for converting a current of a differential signal line into a voltage via the differential signal line, and each signal line of the differential signal line according to transmission data. The present invention relates to a transmission circuit including means for controlling the current to transmit the transmission data and means for stopping power supply to the means for transmitting the transmission data.

  In the transmission circuit according to the present invention, the means for transmitting the transmission data includes a current source, a means for causing a current from the current source to flow through each signal line of the differential signal line in accordance with the transmission data, Means for drawing a current from each signal line of the differential signal line according to transmission data, and the signal lines of the differential signal line may be connected to each other via a terminating resistor.

  Moreover, in the transmission circuit according to the present invention, the means for transmitting the transmission data includes a current source and a means for causing a current from the current source to flow through each signal line of the differential signal line in accordance with the transmission data. Each signal line of the differential signal line may be connected to the low potential side power source among the high potential side power source and the low potential side power source via the termination resistor.

  Further, in the transmission circuit according to the present invention, the means for transmitting the transmission data includes a current source and a means for drawing current from each signal line of the differential signal line according to the transmission data, and via a termination resistor. Then, each signal line of the differential signal line may be connected to the high potential side power source among the high potential side power source and the low potential side power source.

  Further, the present invention is connected to the transmission means for transmitting the transmission data by controlling the current of each signal line of the differential signal line according to the transmission data, and the differential signal line The present invention relates to a receiving circuit including means for converting current into voltage and means for stopping power supply to the means for converting current into voltage.

  According to another aspect of the present invention, there is provided a differential signal line, the transmission circuit according to any one of the above that is connected to the differential signal line, and the reception circuit that is connected to the transmission circuit via the differential signal line. And a differential interface device including

  The present invention also provides a display controller for driving the display unit based on the display data, the storage means for storing display data for at least one frame, and dummy blanking provided before the display unit starts scanning. The above-described receiving circuit for receiving display data to be written to the storage means during the period, and display data writing for writing the display data received by the receiving circuit to the storage means from the dummy blanking period And a display controller including display drive means for driving the display unit based on display data read from the storage means.

  In the display controller according to the present invention, the means for stopping the power supply to the means for converting the current into voltage until the next display data is received after the reception circuit completes the reception of the display data. The power supply may be stopped for a given period of time.

  In the display controller according to the present invention, the means for stopping the power supply to the means for converting the current into voltage writes the display data received by the receiving circuit to the storage means, and then the next display data is obtained. The power supply may be stopped until it is received.

  According to another aspect of the invention, there is provided a panel having an electro-optic element driven by a plurality of first electrodes and a plurality of second electrodes, and the display controller according to any one of the above, which drives the plurality of first electrodes; The present invention relates to a display unit having a scanning drive driver that scans and drives the plurality of second electrodes.

  The present invention also relates to an electronic device having the display unit described above.

  The present invention also provides a display controller for driving the display unit based on the display data, the storage means for storing display data for at least one frame, and dummy blanking provided before the display unit starts scanning. First display data receiving means for receiving display data to be written to the storage means from the period and display data received by the first display data receiving means from the dummy blanking period to the storage Display data writing means for writing to the means, and display driving means for driving the display unit based on the display data read from the storage means.

  Here, the display data refers to data necessary for driving the display unit such as moving image data, still image data, and display control signals for these image data.

  In the present invention, a display controller having storage means for storing display data for one frame and driving the display section based on the display data stored in the storage means is provided before the display section starts scanning. Further, display data to be written to the storage means is received from the dummy blanking period and sequentially written to the storage means. In this way, display data of an image displayed in each frame can be quickly received and written to the storage means. Therefore, even when the amount of display data increases as the screen size of the display unit increases or the number of gradation bits increases, the transfer time required for the transfer can be secured.

  According to the present invention, the display data writing means stores the display data corresponding to the scan line in the storage means before the display data corresponding to the given scan line is read from the storage means in the frame. It is characterized by writing.

  According to the present invention, when display driving is performed in a given scan line unit in the frame, display data in the corresponding frame is written in the storage unit before the scan line is read. In the frame in which the display data is updated, it is possible to avoid the phenomenon that the display data of the previous frame is displayed and the moving image is displayed with a sense of incongruity.

  Further, according to the present invention, the dummy blanking period is provided before the vertical scanning of the display unit is started, and the first display data receiving unit is provided for one frame of the frame from the dummy blanking period. The display data is received.

  In the present invention, a dummy blanking period is provided before the vertical scanning of the display unit is started, and display data for one frame of the frame is received from the dummy blanking period. Thereby, at the start of scanning of the first scanning line, display data corresponding to the scanning line is written in the storage means, and as long as attention is paid to each scanning line in the frame, writing and reading to the storage means are performed simultaneously. The timing generation can be simplified.

  In the present invention, when the display data amount for one frame is D and the transfer data rate of display data received by the first display data receiving means is R, the dummy blanking period is at least D / It is characterized in that it is provided only for the period represented by R.

  In the present invention, the dummy blanking period is provided only for the display data transfer time (D / R) for at least one frame, so that the display data for one frame is stored at the start of scanning of the first scan line. Written in the means. Therefore, when display driving for the first scanning line and thereafter is performed, writing and reading to the storage unit are not performed simultaneously. Thereby, current fluctuation in the storage means due to simultaneous writing or reading can be reduced, and as a result, the noise resistance of the storage means can be improved.

  According to the present invention, the dummy blanking period is provided before the horizontal scanning of the display unit is started, and the first display data receiving means displays the display data of the scanning line from the dummy blanking period. Is received.

  In the present invention, a dummy blanking period is provided before the start of scanning of each horizontal scanning line of the display unit, and display data for the scanning line is received from the dummy blanking period before the start of each horizontal scanning. . Thereby, at the start of scanning of each scanning line, display data corresponding to the scanning line is written in the storage means, and writing and reading to the storage means are not performed at the same time, thereby simplifying timing generation. Will be able to.

  Further, the present invention provides the first display data receiving means only during a given period after the reception of display data by the first display data receiving means until the next display data is received. Receiving operation stopping means for stopping the operation.

  Here, the period from the completion of reception of display data by the first display data receiving means to the reception of the next display data depends on the transfer timing of the display data. For example, when the display data is received for each scanning line, the period until the next display data is received. When the display data is received for each frame, the display data is received in the next frame. This refers to the period until reception, and when display data is received after a given frame, it means the period until display data is received in the next frame after a given frame.

  In the present invention, as described above, the display data is received during the dummy blanking period, and the reception operation is stopped for a given period from the completion of reception until the next reception of display data. I did it. In this way, it is possible to reduce power consumption by starting reception of necessary display data at an early stage and stopping the reception operation when reception is completed promptly.

  Further, in the invention, the first display data receiving means includes a differential amplifier that amplifies a differential signal of display data received via a differential pair of signal lines, and the reception operation stopping means includes the After the display data received by the first display data receiving means is written into the storage means, the operation of the differential amplifier is stopped until the next display data is received.

  In the present invention, the display data received via the differential pair of signal lines is received by the differential amplifier, and after this is written in the storage means, until the next display data is received, The operation of the differential amplifier was stopped. As a result, it is possible to reduce current consumption due to the stop of the differential amplification operation during the period in which display data is not received.

  Further, in the invention, the first display data receiving means includes a differential amplifier that amplifies a differential signal of display data received via a differential pair of signal lines, and the reception operation stopping means includes the After the display data received by the first display data receiving means is written to the storage means, the current of the current source of the differential amplifier is stopped or limited until the next display data is received. Features.

  In the present invention, the display data received via the differential pair of signal lines is received by the differential amplifier, and after this is written in the storage means, until the next display data is received, The current of the current source of the differential amplifier is stopped or limited. As a result, it is possible to reduce current consumption due to the stop of the differential amplification operation during the period in which display data is not received.

  The present invention also provides a display controller for driving the display unit based on display data, the storage means for storing display data for at least one frame, and the first display data for receiving display data with a bit width K. Receiving means, first bit width conversion means for converting display data of bit width K received by the first display data receiving means to bit width L, and display data via a parallel bus of bit width N Second display data receiving means for receiving, second bit width converting means for converting display data of bit width N received by the second display data receiving means into bit width L, and the first or second Display data writing means for writing the display data of the bit width L converted by the bit width conversion means of 2 into the storage means, and based on the display data read from the storage means There are, characterized in that it comprises a display driving means for displaying driving the display unit.

  In the present invention, at least the bit width of the display data received via the parallel bus is enlarged and written to the storage means in units of the bit width. Even if it is necessary to write display data to the means at high speed, the writing frequency can be lowered. This is more effective when the display data necessary for displaying one frame is increased due to an increase in the screen size of the display unit or an increase in the number of gradation bits. Therefore, it is possible to use a low-cost process for manufacturing the memory means, and to suppress an increase in power consumption.

  The display unit according to the present invention includes a panel having an electro-optic element driven by a plurality of first electrodes and a plurality of second electrodes, and the display according to any one of the above that drives the plurality of first electrodes. It has a controller and a scanning drive driver which scans and drives the plurality of second electrodes.

  According to the present invention, it is possible to provide a display unit that can display a moving image without a sense of incongruity even when the amount of display data increases due to an increase in the screen size of the display unit or an increase in the number of gradation bits.

  A display unit according to the present invention includes a panel having an electro-optic element driven by a plurality of first electrodes and a plurality of second electrodes, and the display controller for driving the plurality of first electrodes. And a scan driver that scans the plurality of second electrodes, and a display data supply circuit that supplies the display data to the display controller.

  In the present invention, since the display data supply circuit for supplying the display data is mounted on the display unit, the interface design between the display data supply circuit and the display controller is omitted from the user, and the man-hour and the number of parts are reduced. Can contribute to low-cost development.

  According to the present invention, when the display data supply circuit changes a current source and a current supplied from the current source based on display data, the display data supply circuit supplies a differential signal corresponding to the change to the display controller. The reception operation stopping means includes a differential driver and differential driver control means for controlling the operation of the current source until the next display data is supplied after the display data is supplied to the display controller. The current of the current source of the differential amplifier is stopped or limited, and the differential driver control means stops or limits the current of the current source.

  According to the present invention, high-speed transfer of display data is realized via a differential pair of signal lines, and current consumption on the transmission / reception side can be reduced when transfer is unnecessary. As a result, it is possible to provide a display unit that suppresses an increase in power consumption associated with the transfer of display data, which increases due to an increase in the screen size of the display unit, and achieves both a high transfer rate and low consumption.

  An electronic apparatus according to the present invention includes any one of the display units described above.

  According to the present invention, there is provided an electronic device capable of displaying various images such as moving images with low power consumption even when the display data amount for one frame is increased by increasing the screen size or the number of gradation bits. can do.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

<First Embodiment>
1. Electronic Device FIG. 1 shows an example of the outline of the configuration of an electronic device to which the display controller according to the first embodiment is applied.

  The electronic apparatus includes an MPU (Micro Processor Unit) (display data supply circuit in a broad sense) 10 and a display unit 20. The MPU 10 supplies one or both of moving image data and still image data to the display unit 20. The display unit 20 drives the display unit based on the display data supplied from the MPU 10. Here, the display data refers to data necessary for driving the display unit such as moving image data, still image data, and display control signals for these image data.

  The display unit 20 includes a matrix panel having electro-optical elements, such as a color liquid crystal panel (display section in a broad sense) 22, an X driver IC (display controller in a broad sense) 24 with a built-in RAM that drives the liquid crystal panel 22; And a Y driver IC 26 for scanning.

  The matrix panel 22 only needs to use a liquid crystal or other electro-optical element whose optical characteristics change with voltage application. The liquid crystal panel 22 can be constituted by, for example, a simple matrix panel. In this case, a first substrate on which a plurality of segment electrodes (first electrodes) are formed and a second substrate on which common electrodes (second electrodes) are formed. Liquid crystal is sealed between the substrate. The liquid crystal panel 22 may be an active matrix panel using a three-terminal element such as a thin film transistor (TFT) or a thin-film diode (TFD), or a two-terminal element. These active matrix panels also have a plurality of signal electrodes (first electrodes) driven by the X driver IC 24 and a plurality of scanning electrodes (second electrodes) driven by the Y driver IC 26.

  In the electronic apparatus shown in FIG. 1, the MPU 10 and the display unit 20 are connected via at least a parallel interface (hereinafter referred to as IF) signal line and a differential IF signal line. In FIG. 1, in addition to these, connection is also made via a serial IF signal line.

  The parallel IF signal line includes an 8-bit data bus of D7 to D0, and display commands and still image data are transmitted and received through the 8-bit data bus. In FIG. 1, for example, the command / data identification signal is transmitted / received via the parallel IF control signal line provided separately from the 8-bit data bus, thereby transferring the data transferred via the 8-bit bus D7-D0. Can be identified as a display command or still image data. The display command is a command for performing display control such as setting of a display area of a liquid crystal panel (setting of a still picture display area and setting of a moving picture display area). Still image data is display data for displaying a still image in a display area set by a display command. The parallel IF control signal line transmits / receives other inverted reset signal XRES, inverted chip select signal XCS, inverted read signal XRD, inverted write signal XWR, and the like. The X driver IC 24 performs writing control of still image data to the display data RAM 28 by these control signals.

  The differential IF signal line includes a differential pair of signal lines. For example, each of the 6-bit R, G, and B video signals that are converted into differential signals through the differential pair of signal lines, synchronization A clock or the like is transmitted / received. At this time, the power control signal PS is transmitted / received via the differential IF control signal line provided separately from the signal line of the differential pair. The X driver IC 24 and the MPU 10 perform differential IF operation control by the power control signal PS. The X driver IC 24 takes in the differential signal in synchronization with the synchronous clock and writes it into the display data RAM 28.

  The serial IF signal line transmits, for example, moving image data, which are 6-bit R, G, and B signals, one bit at a time. Similarly, a clock signal CLK, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync (or a composite signal H / Vsync of a horizontal / vertical synchronization signal) and the like are also supplied. The X driver IC 24 writes moving image data in the display data RAM 28 in synchronization with the clock signal CLK and each synchronization signal.

  The X driver IC 24 displays data stored in the display data RAM 28 at a given frame frequency (for example, 60 frames per second (hereinafter abbreviated as f / s), 30 f / s, 15 f / s, etc.). Data is read in a given display unit (for example, one scanning line unit or a plurality of scanning line units), and the liquid crystal panel 22 is driven to display based on the read display data.

  In FIG. 1, the MPU 10 and the display unit 20 are connected via respective interfaces. However, the MPU 10 may be included in the display unit 20. In this case, the MPU 10 directly transmits / receives display data to / from the X driver IC 24 via the IF described above.

  FIG. 2 shows an example in which the MPU 10 and the display unit 20 shown in FIG.

  The MPU 10 shown in FIG. 2 has a central processing unit (hereinafter abbreviated as CPU) 12 that controls the cellular phone 30. The CPU 12 includes a still image memory 14, a DSP (Digital Signal Processor). 16 is connected. In addition, a moving image processing memory 18 is connected to the DSP 16. Further, the MPU 10 includes a serial IF circuit 40, a differential IF circuit 42, and a parallel IF circuit 44 that realize an IF function with the X driver IC 24 shown in FIG.

  The cellular phone 30 is provided with a modulation / demodulation circuit 34 that demodulates a signal received via the antenna 32 or modulates a signal transmitted via the antenna 32. From the antenna 32, for example, moving image data encoded according to the MPEG (Moving Picture Experts Group) layer IV standard can be transmitted and received.

  The mobile phone 30 is provided with, for example, a digital video camera 36 and can capture moving image data. Operation information necessary for data transmission / reception with the mobile phone 30 and photographing with the digital video camera 36 is input via the operation input unit 38.

  For example, the CPU 12 determines the display area of the liquid crystal panel 22 from the moving image information. The moving image displayed in the determined display area is supplied from the antenna 32 or the digital video camera 36, for example. The signal input from the antenna 32 is demodulated through the modulation / demodulation circuit 34 and processed by the DSP 16. The DSP 16 is connected to the moving image processing memory 18 and expands compressed data input via the antenna 32 and the modulation / demodulation circuit 34 and decodes data encoded according to the MPEG layer IV standard. Data transmitted through the modem circuit 34 and the antenna 32 is compressed by the DSP 16 and is encoded when encoded and transmitted according to the MPEG layer IV standard. As described above, the DSP 16 can have a function as an MPEG decoder, encoder, for example, layer IV.

  The DSP 16 also receives a signal from the digital video camera 36, and the signal input from the antenna 32 or the digital video camera 36 is processed into an RGB signal by the DSP 16 and supplied to the display unit 20.

  The moving image data generated by the DSP 16 is supplied to the display unit 20 via either the serial IF signal line via the serial IF circuit 40 or the differential IF signal line via the differential IF circuit 42. The CPU 12 may determine which IF signal line the moving image data is transmitted / received according to the size of the moving image display area.

  On the other hand, the CPU 12 uses commands for still images displayed on the liquid crystal panel 22 and still image data in parallel using the still image memory 14 as necessary based on information from the operation input unit 38. The data is output to the display unit 20 via the parallel IF signal line via the IF circuit 44.

  For example, the moving image is movie information distributed via the Internet, information for reserving the theater ticket is displayed as a still image, and ticket reservation is performed based on information from the operation input unit 38. In this case, the CPU 12 further controls transmission of reservation information, for example, via the modem circuit 34 and the antenna 32. Further, the CPU 12 can control transmission of moving image information captured by the digital video camera 36 via the modem circuit 34 and the antenna 32 as necessary.

2. X driver IC (display controller)
2.1 Configuration FIG. 3 shows an example of a configuration main part of an X driver IC as a display controller in the first embodiment shown in FIG.

  The X driver IC 24 includes a latch circuit 50, a liquid crystal drive circuit 52, and an LCD controller 54 in addition to the display data RAM 28 described above.

  The LCD controller (display data writing means in a broad sense) 54 controls the entire X driver IC 24 and performs display data write control, read control to the display data RAM 28, and display drive control to the liquid crystal panel.

  The LCD controller 54 performs control for reading display data in a given display unit from the display data RAM 28 at a fixed frame period. Display data read from the display data RAM 28 is latched by the latch circuit 50 in synchronization with a latch signal generated by the LCD controller. The data latched by the latch circuit 50 is converted into a signal having a pulse width corresponding to the gradation value according to the polarity inversion period by the display drive control signal from the LCD controller 54, and is shifted to a voltage corresponding to the voltage of the LCD display system. Are supplied to the segment electrodes SEG1 to SEGn of the liquid crystal panel 22.

  Display data for which display control is performed by the LCD controller 54 and a command for controlling the LCD controller 54 are received via at least the parallel IF and the differential IF. In FIG. 3, in addition to this, it is also received via the serial IF.

  The display data RAM 28 of the X driver IC 24 in the first embodiment has three ports. More specifically, the display data RAM 28 includes a first port for writing moving image data transferred via a serial IF signal line or still image data (display data) transferred via a parallel IF signal line. , Having a second port for writing moving image data (display data) transferred via the differential IF signal line, and a third port for reading the display data to drive the display unit ing.

  The differential IF signal line and the differential IF control signal line are connected to a differential IF circuit (first display data receiving means) 60. The differential IF circuit 60 includes a differential amplifier that amplifies the data signal D (bit width K = 1), which is a differential signal received via the differential pair of signal lines, and the clock signal CLK. Since the configuration of this differential amplifier is known, detailed description thereof is omitted, but the differential signal is amplified based on a change in current supplied from a current source.

  The differential IF circuit 60 includes an input buffer circuit that buffers a power control signal PS transmitted / received via the differential IF control signal line. This input buffer circuit is constituted by a CMOS circuit.

  The data signal D and the clock signal CLK, which are differential signals amplified by the differential amplifier of the differential IF circuit 60, are supplied to the start frame detection circuit 62.

  The start frame detection circuit 62 monitors the bit string of the data signal D received in synchronization with the clock signal CLK, and determines whether the start frame is based on a preset bit pattern. A bit string of the data signal D determined to be a start frame by the start frame detection circuit 62 is a serial-parallel (hereinafter abbreviated as S / P) conversion circuit (first bit width in a broad sense). Conversion means) 64.

  The S / P conversion circuit 64 converts the 1-bit width bit string from the start frame detection circuit 62 into parallel data of 16 bits (bit width L = 16), for example. The parallel data is supplied to the LCD controller 54 and the display data RAM 28 together with a control signal such as a start frame detection timing detected by the start frame detection circuit 62. The parallel data is written to the display data RAM 28 in units of 16 bits (bit width L = 16) via the first port.

  The power control signal PS buffered by the input buffer circuit of the differential IF circuit 60 is supplied to at least the differential amplifier of the differential IF circuit 60. In addition to this, the power control signal PS is also supplied to the start frame detection circuit 62 and the S / P conversion circuit 64 in FIG.

  The differential amplifier of the differential IF circuit 60 amplifies the differential signal based on a change in the current supplied from the current source. The power control signal PS stops or limits the current supplied from the current source. The operation is controlled by going. The start frame detection circuit 62 and the S / P conversion circuit 64 also stop operating at the same timing as the operation control of the differential amplifier by the power control signal PS.

  The serial IF signal line is connected to the serial IF circuit 70. The serial IF circuit 70 buffers the serially input data signal D, clock signal CLK, and inverted chip select signal XCS. The serial IF circuit 70 is configured by a CMOS circuit. When the inverted chip select signal XCS is active, the serially input data signal D received in synchronization with the buffered clock signal CLK is supplied to the S / P conversion circuit 72.

  The S / P conversion circuit 72 converts the serially input data signal D into parallel data of 16 bits (bit width L = 16), for example. The parallel data is supplied to the LCD controller 54 and the display data RAM 28 together with a control signal such as a clock signal CLK. This parallel data is written into the display data RAM 28 in units of 16 bits (bit width L = 16) via the second port.

  The parallel IF signal line and the parallel IF control signal line are connected to a parallel IF circuit (second display data receiving means in a broad sense) 80. The parallel IF circuit 80 buffers, for example, 8-bit (bit width N = 8) parallel data signals D7 to D0, a clock signal ECLK, and other control signals (inverted chip select signal XCS and the like). The parallel IF circuit 70 is configured by a CMOS circuit. When the inverted chip select signal XCS is active, the parallel-input data signals D7 to D0 received in synchronization with the buffered clock signal ECLK are converted into S / P conversion circuits (second bit width conversion means in a broad sense). ) 82.

  The S / P conversion circuit 82 converts the parallel input data signals D7 to D0 into, for example, parallel data of 16 bits (bit width L = 16). The parallel data is supplied to the LCD controller 54 and the display data RAM 28 together with a control signal such as a clock signal ECLK. This parallel data is written into the display data RAM 28 in units of 16 bits (bit width L = 16) via the second port.

  The X driver IC 24 has an input buffer circuit 90 in which an input switching signal for operating only one of the serial IF and the parallel IF is buffered. By this input switching signal, the serial IF circuit 70 and the S / P conversion circuit 72, and the parallel IF circuit 80 and the SP conversion circuit 82 are controlled to operate exclusively.

  Further, the X driver IC 24 has an oscillation circuit (OSC) 94, and the LCD controller 54 outputs a display timing sync (vertical synchronization signal Vsync / horizontal synchronization signal Hsync) based on the oscillation output of the OSC 94.

2.2 Blanking Period The X driver IC 24 as a display controller in the first embodiment includes a display data RAM, reads display data from the display data RAM at a fixed frame period, and drives the display unit for display. For this reason, writing of display data corresponding to the scanning line in the frame needs to be performed prior to reading of the scanning line. In addition, since the amount of display data increases as the screen size increases and the number of gradation bits increases, reception of display data is started early in the frame so as to secure an increasing display data transfer time. Yes.

  In this way, the writing timing of the scanning line in the frame is always earlier than the reading timing, and the timing generation is simplified.

  For this reason, in the first embodiment, a dummy blanking period is provided before the start of each scan, and display data is transferred during the blanking period. This eliminates the need to consider the write timing and read timing described above.

  4A and 4B are explanatory diagrams for explaining the dummy blanking period.

  When the liquid crystal panel is driven for display, it is performed in synchronization with a vertical synchronization signal Vsync indicating the scanning start timing for one frame and a horizontal synchronization signal Hsync indicating the scanning start timing of each scanning line in each frame. More specifically, as shown in FIG. 4A, display driving is sequentially performed in synchronization with the horizontal synchronization signal Hsync from the first scanning line of each frame in synchronization with the falling of the vertical synchronization signal Vsync. become.

  Therefore, when the vertical synchronizing signal Vsync is taken on the vertical axis and the horizontal synchronizing signal Hsync is taken on the horizontal axis, an image for one frame is displayed in the display area 180 shown in FIG. That is, vertical scanning and horizontal scanning of the display unit are started with reference to P shown in FIG.

  Here, if a period in which the vertical synchronization signal Vsync is at “H” level is a dummy vertical blanking period, the region 182 becomes a non-display region. Further, if the period in which the horizontal synchronization signal Hsync is at “H” level is a dummy horizontal blanking period, the region 184 becomes a non-display region.

  Therefore, in synchronization with the rising edge of the vertical synchronization signal Vsync, display data is received at a high transfer rate during the dummy vertical blanking period, and the display data for one frame is written into the display data RAM. In this case, focusing on each scanning line, since writing is always performed prior to reading, display driving of one frame can be performed without considering timing.

  Here, when the display data for one frame is D and the transfer rate is R, as shown in FIG. 5, the dummy vertical blanking period is at least longer than the period represented by D / R. When the reading timing from the display data RAM is started, the writing of the display data of the frame can already be completed. Thereby, writing and reading of the display data RAM having three ports at the same time are not performed, and noise resistance can be improved by reducing current fluctuation in the display data RAM due to reading or writing.

2.3 High-speed transfer control by differential IF The X driver IC 24 as a display controller in the first embodiment as described above transmits and receives moving image data by a differential IF using an operational amplifier. . Unlike the IF using a CMOS circuit, the differential IF can implement a high-speed data transfer rate by transmitting and receiving a signal having a small amplitude by a differential pair. As a result, it is necessary to display a moving image without a sense of incongruity even when the screen size of the liquid crystal panel is increased in the future, so that a transfer rate that cannot be realized by a CMOS circuit is realized, and moving image data can be written in the display data RAM. become.

  In order to realize such a differential IF, a differential driver for driving a differential pair of signals and a differential amplifier for amplifying the differential pair of signals are required. A current source used in the differential IF differential driver and the differential amplifier flows a steady current without depending on the transfer rate. Therefore, when the transfer rate is low, the IF using the CMOS circuit consumes less power. On the other hand, when the transfer rate is high, the power consumption of the IF using the CMOS circuit becomes larger, and the power consumption of the differential IF that consumes power by the steady current can be reduced. In addition, in the case of the differential IF, a transfer rate that cannot be achieved by the IF using the CMOS circuit can be realized.

  Therefore, in the first embodiment, while high-speed display data transfer is performed by the differential IF, the display drive of the liquid crystal panel needs to be performed in synchronization with the vertical synchronization signal or the horizontal synchronization signal. In this case, after the transfer is performed at a high transfer rate, transfer control is performed by stopping the differential IF until the next transfer timing, thereby suppressing an increase in power consumption.

  Hereinafter, the configuration of such a differential IF will be described.

2.3.1 Configuration example of differential IF (first configuration example)
FIG. 6A shows a first configuration example of the differential IF, and FIG. 6B shows an example of operation waveforms in the first configuration example.

  In the first configuration example, a differential driver 100 is provided on the transmission side, and a differential receiver 102 is provided on the reception side, which are connected via signal lines D1 and D2 of a differential pair. The differential driver 100 is configured to be included in the differential IF circuit 42 of the MPU in FIG. Further, the differential receiver 102 is configured to be included in the differential IF circuit 60 in FIG.

  In the differential driver 100 on the transmission side, the p-type (first conductivity type) transistor 104 (differential driver control means in a broad sense) has a power supply VDD (first power supply) connected to the source terminal and a gate terminal. A power control signal PS is supplied. One end of a current source 106 is connected to the drain terminal of the p-type transistor 104.

  The other end of the current source 106 is connected to the source terminals of the p-type transistors 108 and 110.

  The drain terminals of the n-type (second conductivity type) transistors 112 and 114 are connected to the drain terminals of the p-type transistors 108 and 110. The gate terminal of the p-type transistor 108 is supplied with an inverted signal (XD + signal) of the D + signal indicating the + side of the data signal D to be transmitted. A D + signal is supplied to the gate terminal of the p-type transistor 110.

  A ground power supply VSS (second power supply) is connected to the source terminals of the n-type transistors 112 and 114. A D-signal indicating the negative side of the data signal D is supplied to the gate terminal of the n-type transistor 112. The gate terminal of the n-type transistor 114 is supplied with an inverted signal (XD− signal) of the D− signal.

  In the differential driver 100, there are a difference between a connection point ND1 between the drain terminal of the p-type transistor 110 and the drain terminal of the n-type transistor 114, and a connection point ND2 between the drain terminal of the p-type transistor 108 and the drain terminal of the n-type transistor 112. The moving pair signal lines D1 and D2 are connected.

  The differential receiver 102 has a differential amplifier 116. The configuration of the differential amplifier 116 is well known and will not be described. However, when the current from the current source changes in response to the change in the potential of the signal line of the received differential pair, this change is handled. Is designed to generate a voltage.

  The differential amplifier 116 is connected to the power supply VDD via a p-type transistor 118 (in a broad sense, reception operation stopping means). A power control signal PS is supplied to the gate terminal of the p-type transistor 118. When the drain current of the p-type transistor 118 is supplied to the differential amplifier 116 by the power control signal PS, the differential amplifier 116 operates. However, when the drain current is stopped or limited, the operation is stopped. It has become.

  The signal lines D1 and D2 of the differential pair are connected via a termination resistor RL, and the differential amplifier 116 of the differential receiver 102 amplifies the voltage generated at both ends of the termination resistor RL. The amplified signal is buffered by the buffer circuit 120 and supplied to the subsequent circuit as the received signal S1.

  According to such a configuration, in the differential driver 100, the current flowing from the current source 106 to the connection points ND1 and ND2 is changed by the D + signal and the D− signal, and the differential pair of signal lines D1, A voltage is generated across the termination resistor RL via D2. In the differential receiver 102, the differential amplifier 116 amplifies the voltage generated at both ends of the termination resistor RL.

  Therefore, as shown in FIG. 6B, a differential signal having an amplitude of Vs (for example, 300 mV) can be transmitted with Vc (for example, 1.2 V) as the center, thereby enabling higher-speed data transfer. Become. The differential amplifier 116 on the receiving side can be used for a subsequent CMOS circuit by amplifying it, buffering it and converting it to a logic level.

  At this time, in the differential IF shown in FIG. 6 (A), only the display data required for display is transferred at high speed and until the next transfer timing, by the power control signal PS, the transmission side and the reception side. Thus, the operation control can be performed to reduce power consumption.

  FIG. 7 schematically shows changes in current consumption due to the power control signal PS.

That is, when the logic level of the power saving control PS is “L”, the differential driver on the transmission side and the differential receiver on the reception side operate, and a constant current I ₀ from the current source flows. On the other hand, the power control signal P
When the logic level of S is “H”, the operations of the differential driver on the transmission side and the differential receiver on the reception side are stopped, and the current consumption by the constant current source becomes zero.

  Therefore, after the logic level of the power saving control PS is set to “L” and data is transferred at high speed, the logic level of the power saving control PS is set to “H” at time T1, and the transmitting side and the receiving side are stopped. , Increase in power consumption can be suppressed.

(Second configuration example)
FIG. 8A shows a second configuration example of the differential IF, and FIG. 8B shows an example of operation waveforms in the second configuration example.

  In the second configuration example, a differential driver 130 is provided on the transmission side and a differential receiver 132 is provided on the reception side, and they are connected via signal lines D1 and D2 of a differential pair. The differential driver 130 is configured to be included in the differential IF circuit 42 of the MPU in FIG. Further, the differential receiver 132 is configured to be included in the differential IF circuit 60 in FIG.

  In the differential driver 130 on the transmission side, the p-type transistor 134 (differential driver control means in a broad sense) is connected to the power supply VDD at the source terminal and supplied with the power control signal PS at the gate terminal. One end of a current source 136 is connected to the drain terminal of the p-type transistor 134.

  The other end of the current source 136 is connected to the source terminals of the p-type transistors 138 and 140.

  The differential pair of signal lines D2 and D1 are connected to the drain terminals of the p-type transistors 138 and 140, respectively. A data signal D to be transmitted is supplied to the gate terminal of the p-type transistor 138. An inverted signal of the data signal D to be transmitted is supplied to the gate terminal of the p-type transistor 140.

  The differential receiver 132 has a differential amplifier 142. Since the configuration of the differential amplifier 142 is known, a description thereof is omitted, but this change occurs when the current from the current source changes in response to the change in the potential of the signal line of the received differential pair. A corresponding voltage is generated.

  The differential amplifier 142 is connected to the power supply VDD via a p-type transistor 144 (reception operation stopping means in a broad sense). A power control signal PS is supplied to the gate terminal of the p-type transistor 144. When the drain current of the p-type transistor 144 is supplied to the differential amplifier 142 by the power control signal PS, the differential amplifier 142 operates. However, when the drain current is stopped or limited, the operation is stopped. It has become.

  The signal lines D1 and D2 of the differential pair are connected to the ground potential VSS via termination resistors RL1 and RL2, respectively. The differential amplifier 142 of the differential receiver 132 amplifies the potential difference between the signal lines D1 and D2 of the differential pair generated by the termination resistors RL1 and RL2. The amplified signal is buffered by the buffer circuit 146 and supplied to the subsequent circuit as the reception signal S2.

  According to such a configuration, in the differential driver 130, the current from the current source 136 changes the drain current of the p-type transistors 138 and 140 according to the data signal D. As a result, the potentials of the signal lines D1 and D2 of the differential pair are changed by the termination resistors RL1 and RL2, and the potential difference is amplified by the differential amplifier 142 by the differential receiver 132.

  Therefore, as shown in FIG. 8B, a differential signal having an amplitude of Vs (for example, 300 mV) can be transmitted centering on Vc (for example, 150 mV), so that higher-speed data transfer is possible. The differential amplifier 142 on the reception side can be used for a subsequent CMOS circuit by amplifying it, buffering it, and converting it to a logic level.

  At this time, in the differential IF shown in FIG. 8B, the power control signal PS can be used to control the operation on the transmitting side and the receiving side, thereby reducing the power consumption as shown in FIG. It is like that.

(Third configuration example)
FIG. 9A shows a third configuration example of the differential IF, and FIG. 9B shows an example of operation waveforms in the third configuration example.

  In the third configuration example, a differential driver 150 is provided on the transmission side, and a differential receiver 152 is provided on the reception side, and they are connected via signal lines D1 and D2 of a differential pair. The differential driver 150 is included in the differential IF circuit 42 of the MPU in FIG. The differential receiver 152 is configured to be included in the differential IF circuit 60 in FIG.

  In the differential driver 150 on the transmission side, the n-type transistor 154 (differential driver control means in a broad sense) is connected to the ground power supply VSS at the source terminal and supplied with the power control signal PS at the gate terminal. The drain terminal of the n-type transistor 154 is connected to one end of the current source 156.

  The other end of the current source 156 is connected to the source terminals of the n-type transistors 158 and 160.

  The differential terminal signal lines D1 and D2 are connected to the drain terminals of the n-type transistors 158 and 160, respectively. A data signal D to be transmitted is supplied to the gate terminal of the n-type transistor 158. An inverted signal of the data signal D to be transmitted is supplied to the gate terminal of the n-type transistor 160.

  The differential receiver 152 has a differential amplifier 162. Since the configuration of the differential amplifier 162 is known, the description thereof is omitted. However, when the current from the current source changes in response to the change in the potential of the signal line of the received differential pair, this change occurs. A corresponding voltage is generated.

  The differential amplifier 162 is connected to the ground power supply VSS via an n-type transistor 166 (in a broad sense, reception operation stopping means). The power control signal PS is supplied to the gate terminal of the n-type transistor 166. When the drain current of the n-type transistor 166 is supplied to the differential amplifier 162 by the power control signal PS, the differential amplifier 162 operates. However, when the drain current is stopped or limited, the operation is stopped. It has become.

  The differential pair of signal lines D1 and D2 are connected to the potential VDD via termination resistors RL3 and RL4, respectively. The differential amplifier 162 of the differential receiver 152 amplifies the potential difference caused by the termination resistors RL3 and RL4. The amplified signal is buffered by the buffer circuit 164 and supplied to the subsequent circuit as the reception signal S3.

  According to such a configuration, in the differential driver 150, the drain currents of the n-type transistors 158 and 160 supplied from the current source 156 change according to the data signal D. As a result, the potentials of the signal lines D1 and D2 of the differential pair are changed by the termination resistors RL3 and RL4, and thus the potential difference is amplified by the differential amplifier 162 by the differential receiver 152.

  Therefore, as shown in FIG. 9B, a differential signal having an amplitude of Vs (for example, 300 mV) can be transmitted with Vc (for example, VDD-150 mV) as the center, so that higher-speed data transfer is possible. Become. The differential amplifier 162 on the receiving side can be used for a subsequent CMOS circuit by amplifying it, buffering it, and converting it to a logic level.

  At this time, in the differential IF shown in FIG. 9B, the power control signal PS can be used to control the operation on the transmitting side and the receiving side, thereby reducing the power consumption as shown in FIG. It is like that.

2.4 Comparison with IF by CMOS Circuit Regarding the differential IF capable of high-speed transfer, the power consumption when performing transfer control using a dummy blanking period will be described in comparison with the IF by the CMOS circuit. .

  FIG. 10 shows the relationship between the IF transfer rate and the current consumption by the CMOS circuit.

  Here, the horizontal axis represents the data transfer rate [Mbps] (megabits per second), and the vertical axis represents the current consumption [mA] (milliamperes).

  Further, since the transfer amount of display data required for displaying one frame differs depending on the image size and the number of gradation bits of various liquid crystal panels, typical image sizes and gradation bit numbers are shown. For example, when transferring 6 bits (18 bits in total) of RGB signals of QCIF (Quarter Common Intermediate Format, 176 × 144) at 15 f / s, 8 bits of RGB signals of CIF (352 × 288) size ( In the case of transferring a total of 24 bits) at 30 f / s, 8 bits (24 bits in total) of RGB signals of VGA (Video Graphics Array, 640 × 480) size are transferred at 30 f / s.

  In the IF using the CMOS circuit, the current consumption increases in proportion to the frequency. Therefore, the current consumption increases as the transfer rate increases (E1). Therefore, when display data of 6 bits (total 18 bits) of RGB signals in QCIF size is transferred at 15 f / s, a sufficiently small current consumption is required, but 8 bits of RGB signals in CIF size (total 24 bits). Bit) display data is transferred at 30 f / s, the required transfer rate is increased, resulting in an increase in current consumption. Furthermore, in the CMOS circuit, the transfer rate of the area indicated by R1 is difficult to achieve any more, and the display data of each 8 bits (24 bits in total) of the RGB signal is transferred at 30 f / s in the CIF size. Is difficult.

  On the other hand, according to the differential IF, a steady current flows without depending on the transfer rate as indicated by E2. Therefore, when the display data of 6 bits (total 18 bits) of the RGB signal is transferred at 15 f / s in the QCIF size, the current consumption is larger than the IF by the CMOS circuit. However, in the differential IF, a constant steady current is consumed regardless of the transfer rate. For example, display data of each 8 bits (24 bits in total) of the RGB signal is transferred at 30 f / s in the CIF size. In some cases, the current consumption is rather smaller than the IF using the CMOS circuit. Further, with the differential IF, display data can be transferred at a transfer rate that cannot be realized with a CMOS circuit.

  Accordingly, display data transfer is started during the dummy blanking period as described above at a high transfer rate that cannot be realized by a CMOS circuit such as 100 Mbps or 400 Mbps, and the transfer of the next display data is completed after the transfer is completed. By stopping the operation of the differential IF until the timing and reducing the consumption of the steady current, it is possible to achieve both a high transfer rate and a low consumption (E3, E4).

2.5 Write Bit Width The X driver IC 24 as the display controller in the first embodiment as described above has a differential IF or serial IF bit width of K (K is a natural number) and a parallel IF bit width of N. When N is a natural number greater than K, display data can be written into the display data RAM 28 in units of a bit width L (L is a natural number) of at least K and N.

  Thereby, even if it is necessary to write display data to the display data RAM at a high speed in order to display a moving image without a sense of incongruity, the writing frequency can be lowered. This can be dealt with when the display data necessary for displaying one frame increases due to the enlargement of the screen size of the liquid crystal panel. For example, if the writing frequency when writing to the display data RAM 28 in units of 8 bits is F, the writing frequency when writing in units of 16 bits is F / 2. Therefore, it is possible to use a low-cost process for manufacturing the display data RAM 28 and to suppress an increase in power consumption.

2.6 Operation Timing of Display Controller Next, the operation of the X driver IC 24 in the first embodiment will be specifically described. In the following description, the first configuration example shown in FIGS. 6A and 6B is applied as the differential IF. However, the same applies to the second and third configuration examples.

  11A and 11B show specific examples of signals transmitted and received by the differential IF.

  In FIG. 11A, the clock signal CLK and the data signal D are transferred from the MPU 10 to the display controller 24 via the differential pair of signal lines. Further, the display controller 24 transmits the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync via the IF by the CMOS circuit in order to notify the MPU 10 of the internally generated display timing.

  Since the MPU 10 recognizes the amount of display data to be transferred through the differential pair of signal lines D, the differential IF operation is performed after the display data is transferred with reference to the notified vertical synchronization signal Vsync or horizontal synchronization signal Hsync. A power control signal PS for stopping is generated, and differential IF operation control between the transmission side of the MPU 10 and the reception side of the display controller 24 is performed.

  Further, as shown in FIG. 11B, the display controller 24 may notify the MPU 10 as a composite signal in which the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync are combined.

  FIG. 12 shows an example of operation timing when display data is transferred at 60 f / s to the display controller via the differential IF described above.

  Here, it is assumed that one vertical scanning period includes, for example, 288 horizontal scanning periods and vertical blanking periods B1 and B2. That is, it is assumed that the dummy vertical blanking period is a period corresponding to two horizontal scanning periods.

  The display controller 24 outputs the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync or the vertical / horizontal synchronization signal composite signal in order to notify the display timing generated internally to the MPU 10 on the display data supply side.

  When the MPU 10 detects the rising edge of the vertical synchronizing signal Vsync and the rising edge of the horizontal synchronizing signal or the rising edge of the vertical / horizontal synchronizing signal composite signal (time TT1), the MPU 10 starts the operation of the differential IF by the power control signal PS. The display controller 24 is notified after a time t1 (t1 ≦ 1H, 1H is one horizontal scanning time) from TT1. Thereafter, during the period when the logic level of the power control signal PS is “L”, the operations of the differential IF circuit 42 of the MPU 10 and the differential IF circuit 60 of the display controller 24 are started, and a steady current flows.

  After elapse of time t2 (t1 ≦ t2 ≦ 1H) from the subsequent time TT1, transmission of the data signal D and the clock signal CLK by the differential IF is started from the MPU 10, and display for one frame at a high transfer rate of 100 Mbps to 400 Mbps, for example. Data is transferred until time TT2.

  That is, transfer of display data for one frame is started during the dummy vertical blanking period. Since the MPU 10 recognizes the transfer data amount of the display data for one frame, the transfer time Tp of the display data for one frame is known from the relationship with the preset transfer rate. Therefore, the MPU 10 sets the logic level of the power control signal PS to “L” for at least one frame of display data transfer time Tp.

  As a result, the power control signal PS becomes the logic level “H” at time TT3 (TT2 ≦ TT3) after the transfer of display data for one frame is completed, and the operation of the operation IF is stopped. Thereafter, during the period when the logic level of the power control signal PS is “H”, the operations of the differential IF circuit 42 of the MPU 10 and the differential IF circuit 60 of the display controller 24 are stopped, and the current consumption becomes zero.

  On the other hand, the display controller 24 is written from the display data RAM in the vertical blanking period in order from the first scanning line after the horizontal scanning period 1H in synchronization with the fall of the vertical synchronizing signal Vsync in the vertical scanning period 1V. The display data of the frame is read, and the liquid crystal panel is driven as described above (picture 1 display).

  When the frame period is 60 Hz, when the vertical synchronization signal Vsync rises in the next vertical scanning period 2V, the display data transfer control for the second frame is performed in the same manner as in the vertical scanning period 1V, and the vertical scanning period 2V becomes vertical. The display data of the frame written during the blanking period is read, and the liquid crystal panel is driven as described above (picture 2 display).

  As described above, a steady-state current flows during the transfer of display data for one frame in the differential IF. However, the operation associated with the transfer of display data in each frame is stopped by stopping the operation of the differential IF after the transfer ends. The current is only the steady-state current of the differential IF from time t1 to TT3. Therefore, as shown in FIG. 10, the power consumption can be reduced compared to the case of IF using a CMOS circuit. This becomes more effective as the amount of display data to be transferred increases.

  FIG. 13 shows an example of operation timing when display data is transferred at 30 f / s to the display controller via the differential IF described above.

  Also in this case, the display data transfer control is the same as 60 f / s shown in FIG.

  When the display controller 24 drives the liquid crystal panel at a frame period of 60 Hz, the display data is transferred to the first frame as shown in FIG. 12 because the display drive is performed based on the same display data for two consecutive frames. When this is done, the next display data may be transferred in the third frame after leaving one frame. That is, since the differential IF stop period becomes longer, it is possible to further reduce power consumption.

  FIG. 14 shows an example of operation timing when display data is transferred to the display controller at 15 f / s via the differential IF described above.

  Also in this case, the display data transfer control is the same as 60 f / s shown in FIG.

  However, in the case where the display controller 24 drives the liquid crystal panel at a frame period of 60 Hz, the display data is shown in FIG. 12 for the first frame because display drive is performed based on the same display data for four consecutive frames. In this way, the next display data may be transferred in the fourth frame after three frames. Accordingly, since the differential IF is stopped for a long time, it is possible to further reduce power consumption.

  Actually, when displaying moving images on a liquid crystal panel, it is assumed that moving images can be recognized without a sense of incongruity due to human visual characteristics up to 15 f / s. It is possible to achieve both reduction of power consumption.

<Second Embodiment>
3. Features of the second embodiment In the first embodiment, it has been described that display data for one frame is collectively transferred using a dummy vertical blanking period. However, the present invention is not limited to this. It is not a thing. In the second embodiment, the screen size of the liquid crystal panel can be increased by high-speed transfer control of the differential IF by transferring display data for the scanning line from the period using a dummy horizontal blanking period. It is possible to achieve both compatibility with low power consumption and low power consumption.

  Since the configuration of the display controller, the display unit using the display controller, and the electronic device in the second embodiment is the same as that of the first embodiment, the description thereof is omitted.

3.1 Dummy Horizontal Blanking Period FIG. 15 is a diagram for explaining the dummy horizontal blanking period.

  In the second embodiment, display data is transferred at high speed during a dummy horizontal blanking period in synchronization with the rising of the horizontal synchronization signal Hsync, and the display data for the scanning lines is written into the display data RAM. . For example, in the scanning period of the first scanning line, display data of the first scanning line is transferred from the dummy horizontal blanking period of the first scanning line. In this case, if attention is paid to each scanning line in the frame, since writing is always performed prior to reading, display driving of one frame can be performed without considering timing.

3.2 Operation Timing FIG. 16 shows an example of operation timing when display data is transferred to the display controller at 60 f / s via the differential IF in the second embodiment.

  Here, it is assumed that one vertical scanning period includes, for example, 288 horizontal scanning periods and vertical blanking periods B1 and B2. That is, it is assumed that the vertical blanking period is a period corresponding to two horizontal scanning periods.

  In addition, the third configuration example shown in FIGS. 9A and 9B is applied as the differential IF, but the same applies to the first and second configuration examples.

  The display controller outputs a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync in order to notify the MPU on the display data supply side of the internally generated display timing.

  When the MPU detects the rise of the vertical synchronization signal Vsync and the rise of the horizontal synchronization signal (time TT11) and detects the rise of the horizontal synchronization signal Hsync in the dummy horizontal blanking period B2, the MPU detects the differential IF by the power control signal PS. In order to start the operation, the display controller is notified with a delay of time t11 (t11 ≦ 1H) from time TT11. Thereafter, during the period when the logic level of the power control signal PS is “H”, the operations of the differential IF circuit of the MPU and the differential IF circuit of the display controller are started, and a steady current flows.

  After elapse of time t21 (t11 ≦ t21 ≦ 1H) from the subsequent time TT11, transmission of the data signal D and the clock signal CLK by the differential IF is started from the MPU. For example, the first scan line at a high transfer rate of 100 Mbps to 400 Mbps is started. The display data is transferred until time TT21.

  That is, transfer of display data for one scanning line is started during the dummy horizontal blanking period. Since the MPU recognizes the amount of display data transferred for one scan line, the display data transfer time TL for one scan line can be determined from the relationship with a preset transfer rate. Therefore, in the MPU, the logic level of the power control signal PS is set to “H” for the transfer time TL of display data for at least one scanning line.

  As a result, the power control signal PS becomes the logic level “L” at time TT31 (TT21 ≦ TT31) after the transfer of the display data for the scanning line is finished, and the operation of the operation IF is stopped. Thereafter, during the period when the logic level of the power control signal PS is “L”, the operations of the MPU differential IF circuit and the display controller differential IF circuit are stopped, and the current consumption becomes zero.

  On the other hand, the display controller synchronizes with the fall of the vertical synchronization signal Vsync in the vertical scanning period 1V, and the display data of the frame written from the display data RAM during the dummy horizontal blanking period in the horizontal scanning period 1H. And the liquid crystal panel is driven as described above.

  Similarly, in the horizontal scanning periods 2H, 3H,..., Display data transfer control is performed in units of scanning lines using each horizontal blanking period. In this way, display for one frame is performed in the vertical scanning period 1V (picture 1 display).

  When the frame period is 60 Hz, when the vertical synchronization signal Vsync rises in the next vertical scanning period 2V, display data transfer control is performed in units of scanning lines in the second frame in the same manner as in the vertical scanning period 1V. The display data written from each dummy horizontal blanking period in the scanning period 2V is read, and the liquid crystal panel is driven as described above. In the vertical scanning period 2V, display for the next one frame is performed (picture 2 display).

  In this way, the differential IF flows a steady current during the transfer of display data for each scanning line, but the display data is transferred during each horizontal scanning period by stopping the operation of the differential IF after the transfer ends. The current consumption associated with is only the steady-state current of the differential IF from time t11 to TT31. Therefore, the power consumption can be reduced as compared with the case of the CMOS interface as shown in FIG. This becomes more effective as the amount of display data to be transferred increases.

  FIG. 17 shows an example of operation timing when display data is transferred to the display controller at 15 f / s via the above-described differential IF in the second embodiment.

  Also in this case, the display data transfer control is the same as 60 f / s shown in FIG.

  However, when the display controller drives the liquid crystal panel at a frame period of 60 Hz, the display drive is performed on the basis of the same display data for the four consecutive frames. When the transfer is performed as shown in FIG. 16, the next display data may be transferred in the fourth frame after three frames. Accordingly, since the differential IF is stopped for a long time, it is possible to further reduce power consumption.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention.

  In FIG. 3, the bit width K of the differential IF is described as 1 bit, but the present invention is not limited to this. If the bit width of the differential IF is 2 bits or more, the transfer time of display data required for moving image display can be further shortened. Therefore, the transfer control as described above increases the image size. In addition, it can contribute to further lower power consumption.

It is a block diagram which shows an example of the outline | summary of a structure of the electronic device to which the display controller in 1st Embodiment is applied. It is a block diagram which shows the structural example of the mobile telephone carrying MPU and the display unit in 1st Embodiment. It is a block diagram which shows an example of the structure principal part of X driver IC as a display controller in 1st Embodiment. FIG. 4A is an explanatory diagram showing the relationship between the vertical synchronization signal and the horizontal synchronization signal. FIG. 4B is an explanatory diagram for explaining a dummy blanking period. It is explanatory drawing for demonstrating transfer control of the display data for 1 frame during the dummy vertical blanking period in 1st Embodiment. FIG. 6A is a configuration diagram illustrating a first configuration example of the differential IF. FIG. 6B is an explanatory diagram illustrating an example of operation waveforms in the first configuration example. It is explanatory drawing for demonstrating the power saving control by a power control signal. FIG. 8A is a configuration diagram illustrating a second configuration example of the differential IF. FIG. 8B is an explanatory diagram showing an example of operation waveforms in the second configuration example. FIG. 9A is a configuration diagram illustrating a third configuration example of the differential IF. FIG. 9B is an explanatory diagram illustrating an example of operation waveforms in the third configuration example. It is explanatory drawing for demonstrating the relationship between a transfer rate and consumption current about differential IF and a CMOS interface. FIG. 11A is an explanatory diagram showing an example of signals transmitted and received by the differential IF. FIG. 11B is an explanatory diagram showing another example of signals transmitted and received by the differential IF. It is a timing chart showing an example of operation timing when display data is transferred to a display controller in a 1st embodiment at 60 f / s. FIG. 6 is a timing diagram illustrating an example of operation timing when display data is transferred to the display controller at 30 f / s in the first embodiment. FIG. 6 is a timing diagram illustrating an example of operation timing when display data is transferred to the display controller according to the first embodiment at 15 f / s. It is explanatory drawing for demonstrating transfer control of a display data per scanning line in the dummy horizontal blanking period in 2nd Embodiment. It is a timing diagram which shows an example of the operation timing at the time of transferring display data at 60 f / s to the display controller in 2nd Embodiment. FIG. 10 is a timing diagram illustrating an example of operation timing when display data is transferred at 15 f / s to a display controller according to the second embodiment.

Explanation of symbols

10 MPU, 12 CPU, 14 still image memory, 16 DSP,
18 video processing memory, 20 display unit,
22 Liquid crystal panel (display panel, matrix panel, display unit),
24 display controller (X driver IC),
26 Y driver IC, 28 display data RAM, 30 mobile phone,
32 antenna, 34 modem circuit, 36 digital video camera,
38 operation input unit, 40, 70 serial IF circuit,
42, 60 differential IF circuit, 44, 80 parallel IF circuit,
50 latch circuit, 52 liquid crystal drive circuit, 54 LCD controller,
62 start frame detection circuit, 64, 72, 82 S / P conversion circuit,
90 input buffer circuit, 94 OSC,
100, 130, 150 differential driver, 102, 132, 152 differential receiver,
104, 108, 110, 134, 138, 140 p-type (first conductivity type) transistors,
106, 136, 156 current sources,
112, 114, 118, 154, 158, 160, 166 n-type (second conductivity type) transistors,
116, 142, 162 Differential amplifier, 120, 146, 164 Buffer circuit

Claims (11)

The differential signal line is connected to a receiving means for converting the current of the differential signal line into a voltage, and the transmission data is transmitted by controlling the current of each signal line of the differential signal line according to the transmission data. Means,
Means for stopping power supply to the means for transmitting the transmission data. In claim 1,
Means for transmitting the transmission data;
A current source;
Means for causing a current from the current source to flow in each signal line of the differential signal line according to the transmission data;
Means for drawing a current from each signal line of the differential signal line according to the transmission data,
Each of the differential signal lines is connected to each other via a terminating resistor. In claim 1,
Means for transmitting the transmission data;
A current source;
Means for causing a current from the current source to flow through each signal line of the differential signal line according to the transmission data,
The transmission circuit, wherein each signal line of the differential signal line is connected to the low potential side power source among the high potential side power source and the low potential side power source via a termination resistor. In claim 1,
Means for transmitting the transmission data;
A current source;
Means for drawing a current from each signal line of the differential signal line according to the transmission data,
The transmission circuit, wherein each signal line of the differential signal line is connected to the high potential side power source among the high potential side power source and the low potential side power source via a termination resistor. Connected to the transmission means for transmitting the transmission data by controlling the current of each signal line of the differential signal line according to the transmission data, and converting the current of the differential signal line into a voltage Means to
Means for stopping the power supply to the means for converting the current into voltage. Differential signal lines;
The transmission circuit according to any one of claims 1 to 4, connected to the differential signal line;
6. A differential interface device comprising: the transmitter circuit; and the receiver circuit according to claim 5 connected via the differential signal line. A display controller for driving the display unit based on display data,
Storage means for storing display data for at least one frame;
The receiving circuit according to claim 5, wherein display data to be written to the storage means is received from a dummy blanking period provided before the start of scanning of the display unit;
Display data writing means for writing display data received by the receiving circuit to the storage means from the dummy blanking period;
Display driving means for driving the display unit based on display data read from the storage means;
A display controller comprising: In claim 7,
Means for stopping power supply to the means for converting the current into voltage,
A display controller characterized in that the power supply is stopped only for a given period from when reception of display data is completed by the receiving circuit to when next display data is received. In claim 7,
Means for stopping power supply to the means for converting the current into voltage,
A display controller, wherein after the display data received by the receiving circuit is written in the storage means, the power supply is stopped until the next display data is received. A panel having electro-optic elements driven by a plurality of first electrodes and a plurality of second electrodes;
The display controller according to any one of claims 7 to 9, which drives the plurality of first electrodes;
A scan driver that scans the plurality of second electrodes;
A display unit comprising:   An electronic apparatus comprising the display unit according to claim 10.

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