JP2000181584A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power to be consumed by the periodical interface operation of an external interface control circuit. SOLUTION: When a central processing unit 4 sets a cycle to an operating cycle control circuit 3 at the time when an external interface control circuit 1 periodically performs communication operation, the operation of the external interface control circuit 1 or data transfer control circuit 2 is independently stopped and afterwards, the operating cycle control circuit 3 enables the external interface control circuit or data transfer control circuit to be operated in that cycle again. Useless power can be suppressed from being consumed when it is practically unnecessary to operate the external interface control circuit or data transfer control circuit in the periodical external interface operation and further, since that control is performed by the operating cycle control circuit, any large burden is not loaded to the central processing unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a periodic interface operation by an external interface control circuit such as a serial interface circuit, and more particularly to a technique which is effective when applied to a low power consumption microcomputer having a serial interface circuit. is there.

[0002]

2. Description of the Related Art Conventionally, a serial interface circuit built in a microcomputer is connected to a memory or the like via an internal bus. Data transfer between the serial interface circuit and the memory can be controlled by, for example, a DMAC (Direct Memory Access Controller). In the DMAC, data transfer conditions such as a data transfer destination address and a transfer source address are initially set by a CPU (central processing unit). Generally, the data transfer rate of the serial interface circuit is generally slower than the operating frequency inside the microcomputer.

The serial interface circuit has a receiving unit for receiving data from an external device and a transmitting unit for transmitting data to the external device. The transmitter and the receiver are enabled by setting the transfer enable bit,
For example, the transfer operation is started in synchronization with the rise of the frame signal. The transmission enable bit and the reception enable bit are held in a register accessible by the CPU, and the operation is performed by the CPU via the bus.

[0004] The receiving section stores received data in a receiving buffer and transfers the stored data to a memory by a DMAC. The transmission data is written from the memory to the transmission buffer under the control of the DMAC, and the written data is transmitted from the transmission unit. When the receiving operation is performed periodically, the DMA transfer from the receiving buffer to the memory is also performed periodically. Similarly, when the transmission operation is performed periodically, the DMA transfer from the memory to the transmission buffer is also performed periodically. The data transfer operation for the DMAC is requested from the serial interface circuit to the DMAC each time a certain reception operation for the reception buffer is completed, and is also performed from the serial interface circuit to the DMAC each time the transmission operation for the data in the transmission buffer is completed. Required.

A serial interface circuit, a DMAC, and the like must always be operable in order to respond to a data reception request or a data transfer request asynchronously given from the outside. For this reason, the serial interface circuit and the DMAC are generally always in an operable state even when the actual operation time is short in synchronization with the communication.

[0006]

According to the above prior art, during a periodical communication operation, the reception unit and the transmission unit of the serial interface circuit are always enabled to operate even during the period when the communication operation is not actually performed. Will be consumed. Similarly, the DMAC is always operable regardless of the presence or absence of communication. In many cases, an external device that communicates with the serial interface circuit is always operable regardless of whether the serial interface circuit is actually performing a communication operation. Here, the operable state means that a clock signal is continuously supplied to a circuit operated in synchronization with the clock signal. When a clock signal is supplied to the circuit, at least a circuit portion that performs a charging / discharging operation in synchronization with a change in the clock signal exists, and at least a path that causes a through current due to a transient response operation of the CMOS circuit is formed. This consumes power.

Communication using a serial interface circuit or the like includes a method that is performed periodically such as voice data communication and a method that is performed randomly such as keyboard input. For random communication, the input / output timing cannot be predicted, so it is necessary to keep the circuit running.However, in periodic communication, the input / output timing is fixed, and the circuit stops when no communication is performed. There is no problem if you let them. In this regard, the prior art does not consider easily realizing a configuration in which the operation of the serial interface circuit is suspended during the idle time of the periodic communication operation. The CPU must rewrite the transmission enable bit and the reception enable bit via the bus each time. For the DMAC, the CPU must rewrite the DMAC enable bit via the bus each time.

Further, even if the power consumption in the periodic operation by the serial interface circuit or DMAC built in the microcomputer can be reduced, the operation of the serial interface circuit is stopped for the external device connected to the serial interface circuit. There is no guarantee that the operation can be stopped during. At least, the present inventor has found that the microcomputer supports a function of outputting a control signal that can be used to suspend operation of an external device in response to suspension of operation of the microcomputer built-in serial interface circuit. If low power consumption of the entire system is intended, it is desirable to reduce unnecessary power consumption by an external device connected to the serial interface circuit outside the microcomputer.

An object of the present invention is to provide a data processing device capable of easily reducing power consumed in a periodic interface operation by an external interface control circuit.

Another object of the present invention is to provide a data processing device which can contribute to a reduction in power consumption of an external device connected to an external interface control circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] A first aspect is that, in a periodic external interface operation of an external interface control circuit (1) such as a serial interface circuit, an autonomous operation clock supply stop and a cycle in response to termination of the external interface operation are performed. Supply restart. The data processing unit (MCU) includes a central processing unit (4) and a memory (5).
An external interface control circuit (1), a data transfer control circuit (2) capable of controlling data transfer between a memory and the external interface control circuit, and a period at which an external interface operation by the external interface control circuit is possible. And an operation cycle control circuit (3) for controlling. The external interface control circuit (1) responds to the end of the external interface operation (203 = “1” and 204 = “1”) in response to the external interface operation circuit (101, 10).
2) The supply of the first operation clock signal (fCLK) to the external interface is stopped, and the end of the external interface operation is determined by an operation cycle control circuit (3) and a data transfer control circuit (2).
Notify. The data transfer control circuit (2) responds to the end notification of the external interface operation (209 = “1”) and performs a data transfer operation between the memory and the external interface control circuit according to a data transfer control condition. to start. The operation cycle control circuit (3), upon receiving a notice of the end of the external interface operation (209 = "1"), measures a certain time specified by the first cycle information and then executes the external interface control circuit (1). ) To the first
Of the operation clock signal (fCLK) is restarted (218 = "1"). The central processing unit sets the data transfer control condition in the data transfer control device and sets the first cycle information in the operation cycle control circuit.

The data transfer control circuit (2) can be included in the control target of clock supply stop / supply restart. In the above, the data transfer control circuit (2) further notifies the end of the external interface operation (209 = "1").
The data transfer control operation between the memory (5) and the external interface control circuit (1) in response to the
30 = “1”), the supply of the second operation clock signal (InCLK) to the data transfer circuit is stopped, and the end of the data transfer operation is notified to the operation cycle control circuit (3). . The operation cycle control circuit (3) further includes a second
After measuring a certain time designated by the period information of the second transfer clock signal (I) to the data transfer control circuit (2).
instruction to restart the supply of (nCLK) (331 = “1”)
, It is possible to control the cycle in which the data transfer operation by the data transfer control circuit (2) is possible. The central processing unit (4) further sets second cycle information in the operation cycle control circuit (3).

When the control target is extended to the outside of the data processing unit (MCU), the operation cycle control circuit (3) further receives the external interface operation end notification (209 = "1"). Then, an external control enable signal (340), which is set to the inactive state and is set to the active state after measuring a certain time specified by the third cycle information, is generated. The central processing unit further sets third cycle information in the operation cycle control circuit.

As described above, when the external interface control circuit (1) periodically performs a communication operation, the central processing unit (6) sets the cycle in the operation cycle control circuit (3). After the operation of 1) and the operation of the data transfer control circuit (2) are independently suspended, the operation cycle control circuit (3) operates the external interface control circuit (1), the data transfer control circuit (2), etc. at that cycle. It can be made cyclically operable.

[2] The second mode realizes periodic clock supply stop / restart in the periodic external interface operation of the external interface control circuit (1) such as a serial interface circuit. Data processing device (M
CU) includes a central processing unit (4), a memory (5), an external interface control circuit (1), and a data transfer control circuit (2) capable of controlling data transfer between the memory and the external interface control circuit. And an operation cycle control circuit (3) for controlling a cycle in which the external interface can be operated by the external interface control circuit. The external interface control circuit (1) notifies the end of the external interface operation to the operation cycle control circuit (3) and the data transfer control circuit (2). The data transfer control circuit (2) notifies the end of the external interface operation (20
9 = "1") in accordance with the data transfer control condition,
Activating a data transfer operation between the memory and the external interface control circuit. The operation cycle control circuit (3) is configured to notify the end of the external interface operation (2
09 = “1”), the enable signal (218) for the external interface operation is deactivated, and after measuring a certain time specified by the first cycle information, the enable signal for the external interface operation is activated. State. The external interface control circuit (1) responds to the active state of the external interface operation enable signal by an external interface operation circuit (101, 10).
2) The supply of the first operation clock signal (fCLK) to the external interface operation circuit is started in response to the inactive state of the enable signal for the external interface operation. Stop. The central processing unit sets the data transfer control condition in the data transfer control device, and sets first cycle information in the operation cycle control circuit.

The data transfer control circuit (2) can be included in the control target of clock supply stop / supply restart. In the above, the data transfer control circuit (2) further includes a data transfer between the memory (5) and the external interface control circuit (1) in response to the external interface operation end notification (209 = "1"). End of operation (330 =
"1") to the operation cycle control circuit (3). The operation cycle control circuit (3) further receives an enable signal (3) for the data transfer operation by the data transfer control device when the data transfer operation end notification (330 = "1") is received.
31) is deactivated, the enable signal (331) for the data transfer operation is activated after measuring a certain time specified by the second cycle information, so that the data transmitted by the data transfer control circuit (2) is activated. The period in which the transfer control operation can be performed can be controlled. The data transfer control circuit (2) includes an enable signal (33) for the data transfer operation.
In response to the active state of 1), the data transfer operation circuit (10
5, 106) to the second operation clock signal (InCL).
K), and stops the supply of the second operation clock signal to the data transfer operation circuit in response to the inactive state of the data transfer operation enable signal. The central processing unit further sets second cycle information in the operation cycle control circuit.

When the control target is extended to the outside of the data processing unit (MCU), the operation cycle control circuit (3) further receives the external interface operation end notification (209 = "1"). Then, an external control enable signal (340), which is set to the inactive state and is set to the active state after measuring a certain time specified by the third cycle information, is generated. The central processing unit further sets third cycle information in the operation cycle control circuit.

In the second mode, when the external interface control circuit (1) periodically performs a communication operation, the central processing unit (6) sets the cycle in the operation cycle control circuit (3). The circuit (3) can enable the external interface control circuit (1), the data transfer control circuit (2), and the like to operate cyclically with the enable signal (218, 331, 340) according to the cycle.

[3] In the third aspect, in the periodic external interface operation of the external interface control circuit (1), the periodic clock supply stop / restart is realized for each multiple of the data transfer unit. Data processing device (M
CU) includes a central processing unit (4), a memory (5), an external interface control circuit (1), and a data transfer control circuit (2) capable of controlling data transfer between the memory and the external interface control circuit. And an operation cycle control circuit (3) for controlling a cycle in which the external interface can be operated by the external interface control circuit. The external interface control circuit (1) notifies the end of the external interface operation (209 = "1") to the operation cycle control circuit (3) and the data transfer control circuit (2). The data transfer control circuit starts a data transfer operation between the memory and the external interface control circuit in accordance with a data transfer control condition in response to the end notification of the external interface operation (209 = "1"). The operation cycle control circuit (3), when the number of the end notification (209 = "1") of the external interface operation reaches the first repetition number, enables the external interface operation enable signal (2).
18) is deactivated, and after measuring a certain time specified by the first cycle information, the enable signal (218) for the external interface operation is activated. The external interface control circuit (1) responds to an active state of the external interface operation enable signal (218) by an external interface operation circuit (101, 102).
To start supplying the first operation clock signal (fCLK) to the external interface operation enable signal (2).
The supply of the first operation clock signal to the external interface operation circuit is stopped in response to the inactive state of 18).
The central processing unit sets the data transfer control condition in the data transfer control device, and sets the first repetition number and first cycle information in the operation cycle control circuit.

The data transfer control circuit (2) can be included in the control of clock supply stop / supply restart. The data transfer control circuit (2) further ends the data transfer operation between the memory and the external interface control circuit in response to the end notification of the external interface operation (209 = “1”) (330 = “1”). ") To the operation cycle control circuit (3). The operation cycle control circuit further notifies the end of the data transfer operation (330 = "1").
When the number of times has reached the second repetition number, the enable signal (3) of the data transfer operation by the data transfer control device (2)
31) is deactivated, the enable signal (331) for the data transfer operation is activated after measuring a certain time specified by the second cycle information, so that the data transmitted by the data transfer control circuit (2) is activated. The period in which the transfer control operation can be performed can be controlled. The data transfer control circuit starts supplying a second operation clock signal (InCLK) to the data transfer operation circuit in response to the activation state of the enable signal (331) of the data transfer operation, The supply of the second operation clock signal to the data transfer operation circuit is stopped in response to the inactive state of the enable signal of. The central processing unit further sets the second repetition number and second cycle information in the operation cycle control circuit.

In the case where the control target is extended to the outside of the data processing unit (MCU), the operation cycle control circuit (3) further sets the number of times of the end notification (209 = "1") of the external interface operation. An external control enable signal (340) which is deactivated when the third repetition number is reached and which is activated after measuring a certain time specified by the third cycle information is generated. The central processing unit further includes a third repetition number and a third
And the period information of.

According to a third aspect, when the external interface control circuit (1) performs a communication operation periodically for each multiple of data of the data transfer unit, the central processing unit (6) operates the operation cycle control circuit (3). The operation cycle control circuit (3) sets the enable signal (218, 331, 31) according to the cycle.
In 340), the external interface control circuit (1), the data transfer control circuit (2), and the like can be made operable, and their states can be maintained for the number of external interface operations specified by the number of repetitions. Therefore, it is possible to prevent inconvenience caused by frequent repetition of clock supply stop / supply operation when the data transfer interval of the external interface operation is small.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <Outline of Data Processing Apparatus> FIG. 1 shows a microcomputer as an example of a data processing apparatus according to the present invention. Microcomputer MCU
Are formed on one semiconductor substrate such as single crystal silicon. The microcomputer MCU includes a central processing unit (CPU) 4 for executing instructions, and an R used for a work area or a data primary storage area of the CPU 4.
Memory 5 composed of AM and internal bus 1 connecting them
14, a serial interface circuit 1 connected to the internal bus 114, a data transfer control circuit 2 for controlling data transfer between the serial interface circuit 1 and the memory 5, a serial interface circuit 1, and a data transfer control circuit. 2, an operation cycle control circuit 3 for generating a signal for controlling the operation cycle, and a clock generation circuit (CP) for generating an internal operation reference clock signal InCLK.
G) 6, a terminal unit 7 connected to an external circuit, and a bus interface circuit 8 for interfacing the internal bus 114 with the external bus. The internal bus 114 includes an address bus ABUS and a data bus DBUS representatively shown, and further includes a control bus not shown. Although not particularly limited, the CPU 4 includes a product-sum operation unit in addition to the arithmetic and logic operation unit, and by executing the product-sum operation instruction included in the instruction set, the digital signal processing operation can be performed efficiently. ing.

In FIG. 1, the serial interface circuit 1 is shown to have only one serial channel for ease of understanding, but it is not precluded that the serial interface circuit 1 has a plurality of serial channels. Similarly, although the data transfer control circuit 2 is illustrated as having one transfer control channel, it is needless to say that the data transfer control circuit 2 may include a plurality of data transfer channels.

The serial interface circuit 1 includes a transmission buffer 107 and a reception buffer 108 which can be accessed independently of each other. The transmission data temporarily stored in the transmission buffer 107 is transmitted to the terminal unit 7 via the transmission unit 101.
Is serially output to the outside. Data serially supplied from the outside via the terminal unit 7 is input to the receiving unit 102 and stored in the receiving buffer 108. Str is a transmission signal output from the transmission unit 101, and Src is a reception signal supplied to the reception unit 102.

The input / output control circuit 103 included in the serial interface circuit 1 sends a signal to transfer the next transmission data from the memory 5 to the serial interface circuit 1 every time the transmission unit 101 completes data transmission. 20
7 to the data transfer control circuit 2 and
02 requests the data transfer control circuit 2 by a signal 208 to transfer the data received each time the data reception is completed and stored in the reception buffer 108 to the memory 5 or the like. Writing of data to the transmission buffer 107 is controlled by the transmission buffer writing circuit 110. Receive buffer 1
Read data from the buffer reading circuit 1
09 controls. Also, the input / output control circuit 103 outputs a transmission / reception end signal 209 by the serial interface circuit 1.
Is output to the operation cycle control circuit 3. The input / output control circuit 103 stops the supply of the clock signal fCLK to the transmission unit 101 and the reception unit 102 at the end of transmission / reception, and suspends the operation of those circuits. Clock signal fC
LK is a motive clock signal for communication.
Is supplied from outside through

The data transfer control circuit 2 has a function as a data transfer channel of a direct memory access controller (DMAC).
The transfer control information such as the transfer destination memory address and the number of words to be transferred is previously stored in the memory readout circuit 105 by the CPU 4.
Initialized in the memory write circuit 106. The transfer control circuit 104 in the data transfer control circuit 2 controls the read access of the memory 5 by using the memory read circuit 105 in response to the transmission data transfer instruction by the signal 207 output from the input / output control circuit 103. , Instructs the buffer write circuit 110 to perform a write operation, and controls data transfer from the memory 5 to the transmission buffer 107. Further, the transfer control circuit 104 responds to the received data transfer instruction by the signal 208, and
09 and the memory write circuit 10
6, the writing control of the memory 5 is performed, and the transfer of the received data from the receiving buffer 108 to the memory 5 is controlled.

When the transfer control circuit 104 completes the data transfer between the memory 5 and the serial interface 1 instructed by the end of the transmission and reception, the clock signal InCLK to the memory read circuit 105 and the memory write circuit 106 is transmitted. Is stopped, and the operation of those circuits is stopped.

In the operation cycle control circuit 3, the operation cycle for the communication operation by the serial interface circuit 1 and the operation cycle for the data transfer operation by the data transfer control circuit 2 are initialized by the CPU 4 in advance. . The operation cycle control circuit 3 includes the input / output control circuit 103
Receives the end signal 209 of the transmission / reception operation output from the communication interface, at the start timing of the next communication operation in the communication operation cycle, the control signal 218 for enabling the operation of the inactive serial interface circuit 1 to be resumed. Give to circuit 1. Similarly, when the operation cycle control circuit 3 receives the signal 330 indicating the end of the data transfer from the data transfer control circuit 2, the operation cycle control circuit 3 stops the pause at the start timing of the next data transfer operation in the data transfer operation cycle. A control signal 331 for enabling the operation of the data transfer control device to be restarted is given to the data transfer control circuit 2. Further, the operation cycle control circuit 3 synchronizes with the signal 218 for controlling the serial interface circuit 1 and the signal 331 for controlling the data transfer control circuit 2,
A signal 340 for controlling an external device is output to the outside of the microcomputer MCU via the terminal unit 7.

As described above, the input / output control circuit 103 and the transfer control circuit 104 receive the clock signal fCL at the time when the transmission / reception operation and the data transfer operation accompanying the communication are completed.
K, the supply of InCLK is stopped, and the operation of a required portion of the serial interface circuit 1 and the data transfer control circuit 2 is put into a pause state. Then, the operation state is determined by the signals 218 and 331 sent from the operation cycle control circuit 3. Can be returned to. In other words, when the serial interface circuit 1 periodically performs a communication operation and the CPU 6 sets the cycle in the operation cycle control circuit 3, after the operations of the serial interface circuit 1 and the data transfer control circuit 2 are stopped, The operation cycle control circuit 3 can make the input / output control circuit 103 and the transfer control circuit 104 operable again in that cycle. Therefore, it is possible to reduce unnecessary power consumed by the serial interface circuit 1, the data transfer control circuit 2, and the like at a time that is not originally related to communication.

The operation of the plurality of communication channels, whose illustration of the serial interface circuit is omitted, is the same as that of the communication channel typically shown in FIG. 1, and the description of the operation will be omitted here.

<< Input / output control circuit >> The input / output control circuit 1
03 will be described in detail. The main role of the input / output control circuit 103 is to output a transmission / reception permission signal according to the setting state of the control register 240,
02 is to output the data transfer request output from the data transfer control circuit 2 to the data transfer control circuit 2. In addition to this, there is a function of stopping the supply of the external clock signal fCLK to, for example, the transmission / reception units 101 and 102 in synchronization with the completion of the transmission / reception operation, and stopping the operation of the portion related to the transmission / reception operation in the serial interface circuit. are doing.

FIG. 2 shows a detailed example of the input / output control circuit 103. Prior to transmission / reception, the CPU 6 operates a control register 24 provided in the serial interface circuit 1 in order to enable circuits related to transmission / reception.
A transmission permission bit or a reception permission bit in 0 is set. The transmission permission bit of the control register 240 is reflected on the signal 220. Signal 220 and signal 2
11 is input to the AND gate 231, and its logical product is used as a set signal of the flip-flop 216 (input signal of the terminal S). Non-inverted output Q of flip-flop 216
Becomes the transmission permission signal 205 (TxEn), and the signal 2
The set state ("1") of 05 permits the transmission operation. Similarly, the reception permission bit of the control register 240 is reflected on the signal 219. The signal 219 and the signal 211 are input to the AND gate 230, and the logical product thereof is used as a set signal of the flip-flop 217 (input signal of the terminal S). The non-inverted output Q of the flip-flop 217 becomes the reception permission signal 206 (RxEn), and the set state (“1”) of the signal 206 permits the reception operation. The description of the signal 211 will be described later.

In the input / output control circuit 103, the transmitting unit 101
Transmission data transfer request signal 203 (TR
eq), the flip-flop 214 is set, and its output is transmitted data load request signal 207 (Ldre
q) is output to the data transfer control circuit 104. Similarly, the received data transfer request signal 204 (R-Req) output from the receiving unit 102 causes the flip-flop 215
Is set, and the output is the received data store request signal 2
08 (Streq). After the data transfer control circuit 2 starts the transfer in response to the transmission data load request signal 207 and the reception data store request signal 208, the data transfer start signal 21 output from the transfer control circuit 104
2 and 213 are the flip-flops 214 and 2 respectively.
Fifteen reset terminals (R) are input, and the outputs 207 and 208 of the flip-flop are reset.

Next, a configuration for stopping the operation of the part related to transmission and reception in synchronization with the completion of the transmission and reception operation will be described. When the transmission unit 101 completes the transmission operation, the transmission unit 101 transmits a transmission data transfer request signal 203 for the next transmission.
Is output as “1”. The flip-flop 223 is
Set by “1” of the transmission data transfer request 203,
The signal 225 of “1” is output. Similar processing is performed in the receiving operation, and the “1” of the received data transfer request signal 204 causes the flip-flop 222 to output a “1” signal 224.
Is output. The AND gate 226 outputs the signal 22
The logical product of 4,225 is output. When the signal 218 is “0”, the AND gate 227 outputs the output of the AND gate 226 to the reset terminal R of the flip-flop 221. The flip-flop 221 is reset when the output of the AND gate 227 is "1". Control signal 218 (W
ake-up) is a signal for causing the serial interface circuit 1 to start the next communication operation by "1". The output of the AND gate 227 becomes "1" because the signal 218 is "0" and the flip-flops 222 and 224 are set by the transmission data transfer request signal 203 and the reception data transfer request signal 204, respectively. It is time. This is when the transmission / reception units 101 and 102 have both completed the transmission / reception operation, and the serial interface circuit 1 has not been instructed to start the next communication operation. At this time, the non-inverted output signal 211 of the flip-flop 221 is set to “0”, and the inverted output signal 209 (TR-End) is set to “1”.

The signal 209 indicates the end state of the transmission / reception operation in the serial interface 1 by "1" and is supplied to the operation cycle control circuit 3.

The signal "0" 211 resets the flip-flops 216 and 217 for generating the transmission permission signal 205 and the reception permission signal 206. That is, the output signals 219 and 220 of the control register 240 are "1".
When the signal 211 becomes "0", the outputs of the AND gates 232 and 228 become "1", the transmission permission signal 205 and the reception permission signal 206 become "0", and transmission and reception are not performed.

The signal 211 is used for controlling the input of the external input / output clock signal fCLK via the AND gate 229. When the signal 211 becomes "0", the clock signal fCLK is transmitted to the output 210 of the AND gate 229. However, the operation of the circuit part operating using the clock signal fCLK is stopped. AND Gate 2
29 is connected to the clock input terminals of the transmission unit 101 and the reception unit 102 included in the serial interface circuit 1, and when the output 210 stops changing, many circuits having the output 210 as an input are provided. Stops operation. For example, in the case of a CMOS circuit, a circuit operated in response to the clock signal fCLK does not perform a charging / discharging operation during a transient response, and power consumption is significantly reduced.

When the signal 218 becomes "1" while the clock signal fCLK is stopped, the flip-flop 2
21 is set, and the clock signal fCLK is transmitted as an output signal 210 to the transmitting unit 101 and the receiving unit 102 via the AND gate 229. At the same time AND gate 23
The flip-flops 216 and 217 connected via 0 and 231 are set according to the value of the transmission / reception permission bit of the control register, and the transmission / reception permission signals 205 and 206 are activated to "1" and transmitted. The unit 101 and the receiving unit 102 are made operable.

<< Data Transfer Control Circuit >> FIG. 3 shows an example of the transfer control circuit 104. Bus arbitration circuit 300
Is a transfer request signal 332 from the CPU 6 and a transmission data transfer request signal 207 supplied from the input / output control circuit 103.
And one of the received data transmission request signals 208 is selected, and the right to use the bus is given to the source of the selected signal. When the bus arbitration circuit 300 gives the bus use right to the transfer request signal 332 from the CPU 6 or the transmission data transfer signal 207 supplied from the input / output control circuit 103 as a transfer request circuit, the bus arbitration circuit 300 changes the flip-flop 315 by the signal 311. In the set state, when the right to use the bus is given in response to the request by the received data transfer signal 208 supplied from the input / output control circuit 103 as the transfer request circuit, the flip-flop 314 is set in the signal 310. The non-inverted output 312 of the flip-flop 314 is supplied to the buffer write circuit 110 and the memory read circuit 105, and the non-inverted output 313 of the flip-flop 315 is supplied to the buffer read circuit 109 and the memory write circuit 106. Flip-flops 314, 31
The reset signal (R) is supplied to the reset terminal (R) 5 from the memory read circuit 105 and the memory write circuit 106 after the transfer operation is completed.

The AND gate 303 outputs a signal (BUSRD)
Y) 330 is output. This signal 330 is output from the inverted outputs 320 and 321 of the two flip-flops 314 and 315.
Are both "1", the CPU 6 is permitted to use the bus. Before the start of the first transmission operation, it is assumed that none of the flip-flops 314 and 315 has been set. At this time, the bus use permission signal 330 output from the AND gate 303 is set to "1". . CPU4
In this state, various instructions can be executed using the bus.

In the bus arbitration circuit 300, the transfer request signal 332 from the CPU 6 or the transmission data transfer signal 207 supplied from the input / output control circuit 103 is applied to the AND gate 302 via the OR gate 304, An inverted output 320 of 314 is provided. Therefore, when the flip-flop 314 is reset, the transfer request signal 33
2 is supplied, a transfer request signal 332 from the CPU 6 is transmitted.
Is selected.

When the flip-flop 315 is set, the transmission data transfer signal 313 is set to “1”, and the memory write circuit 106 and the buffer read circuit 10
9 to transfer the received data from the reception buffer 108 to the memory 5, and activate the operations of the circuits 106 and 109.

When set to the set state, the flip-flop 314 sets the transmission data transfer signal 312 to “1”, and sets the transmission data transfer signal 312 to “1”.
In order to transfer the transmission data from the memory 113 to the transmission buffer 107, the operation of the circuits 105 and 110 is started.

When the data transfer with the serial interface circuit 1 is completed, the bus use permission signal 330 for the CPU 4 is set to "1".

Bus use permission signal 330 for CPU 4
Is also used as an operation pause signal of the data transfer control circuit 2 and is input to the AND gate 305. When the restart instruction signal 331 from the operation cycle control circuit 3 is “0” in the non-instruction state (restart suppression state), the flip-flop 316 is reset, and the signal 334 becomes “0”. Signal 33
4 is supplied to an AND gate 306 functioning as an input gate of the clock signal InCLK, and when the signal 334 is “0”, the clock signal InCLK is supplied to the signal line 3 in the subsequent stage.
The supply to 33 is suppressed. The signal line 333 supplies a synchronous clock signal to the memory read circuit 105 and the memory write circuit 106, and the change in the clock signal is stopped on the signal line 333, whereby the circuit operation is stopped. In this idle state, when the signal 331 is set to “1”, the flip-flop 316 is inverted to the set state, the signal 334 is set to “1”, and the memory read circuit 105 and the memory write circuit 10
6, the supply of the clock signal InCLK is restarted, and the data transfer control circuit 2 becomes operable.

The transfer control circuit 104 shown here
Corresponds to the case where the serial interface circuit 1 has one communication channel. When a plurality of serial interface circuits 1 have a plurality of communication channels, FIG.
The circuit for controlling the bus right described in (1) can be configured by equipping 314, 315 flip-flop pairs for the number of communication channels.

<< Operation period control circuit >> Operation period control circuit 3
Is to control the operation of the part related to the serial interface in synchronization with the transmission / reception timing. FIG. 4 shows a detailed example of the operation cycle control circuit 3.

The value of the initial value register 413 is preset in the counter 410 by the reset signal RST. The reset signal RST is output from the CPU 4 without any particular limitation. The flip-flop 401 is set by the transmission / reception end signal 209 from the serial interface circuit 1, and the signal 420 is set to "1" in the set state. The signal 420 and the clock signal InCLK are input to the AND gate 404, and the signal 420 is “1”.
At this time, the clock signal InCLK is transmitted to the signal line 423. The output signal 423 of the AND gate 423 is
There are ten count clocks, and the counter 410 counts up by +1 every cycle of the count clock. The count value of the counter 410 is compared with the value of the period register 419 by the comparison circuit 416, and when both values match, the signal 218 is set to “1”. Signal 2 in "1" state
Reference numeral 18 also serves as a reset signal for the counter 410, and the count value of the counter 410 is initialized to "0" by the reset. As a result, the signal 218 is set to “1” at a predetermined interval.
The signal 218 in the “1” state functions as a signal (Wake-up) for restarting the operation of the circuit to which the signal 218 is supplied, as described above.

In FIG. 4, flip-flop 403, AND gate 406, counter 412, initial value register 4
15, and a circuit constituted by the comparison circuit 418
Signal 33 for restarting operation of data transfer control circuit 2
1 that starts the counting operation of the counter 412 in response to the "1" state of the signal 330 indicating the end state of the data transfer operation in the data transfer control circuit 2 and forms the restart signal 331. And the basic function is substantially the same as the circuit that generates the signal 218.

In FIG. 4, flip-flop 402, AND gate 405, counter 411, and initial value register 4
The circuit constituted by 14, the comparison circuit 417, and the flip-flop 440 is a circuit that forms a signal 340 for restarting the operation of the external device connected to the terminal unit 7. This circuit configuration is added to the circuit configuration that generates the signal 218 by adding a flip-flop 440 that is reset by the end of the communication operation notified by the signal 209 and is set to a set state by the matching result of the comparison circuit 417. Are different. The signal 340 is supplied to an external device (not shown) via the terminal unit 7. The flip-flop 440 is provided at the output stage of the signal 340 in consideration that the circuit for controlling the suspension and restart of the external device may have an arbitrary configuration.

If there are other circuits to be controlled, the required number of circuit configurations may be prepared. Note that the role of the initial value registers 413 to 415 is as follows. The circuit connected to the operation cycle control circuit 3 has a certain fixed time from the start of supplying the clock until the state becomes operable from the sleep state. Because it is necessary
By advancing the value of the counter by the value set in the initial value register only at the very beginning, the signal 218 and the like can be set to the "1" state before the communication operation is performed. Can be previously stabilized. still,
Before performing the communication operation, the value of the initial value
Should be initialized. Also, the period register 419
Can set individual data for each of the comparison circuits 416, 417, and 418, and can supply each set data to the corresponding comparison circuits 416, 417, and 418 in parallel.

<< System Configuration Example >> FIG. 5 shows an example of a data processing system in which an external device 502 is connected to the microcomputer MCU. External device 502
Is a microphone, for example, and has a communication module 503, which is connected to the terminal unit 7. A signal line 511 is a transmission system, and a signal line 510 is provided.
Denotes a receiving system, and the signal line 512 denotes a transmission system of a communication clock such as fCLK. The transmission and reception signal lines include a transfer synchronization signal and the like in addition to the data lines as necessary. Here, for the sake of simplicity, the figures are collectively described as a transmission system or a reception system. In addition, a signal line 513 is used as a signal for controlling an external device by a microcomputer MC.
U is connected to the external device 502. Signal line 513
Is supplied with the control signal 340, for example. Signal 34
0 is set to the “0” state in the end state of the transmission / reception operation in the serial interface circuit 1, and is periodically set to the “1” state. When the external device 502 is, for example, a microphone, the microcomputer MCU only needs to input an audio signal every fixed sampling period. Therefore, data of a period responding to the sampling period should be set in the period register 419. , External device 502
The operation can be repeatedly started and stopped every sampling period, and power consumption can be reduced in the external device 502 as well. When the external device has a plurality of communication circuits, it is sufficient that each of the communication circuits has a terminal capable of controlling the operation state and the sleep state.

FIG. 6 is a timing chart showing main signal states when the system of FIG. 5 is operated. In the first data transfer, the serial interface circuit 1,
Since both the data transfer control circuits 2 are in the operating state, the wake-up such as 218 and 331 (only Wa
Communication is started without a signal. Here, a state in which transmission and reception are performed simultaneously is shown. The transmission / reception operation is started according to the transmission / reception transfer synchronization signal. When the transmission / reception is completed, the T-Req signal 203 and the R-Req signal 204 are output to the data transfer control circuit 2. When the next transmission data is transferred to the transmission buffer 107, T-Req
The signal 203 is reset. Next, when the reception data is transferred from the reception buffer 108 to the memory 5, R-Req
The signal 204 is reset. When both the T-Req signal 203 and the R-Req signal 204 are reset, TR-E
The nd signal 209 is set, indicating that the transmission / reception operation has been completed. From this point, the counter 410 of the operation cycle control circuit 3 starts operating. Serial interface circuit 1
Indicates that the data transfer control circuit 2
When the data transfer to and from the buffers 107 and 108 is completed, the supply of the clock signals fCLK and InCLK to the predetermined internal circuits is automatically stopped, respectively, and the apparatus enters a sleep state. The control signal 340 to the external device 502 is. TR-En
The external device 502 is reset when the d signal 209 is set, and the external device 502 enters a sleep state. Next, when the values of the counters 410 and 411 of the operation cycle control circuit 3 match the value of the preset cycle register 419, Wake-up is performed.
The signals 218 and 340 are set to "1" and output. The output timing of the “1” state is determined by the initial value register 419.
It depends on the setting. In this example, first, the Wake-up signal 218 of the serial interface circuit 1 is output.
And the signal 340 to the external device 501 are simultaneously set to the “1” state and output. This timing must be before the synchronization signal for data communication. The Wake-up signal 218 and the signal 340 cause the serial interface circuit 1 and the external device 502 to be in an operating state and enable communication. Wake-up signal 331 of data transfer control circuit 2 during transmission / reception in accordance with synchronization signal fCLK
Is set to the “1” state and output, and the data transfer control circuit 2
Becomes active, and the buffers 107 and 108 and the memory 5
Prepare for data transfer between and. When transmission / reception ends, the serial interface circuit 1 outputs a T-Req signal 203.
And an R-Req signal 204 to the data transfer control circuit 2. Thereafter, the same progress as the first time is followed, and the serial interface circuit 1, the data transfer control circuit 2, and the external device 502 repeat the operation state and the sleep state at intervals set in the cycle register 419.

As can be seen from this figure, the serial interface circuit 1, the data transfer control circuit 2, and the external device 50
2 is running, except in the first case,
From the "1" state of the ke-up signals 218, 331, and 340 to the output of the end signal from each circuit, the operation time is reliably shortened and the power consumption is reduced as compared with the case where the circuits are always operating. It becomes possible to reduce. As an example, consider the input and output of voice data in the telephone band. Usually, the sampling frequency of voice data in the telephone band is 8 kHz, and the resolution is 16 bits. For example, if the serial communication clock is 1
In the case of 3 MHz, the time required for data transfer of one sample is about 1.3 μs, and the time between two samples is 125 μs, which is the reciprocal of the sampling frequency. Of about 1%. Further, the data transfer between the buffers 107 and 108 and the memory 5 is usually performed by an internal clock signal (InCLK) faster than the communication clock signal (fCLK), and the data bus used for the transfer has a multi-bit parallel configuration. Therefore, the time required for data transfer is shorter.
It can be understood that the power consumption reduction effect obtained by bringing the circuits related to communication into the idle state during the time that is irrelevant to communication, which occupies most of the whole, is shown. This is the same for the external device 502 to be communicated. For example, if the external device 502 includes relatively large power consumption circuits such as an analog-to-digital conversion circuit for communication, stopping these circuits during periods of no communication reduces the power consumption of the entire system. In this respect, a great effect can be obtained.

<< Structural Example Using Enable Signal >> In the description so far, each circuit related to the serial interface automatically comes into a hibernate state after the operation is completed, and the Wake-up signals 218, 331 and 331 from the operation cycle control circuit 3 are provided. 340
Although the example in which the operation state is set in the above is described, an example in which the operation cycle control circuit 3 outputs a signal for directly controlling the operation state and the halt state of each circuit will be described. In the above description, the signals 218 and 331 shown in FIG. 1 are the Wake-up signals for transitioning the serial interface circuit 1 and the data transfer control circuit 2 from the sleep state to the operation state, respectively. , And an enable signal (hereinafter, referred to as an En signal) for directly controlling the transition of the operation state. In the first example described so far, the serial interface circuit 1 and the data transfer control circuit 2 automatically enter the sleep state when their operations are completed. However, in the second example described below, they are enabled (only En Also written)
The sleep state and the operation state are determined by the value of the signal.

FIG. 7 shows an input / output control circuit 1 according to the second example.
03 is shown. In the first example of FIG. 2, Wake-u
p signal 218 sets flip-flop 221 and
While the output of the clock fCLK was controlled, in FIG. 7, the En signal (Tx
Rx-En) 218 directly controls the clock fCLK via the AND gate 721. The transmission / reception permission signal 2
05 and 206 are also controlled by the En signal 218. Further, flip-flops 710 and 711 for generating a transmission / reception end signal are also reset by the En signal 218.

FIG. 8 shows a transfer control circuit 10 according to the second example.
Four examples are shown. In the first example of FIG. 3, the clock InCLK is controlled by the Wake-up signal 331 and the BUSRDY signal 330 for the data transfer control circuit setting or resetting the flip-flop 316 via the AND gate 305. In FIG. 8, the En signal 331 for the data transfer control circuit is
6, the gate control of the clock InCLK is performed directly.

FIG. 9 shows an example of the operation cycle control circuit 3 according to the second example. In FIG. 4, since the Wake-up signals 218 and 331 are output to the serial interface circuit 1 and the data transfer control circuit 2, flip-flops are provided at the subsequent stage of the comparison circuits 416 and 418 of the respective signal generation circuits. Not. However, in the second example, while the two circuits 1 and 2 are operated, the respective En signals must be kept in the “1” state. Therefore, flip-flops 441 and 442 are provided in the output stage. I have. These flip-flops 441 and 442 are reset by operation end signals 209 and 330 of the serial interface circuit 1 and the data transfer control circuit 2, respectively. The other operation principle is the same as that of the control signal generation circuit of FIG.

In the configuration in which the En signal is used as the control signal, the transition of each signal is as shown in FIG. The difference from the example of FIG. 6 is that the En signal is maintained at “1” during the operation of each circuit because the control signal has changed from the Wake-up signal to the En signal. In this example, unlike the first example, the serial interface circuit 1
And that the data transfer control circuit 2 does not automatically go into a halt state.
The same as the example.

<< Configuration Considering Data Transfer Interval >> In the first and second examples described above, the data communication interval is one.
This is a case where it is longer than the time required for communication of two data. In the case where the communication interval is short, if the operation state and the sleep state are switched for each data communication, the power consumption may not be reduced. For example, in the European digital mobile phone standard, 577 every 4.615 msec.
During the period of μsec, the transmission and reception of the encoded data is about 1.84.
This is performed at intervals of 5 μsec. At this time, the time required for communication of the encoded data is 1.23 μsec, and most of the data transmission / reception interval is used for transmission / reception itself. Furthermore, since a certain period of time is required for the circuit to enter the operating state, it is necessary to start transitioning from the sleep state to the operable state before the communication actually starts. For this reason, even if the circuit is in a halt state for this short period, the effect of lower power consumption cannot be expected as far to the left. In this way, when the data communication interval is short, it is more efficient to keep the operation state during the period of continuous communication, and to put the system into a pause state until the next communication starts when the continuous communication ends. Is good. In order to realize this, the operation cycle control circuit 3 illustrated in FIG. 11 can be employed.

The operation cycle control circuit 3 shown in FIG.
, A data number register 550 and a counter 55
1, 552, 553 and comparison circuits 554, 555, 55
6 and a bus 557 are added. The bus 5
57 is a data number register 550 and comparison circuits 554,5
55 and 556 are connected. The data number register 550 stores the number of data for continuously operating the circuit. The counters 551, 552, 553 count up by one for each "1" state of the communication operation end signals 209, 330 of the respective circuits each time one data is communicated. 555,556
Is compared with the value of the data number register 550. When the values of the counters 551, 552, 553 match the value of the data number register 1150, the comparison circuits 554,
555 and 556 cause flip-flops 441 and 44
0, 442 are reset and signals 218, 340, 33
The 1 En signal is reset (instruction to suspend operation). Thus, in the case of data having a short transfer interval, E is equal to the number of data set in the data number register 550.
The n signal can be kept at "1". 218, 34
The set timing (instruction state for enabling the operation) of each En signal of 0, 331 is determined by the period register 41 as described above.
9 is set. FIG. 12 shows an example of the signal waveform of the signal 331. The signal 331 maintains a high level during the communication operation of the code data over a plurality of cycles.

In terms of generating a signal waveform such as the signal 331 in FIG. 12, such a signal waveform can be generated by using a timer counter. For example, as illustrated in FIG. 13, the timer counter inverts the output when the count value matches the preset set value 1 and set value 2. Set values 1 and 2 as comparison values are set in the timer counter so that the output signal is inverted at the timing of starting and ending the data transfer. For this timer counter, a timer counter function as one of the peripheral functions mounted on the microcomputer can be used, but in this case, the serial interface circuit 1 and the data transfer control circuit 2 are the same as those described above. It goes without saying that a configuration must be provided.

<< Configuration Having a Plurality of Serial Interface Circuits >> The above example is an example of a case where one serial communication channel and one data transfer channel are involved. However, when the present invention is applied to a configuration having a plurality of them, New circuits may need to be added.
For example, when it is assumed that a plurality of data transfer channels are provided, FIG.
A circuit for generating the signal 331 is provided separately. However, when each data transfer channel shares a clock signal supply system and one data transfer channel stops supplying the clock signal, the effect of all other In this case, the data transfer control operation is inconvenient. For example, in a mobile phone or the like, when the serial interface circuit transmits and receives voice data and encoded data, the interval between both data communications is different. Considering GSM which is a European mobile phone standard as a specific example, the interval at which data is input to the serial interface circuit is 125 μsec for audio data and about 1.845 μsec for encoded data. However, the encoded data is received every 4.615 msec for a period of 577 μsec. At this time, the time required for the communication of the encoded data is 1.23 μsec. If a plurality of data transfer control circuits share a clock supply circuit, for example, if the data transfer control circuit for audio data stops supplying the clock, the transfer of encoded data with different transfer intervals will not be performed, and the system The whole will not work. In such a case, the En signal of each circuit sharing the clock supply circuit may be input to the OR circuit, and the stop of the clock supply may be controlled by the OR signal. FIG. 14 shows an example in which the serial interface circuit transmits and receives audio data and encoded data at different communication intervals. In FIG. 14, the data transfer circuit En signal is a logical sum signal of the audio data data transfer circuit En signal and the code data data transfer circuit En signal. When a plurality of circuits sharing a clock supply circuit perform data communication with different communication intervals, the entire operation is controlled by controlling the circuits by the logical sum of the En signals of the respective circuits as in the example of FIG. Can be performed normally.

The invention made by the inventor has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the configuration of FIG. 1 is not limited to one chip. For example, the memory may be constituted by a chip different from the microcomputer. Although the effect of low power consumption is reduced, it is also possible to exclude a data transfer control circuit such as a DMAC from the control target of the operation cycle control circuit.
The end of the external interface operation means a state in which data reception for each reception unit (or data multiple times the reception unit) is completed, and data transmission for each transmission unit (or data multiple times the transmission unit) is completed. Means the state. Transmission buffer and reception buffer are data registers or FIFO
It can be constituted by a memory or the like. The operation clock signal of the external interface control circuit is not limited to a synchronous clock signal such as fCLK supplied from outside, and may be a clock signal inside the data processing device according to the interface specifications. The peripheral circuit mounted on the microcomputer is not limited to the circuit illustrated in FIG. 1, and may include other appropriate peripheral circuits. A serial interface circuit, which is an example of an external interface control circuit, includes a so-called SCI (serial communication interface) including three lines of an input / output clock line, an input data line, and an output data line, and an input clock line. , An output clock line, an input data line, an output data line, an input frame signal line, and an output frame signal line.

[0069]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the first aspect of the present invention,
When the central processing unit sets the cycle in the operation cycle control circuit when the external interface control circuit periodically performs a communication operation, the operation of the external interface control circuit and the data transfer control circuit is automatically suspended, and then the operation is performed. The cycle control circuit can make the external interface control circuit, the data transfer control circuit, and the like operable again in that cycle.

According to the second aspect of the present invention, the suspension of the operation of the external interface control circuit and the data transfer control circuit can be controlled by the operation cycle control circuit.

According to the third aspect of the present invention, in the periodic external interface operation of the external interface control circuit, periodic clock supply stop / restart can be realized for each multiple of data of the data transfer unit.

Therefore, wasteful power consumption can be suppressed when the external interface control circuit and the data transfer control circuit do not need to substantially operate in the periodic external interface operation. ,
Since the control is performed by the operation cycle control circuit, the above effect can be obtained without imposing a large load on the central processing unit. Further, it is possible to contribute to a reduction in power consumption of an external device connected to the external interface control circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microcomputer which is an example of a data processing device according to the present invention.

FIG. 2 is a logic circuit diagram showing a detailed example of an input / output control circuit.

FIG. 3 is a logic circuit diagram illustrating an example of a transfer control circuit.

FIG. 4 is a logic circuit diagram showing a detailed example of an operation cycle control circuit.

FIG. 5 is a block diagram illustrating an example of a data processing system in which an external device is connected to a microcomputer.

6 is a timing chart showing main signal states when the system of FIG. 5 is operated.

FIG. 7 is a logic circuit diagram showing a second example of the input / output control circuit using the operation enable signal periodically generated by the operation cycle control circuit.

FIG. 8 is a logic circuit diagram showing a second example of the transfer control circuit using the operation enable signal periodically generated by the operation cycle control circuit.

FIG. 9 is a logic circuit diagram showing a second example of an operation cycle control circuit that periodically generates an operation enable signal.

FIG. 10 is a timing chart showing states of main signals when the configuration according to the second example using the operation enable signal is operated.

FIG. 11 is a block diagram showing still another example of the operation cycle control circuit which controls the suspension of the operation every time the transmission operation of the data having a multiple of the transfer unit is completed.

12 is a timing chart showing an example of a waveform of an enable signal obtained by the configuration of FIG.

FIG. 13 is an explanatory diagram of a case where a waveform of an enable signal obtained by the configuration of FIG. 11 is generated using a timer counter.

FIG. 14 is a timing chart showing an example of an operation when the serial interface circuit transmits and receives audio data and encoded data at different communication intervals.

[Explanation of symbols]

MCU microcomputer fCLK clock signal InCLK clock signal 1 serial interface circuit 2 data transfer control circuit 3 operation cycle control circuit 4 central processing unit 5 memory 101 transmission circuit 102 reception circuit 103 input / output control circuit 104 transfer control circuit 105 memory read circuit 106 memory Write circuit 107 Send buffer 108 Receive buffer 109 Buffer read circuit 110 Buffer write circuit 114 Internal bus 203 Send data transfer request signal 204 Receive data transfer request signal 205 Send enable signal 206 Receive enable signal 207 Send data load request signal 208 Receive data store request Signal 209 Transmission / reception end signal 218 Wake-up signal and enable signal to serial interface circuit 330 Data transfer End signal 331 Wake-up signal to transfer control circuit, enable signal 340 Wake-up signal to external device, enable signal

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yuki Inoue 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. Central Research Laboratory F-term (reference) 5B011 EB03 KK03 LL13 5B014 GE05

Claims (10)

[Claims] 1. A central processing unit, a memory, an external interface control circuit, a data transfer control circuit capable of controlling data transfer between the memory and the external interface control circuit, and an external interface operation by the external interface control circuit An operation cycle control circuit that controls a possible cycle of the external interface control circuit, wherein the external interface control circuit stops supplying the first operation clock signal to the external interface operation circuit in response to the end of the external interface operation. Notifying the end of the external interface operation to an operation cycle control circuit and a data transfer control circuit, wherein the data transfer control circuit responds to the end notification of the external interface operation, Start the data transfer operation with the interface control circuit, and When receiving an end notification of the external interface operation, the operation cycle control circuit causes the external interface control circuit to restart supply of the first operation clock signal after measuring a fixed time specified by the first cycle information. Providing an instruction, wherein the central processing unit sets the data transfer control condition in the data transfer control device and sets the first cycle information in the operation cycle control circuit. . 2. The data transfer control circuit further includes: a data transfer control circuit responsive to a completion notification of the external interface operation to the data transfer circuit in response to completion of the data transfer control operation between the memory and the external interface control circuit; Stopping the supply of the second operation clock signal, and notifying the end of the data transfer operation to the operation cycle control circuit. The operation cycle control circuit further includes, when notified of the end of the data transfer operation, By giving an instruction to restart the supply of the second operation clock signal to the data transfer control circuit after measuring a certain time specified by the second cycle information, a cycle in which the data transfer operation can be performed by the data transfer control circuit The central processing unit may further control the operation cycle control circuit to perform a second operation.
2. The data processing apparatus according to claim 1, wherein the cycle information is set. 3. The operation cycle control circuit is further set to an inactive state when the external interface operation end notification is received, and is set to an active state after measuring a predetermined time specified by third cycle information. The central processing unit further generates an external control enable signal;
3. The data processing apparatus according to claim 1, wherein the cycle information is set. 4. A central processing unit, a memory, an external interface control circuit, a data transfer control circuit capable of controlling data transfer between the memory and the external interface control circuit, and an external interface operation by the external interface control circuit An operation cycle control circuit for controlling a possible cycle, wherein the external interface control circuit notifies an end of the external interface operation to the operation cycle control circuit and the data transfer control circuit, and the data transfer control circuit includes the external interface In response to the operation end notification, the data transfer operation between the memory and the external interface control circuit is started in accordance with the data transfer control condition. The external interface operation enable signal is deactivated. The external interface operation enable signal is activated after measuring a predetermined time specified by the first cycle information, and the external interface control circuit responds to the external interface operation enable signal active state. To start supplying the first operation clock signal to the external interface operation circuit, and responds to the inactive state of the enable signal of the external interface operation by supplying the first operation clock signal to the external interface operation circuit. Stopping the supply, the central processing unit sets the data transfer control condition in the data transfer control device,
A data processing device for setting the period information of the data. 5. The data transfer control circuit further notifies the operation cycle control circuit of the end of the data transfer operation between the memory and the external interface control circuit in response to the end notification of the external interface operation, The operation cycle control circuit further deactivates the enable signal of the data transfer operation by the data transfer control device when receiving the end notification of the data transfer operation, and measures a certain time specified by the second cycle information. After that, the enable signal of the data transfer operation is activated to control the cycle in which the data transfer control circuit can perform the data transfer control operation, and the data transfer control circuit controls the enable signal of the data transfer operation. The supply of the second operation clock signal to the data transfer operation circuit is started in response to the active state of In response to the inactive state of the enable signal data transfer operation to stop the supply of the second operation clock signal to the data transfer operation for the circuit, the central processing unit further includes a first said operation cycle the control circuit 2
5. The data processing apparatus according to claim 4, wherein the cycle information is set. 6. The operation cycle control circuit is further set to an inactive state when the external interface operation end notification is received, and is set to an active state after measuring a certain time specified by third cycle information. The central processing unit further generates an external control enable signal;
The data processing apparatus according to claim 4 or 5, wherein the cycle information is set. 7. A central processing unit, a memory, an external interface control circuit, a data transfer control circuit capable of controlling data transfer between the memory and the external interface control circuit, and an external interface operation by the external interface control circuit An operation cycle control circuit for controlling a possible cycle, wherein the external interface control circuit notifies an end of the external interface operation to the operation cycle control circuit and the data transfer control circuit, and the data transfer control circuit includes the external interface In response to the operation end notification, in accordance with a data transfer control condition, activate a data transfer operation between the memory and the external interface control circuit, wherein the operation cycle control circuit performs the number of times of the external interface operation end notification. The external interface operation when And the enable signal of the external interface operation is activated after measuring a certain time specified by the first cycle information, and the external interface control circuit comprises an enable signal of the external interface operation Starts the supply of the first operation clock signal to the external interface operation circuit in response to the active state of the external interface operation circuit, and responds to the inactive state of the external interface operation enable signal in response to the first operation clock signal to the external interface operation circuit. The central processing unit sets the data transfer control condition in the data transfer control device, and sends the first repetition number and the first cycle information to the operation cycle control circuit. A data processing device characterized by setting. 8. The data transfer control circuit further notifies the operation cycle control circuit of the end of the data transfer operation between the memory and the external interface control circuit in response to the end notification of the external interface operation, The operation cycle control circuit further sets an enable signal of the data transfer operation by the data transfer control device to an inactive state when the number of times of the end notification of the data transfer operation reaches a second repetition number, and By activating the enable signal of the data transfer operation after measuring a certain time specified by the following, it is possible to control a period in which the data transfer control circuit can perform the data transfer control operation, and the data transfer control circuit A second operation clock signal to the data transfer operation circuit in response to the activation state of the enable signal of the data transfer operation; Starting the supply, stopping the supply of the second operation clock signal to the data transfer operation circuit in response to the inactive state of the enable signal of the data transfer operation, wherein the central processing unit further controls the operation cycle control 8. The data processing apparatus according to claim 7, wherein the second repetition number and the second cycle information are set in a circuit. 9. The operation cycle control circuit is further set to an inactive state when the number of times of the end notification of the external interface operation reaches a third repetition number, and sets a fixed time designated by the third cycle information. An external control enable signal that is activated after measurement is generated, and the central processing unit further sets the third repetition number and third cycle information in the operation cycle control circuit. 9. The data processing device according to claim 7, wherein: 10. The external interface control circuit is a serial interface circuit, the data transfer control circuit is a direct memory access controller,
10. The data processing device according to claim 1, wherein the data processing device is a microcomputer formed on one semiconductor chip.