JP2007241936A - Data transfer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce wasteful power consumption by stopping an unnecessary clock during data transfer. <P>SOLUTION: This data transfer circuit comprises a selector 54 for selectively supplying a bus clock BCK or an audio clock ACK to a RAM 20 according to a clock selection signal CLS, and a clock generation circuit 34 capable of stopping output of the bus clock BCK by a clock control signal BCC. When operation of a CPU 1A is unneeded, a FF (Flip Flop) 56 is set by the clock stop signal BCS to stop the operation of the clock generation circuit 34, whereby unnecessary power consumption by wasteful clock supply is reduced. When data in the RAM 20 is completely read out, an interruption signal INT is outputted from an I/F 10A, and the clock generation circuit 34 is activated to restart the operation by the CPU 1A. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data transfer circuit that reads out music data or the like once stored in a memory from a processor in synchronization with a low-speed clock signal and transfers the data to a sound source processing circuit or the like, and more particularly to reduction in power consumption thereof.

FIG. 2 is a block diagram showing an example of a conventional data transfer circuit.
This data transfer circuit is used for digital audio serial communication called I2S (Inter-IC Sound), and is a memory (Random Access Memory, hereinafter referred to as “RAM”) that can read and write music data at any time with a high-speed processor. ) Is read out, the music data is read out on the transmission circuit side, and transferred to an external data processing device such as a sound source processing circuit in accordance with a low-speed audio transfer clock.

  This data transfer circuit temporarily stores music data, an interface circuit (hereinafter referred to as “I / F”) 10 connected to a central processing unit (hereinafter referred to as “CPU”) 1 via a system bus 2. A RAM 20 used as a buffer, a transmission circuit 30 that reads out music data from the RAM 20 and transfers it to a sound source processing circuit in synchronization with an audio clock ACK for audio transfer, a clock generation circuit 40 that generates the audio clock ACK, and several It is composed of these logic circuits. The CPU 1, I / F 10, and RAM 20 are configured to operate in synchronization with the bus clock BCK output from the clock generation circuit 3.

  The I / F 10 is accessible from the CPU 1 side. The write address register (WREG) 11 is updated to the next write address each time data is written to the RAM 20, and updated to the next read address each time data is read from the RAM 20. A read address register (RREG) 12 is provided. Further, the I / F 10 outputs a chip enable signal CE, a write control signal WE, and input data DI to be written to the RAM 20 based on a data write request from the CPU 1 to the RAM 20, and a function from the transmission circuit 30 side. A function for holding access from the CPU 1 based on a wait signal WAIT given in accordance with a data read request and a function for outputting an interrupt signal INT to the CPU 1 when the data in the RAM 20 falls below a certain amount. ing.

  If the write state is specified by the write control signal WE when the RAM 20 is selected by the chip selection signal CS, the RAM 20 writes the input data DI to the address specified by the address signal MAD in synchronization with the bus clock BCK. If the write state is not designated by the write control signal WE when the chip select signal CS is selected, the data at the address designated by the address signal MAD is read and output as the output data DO. ing.

  The transmission circuit 30 takes in the output data DO output in parallel from the RAM 20, converts the output data DO into serial data OUT according to the audio clock ACK, and outputs the serial data OUT. The transmission circuit 30 outputs a transmission trigger signal TRG in order to read out the next output data from the RAM 20 every time the output data DO is fetched.

  The transmission trigger signal TRG is given to the differentiation circuit 51. The differentiating circuit 51 is supplied with the bus clock BCK, and outputs the wait signal WAIT for one clock cycle from the rising edge of the first bus clock BCK after the transmission trigger signal TRG is supplied. The wait signal WAIT is supplied to the I / F 10, one input side of a two-input negative OR gate (hereinafter referred to as “NOR”) 52, and a selection terminal of the selector 53.

  A chip enable signal CE for the RAM 20 is supplied from the I / F 10 to the other input side of the NOR 52, and a chip selection signal CS for the RAM 20 is output from the output side of the NOR 52.

  Selector 53 selects write address WAD output from write address register 11 of I / F 10 and read address RAD output from read address register 12 in accordance with wait signal WAIT, and provides the same to RAM 20 as address signal MAD. It is. The selector 53 selects the read address RAD while the wait signal WAIT is being output.

  In this data transfer circuit, data writing from the CPU 1 to the RAM 20 and data reading from the transmission circuit 30 in the RAM 20 are performed asynchronously. However, since the data read out by the transmission circuit 30 is converted into an acoustic signal by the external sound source processing circuit and output, the data is read by the transmission circuit 30 when a data write request and a read request to the RAM 20 occur simultaneously. Reading is prioritized. Further, the RAM 20 is accessed in synchronization with the same bus clock BCK as that of the CPU 1 so that the processing capability of the CPU 1 is not lowered even in the case of reading from the transmission circuit 30.

  That is, when the transmission trigger signal TRG, which is a data read request, is output from the transmission circuit 30, the wait signal WAIT for one clock cycle is output from the differentiation circuit 51 in synchronization with the bus clock BCK. When the wait signal WAIT is output, the I / F 10 suppresses access from the CPU 1. Further, the chip selection signal CS is output from the NOR 52 to the RAM 20, and the read address RAD is selected by the selector 53 and applied to the RA 20 as the address signal MAD.

  As a result, the data at the read address RAD is read from the RAM 20 and applied to the transmission circuit 30 as output data DO. The transmission circuit 30 takes in the output data DO, converts it into serial data OUT, and outputs it to the sound source processing circuit.

  The I / F 10 outputs an interrupt signal INT to the CPU 1 when the amount of data in the RAM 20 becomes equal to or less than a predetermined amount by reading to the RAM 20. As a result, the music data is written from the CPU 1 to the RAM 20 and the data is replenished.

JP 2000-181484 A

  In the above-mentioned patent document 1, in communication using a serial interface circuit, the supply of the operation clock to the reception unit and the transmission unit of the serial interface circuit is stopped during a period when the communication operation is not actually performed. A data processing device is described that reduces the required power consumption.

  However, in the data transfer circuit (including the data processing device of Patent Document 1), not only the clock for serial transfer but also the bus clock cannot be stopped during serial data transfer. For this reason, even after the data has been written to the RAM, even when the CPU processing is no longer necessary, the bus clock must be constantly output as long as serial data transfer is being performed, which makes it difficult to reduce power consumption. It was.

  An object of the present invention is to reduce power consumption by stopping unnecessary bus clocks during data transfer.

  The present invention provides a data transfer circuit for transmitting data from a CPU operating in accordance with a first clock signal to a data processing device in accordance with a second clock signal, a memory for storing data output from the CPU in accordance with a memory clock signal, A first clock generation circuit that starts outputting the first clock signal according to a reset signal and stops outputting the first clock signal when a stop signal is given from the CPU, and the control according to the control of the CPU A second clock generation circuit for outputting a second clock signal; and a clock selection for selecting the first or second clock signal in accordance with a clock selection signal supplied from the CPU and supplying the memory clock signal to the memory Read data from the memory according to the circuit and the second clock signal A transmission circuit for outputting to the data processing apparatus Te, the data in the memory is characterized by being configured to include a I / F for outputting the reset signal when reaching a predetermined amount.

  The present invention includes a clock selection circuit that selects the first or second clock signal in accordance with the clock selection signal and supplies the selected clock signal to the memory, and outputs the first clock signal supplied to the CPU in response to a stop signal from the CPU. A first clock generation circuit for stopping the operation. Thereby, when operation | movement of CPU becomes unnecessary by this, a 1st clock signal can be stopped and there exists an effect that the unnecessary power consumption by clock supply can be reduced.

  The present invention can be applied not only to data transfer from the CPU to the data processing apparatus but also to data transfer from the data processing apparatus to the CPU.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

  FIG. 1 is a configuration diagram of a data transfer circuit showing a first embodiment of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.

  The data transfer circuit includes an I / F 10A connected to the CPU 1A via the system bus 2, a RAM 20 used as a buffer for temporarily storing music data, and a low-speed audio transfer (reading music data from the RAM 20). For example, the transmission circuit 30 is configured to be transferred to a sound source processing circuit in synchronization with an audio clock ACK of 1 MHz), a clock generation circuit 40A that generates the audio clock ACK, and several logic circuits. The CPU 1A and the I / F 10A are configured to operate in synchronization with a high-speed (for example, 120 MHz) bus clock BCK output from the clock generation circuit 3A.

  The CPU 1A is connected to the I / F 10A and various functional blocks (not shown) via the system bus 2, and also stops the operation of the clock generation circuit 40A and the clock stop signal BCS for stopping the operation of the clock generation circuit 3A. A function of outputting a clock stop signal ACS for the The clock stop signal BCS is connected to a set terminal S of an SR flip-flop (hereinafter referred to as “FF”) 56, and a clock control signal BCC output from the FF 56 is supplied to the clock generation circuit 3A. ing. On the other hand, the clock stop signal ACS is supplied to the clock generation circuit 40A as it is.

  The I / F 10A has a write address register 11 that is accessible from the CPU 1A side and is updated to the next write address each time data is written to the RAM 20, and a clock selection register (CREG) 13. Further, the I / F 10A outputs a chip enable signal CE, a write control signal WE, and input data DI to be written to the RAM 20 based on a data write request from the CPU 1A to the RAM 20, and a function from the transmission circuit 30 side. A function for holding a request from the CPU 1A based on a wait signal WAIT given in accordance with a data read request, and a function for outputting an interrupt signal INT to the CPU 1A when data in the RAM 20 is read and lost. Yes. The interrupt signal INT is supplied to the reset terminal R of the FF 56 in addition to the CPU 1A.

  If the write state is specified by the write control signal WE when the RAM 20 is selected by the chip selection signal CS, the RAM 20 writes the input data DI to the address specified by the address signal MAD in synchronization with the bus clock BCK. If the write state is not designated by the write control signal WE when the chip select signal CS is selected, the data at the address designated by the address signal MAD is read and output as output data DO.

  The transmission circuit 30 operates according to the audio clock ACK, takes in the output data DO output in parallel from the RAM 20, converts the output data DO into serial data OUT according to the audio clock ACK, and outputs the serial data OUT. The transmission circuit 30 outputs the transmission trigger signal TRG in order to read the next output data from the RAM 20 after taking the output data DO.

  The transmission trigger signal TRG is given to the differentiation circuit 51. The differentiation circuit 51 is supplied with the memory clock MCK from the selector 54 and outputs a wait signal WAIT for one clock cycle from the rising edge of the first memory clock MCK after the transmission trigger signal TRG is applied. is there. The wait signal WAIT is supplied to the I / F 10A, one input side of the NOR 52, the selection terminal of the selector 53, and the clock terminal of the address counter 55. A chip enable signal CE for the RAM 20 is supplied from the I / F 10A to the other input side of the NOR 52, and a chip selection signal CS for the RAM 20 is output from the output side of the NOR 52.

  The address counter 55 is reset to 0 by an initial reset, and counts up one by one periodically to a predetermined value in synchronization with the fall of the wait signal WAIT. The count value of the address counter 55 is given to the selector 53 as the read address RAD.

  Selector 53 selects write address WAD output from write address register 11 of I / F 10A and read address RAD output from read address counter 55 in accordance with wait signal WAIT, and provides the same to RAM 20 as address signal MAD It is. In the selector 53, the read address RAD is selected while the wait signal WAIT is output.

  The selector 54 selects either the bus clock BCK or the audio clock ACK according to the clock selection signal CSL set in the clock selection register 13 of the I / F 10A, and outputs it as a memory clock MCK to the RAM 20 and the differentiation circuit 51. To do.

Next, the operation will be described.
(1) By the initial reset operation, the read address RAD of the address counter 55 is reset to 0, and the FF 56 is reset. As a result, the clock generation circuit 3A operates and the bus clock BCK is supplied to the CPU 1A and the I / F 10A. In the initial setting processing by the CPU 1A, the write address WAD of the write register 11 in the I / F 10A is set to 0, and the clock selection signal CSL for selecting the bus clock BCK is set in the clock selection register 13. Further, the CPU 1A outputs a clock stop signal ACS for stopping the operation of the clock generation circuit 40A, and the audio clock ACK is stopped.

(2) When music data to be transferred is generated by the processing of the CPU 1A, the CPU 1A writes music data for one song into the RAM 20 via the I / F 10A. After completing the writing of the music data, the CPU 1A rewrites the clock selection signal CSL in the clock selection register 13 with a signal for selecting the audio clock ACK.

(3) The CPU 1A stops outputting the clock stop signal ACS. Thus, the operation of the clock generation circuit 40A is started, and the audio clock ACK is given to the transmission circuit 30 and the selector 54.

(4) The operation of the transmission circuit 30 is started, and a transmission trigger signal TRG for reading the music data in the RAM 20 is output from the transmission circuit 30 and applied to the differentiation circuit 51.

  Since the audio clock ACK selected by the selector 54 is given to the differentiating circuit 51, the audio clock ACK for one cycle is output by the differentiating circuit 51 as the wait signal WAIT.

  The wait signal WAIT is supplied to the selector 53, and the read address RAD of the address counter 55 is selected by the selector 53 and supplied to the RAM 20 as the memory address MAD. Further, since the wait signal WAIT is given to the RAM 20 via the NOR 52 as the chip selection signal CS, the music data at the address specified by the read address RAD is read from the RAM 20 and given to the transmission circuit 30 as output data DO. . The transmission circuit 30 takes in the output data DO.

  When the wait signal WAIT stops, the address counter 55 counts up at the fall timing, and the next address to be read is set as the read address RAD.

(5) The transmission circuit 30 converts the captured output data DO into serial data OUT in synchronization with the audio clock ACK and outputs the serial data OUT to the sound source processing circuit. Further, the transmission circuit 30 outputs a transmission trigger signal TRG in order to read the next output data DO. Such a read operation of the RAM 20 is repeatedly performed by the transmission circuit 30.

(6) On the other hand, the CPU 1A sets the interrupt permitted state and outputs a clock stop signal BCS for stopping the operation of the clock generation circuit 3A. Accordingly, the FF 56 is set, the clock control signal BCC is output, and the operation of the clock generation circuit 3A is stopped. As a result, the bus clock BCK stops, and the circuits such as the CPU 1A that operate with the bus clock BCK stop. On the other hand, the transmission circuit 30 operating with the audio clock ACK continues to operate.

(7) When all the music data written in the RAM 20 is read, an interrupt signal INT is output from the I / F 10A. Accordingly, the FF 56 is reset, the clock control signal BCC is stopped, and the operation of the clock generation circuit 3A is restarted. As a result, the CPU 1A starts operating, and processing according to the interrupt signal INT is performed.

(8) The CPU 1A outputs the clock stop signal ACS to the clock generation circuit 40A to stop the audio clock ACK, and then rewrites the clock selection signal CSL in the clock selection register 13 to a signal for selecting the bus clock BCK. . As a result, the initial state of (2) is restored, and the next music data can be written to the RAM 20 from the CPU 1A.

  As described above, when the CPU 1A is not operating, the data transfer circuit according to the first embodiment reads out music data from the RAM 20 in synchronization with the low-speed audio clock ACK and operates the clock generation circuits 3A and 40A. The CPU 1A can be controlled. As a result, only a necessary clock can be supplied in accordance with the state of operation, and there is an advantage that power consumption due to an unnecessary clock can be reduced.

  In the data transfer circuit according to the first embodiment, the simple selector 54 is used to switch the memory clock MCK supplied to the RAM 20. Therefore, if the switching is inadvertently performed by the clock selection signal CSL, the pulse width having a very small pulse width depending on the timing is used. May generate a malfunction in the RAM 20 and the like. For this reason, as shown in the operation description of the first embodiment, the audio clock ACK needs to be stopped when the clock is switched.

  However, if the audio clock ACK is stopped while the serial data OUT is being output from the transmission circuit 30, there is a problem that the music being reproduced by the sound source processing circuit is interrupted. In order not to stop the audio clock ACK during music reproduction, it is necessary to store music data for one song in the RAM 20. Therefore, in the data transfer circuit according to the first embodiment, it is necessary to set the RAM 20 to a capacity capable of storing music data for one song.

  The second embodiment is intended to reduce the capacity of the RAM 20 by using a clock selection circuit that does not generate whiskers even if the clock is switched without stopping the audio clock ACK.

FIG. 3 is a circuit diagram of a clock selection circuit showing the second embodiment of the present invention.
The clock selection circuit 60 is provided in place of the selector 54 in FIG. 1, and the FF 61 that holds the audio clock ACK at the rising timing of the bus clock BCK and the signal FP1 of the output terminal Q of the FF 61 are on the same bus. It has an FF 62 held at the rising edge of the clock BCK, and an AND gate (hereinafter referred to as “AND”) 63 that takes the logical product of the signal FP2 and the signal FP1 of the inverting output terminal / Q of the FF62.

  The signal SL1 output from the AND 63 is given to the selection terminal of the selector 64. A clock selection signal CSL is given to the first input terminal of the selector 64, and the output side of the selector 64 is connected to the input terminal D of the FF 65. The bus terminal BCK is supplied to the clock terminal C of the FF 65, and the signal SL 2 of the output terminal Q of the FF 65 is supplied to the second input terminal of the selector 64 and also to the selection terminal of the selector 66. The selector 66 selects either the bus clock BCK or the audio clock ACK according to the signal SL2, and outputs it as the memory clock MCK.

  4A and 4B are signal waveform diagrams showing the operation of FIG. 3, FIG. 4A is a switching operation from the bus clock to the audio clock, and FIG. 4B is an audio clock to the bus clock. Switching operation to is shown.

  In the clock selection circuit 60, a differentiation signal (FF 61, 62 and AND 63) synchronized with the bus clock BCK generates a one-pulse selection signal SL1 from the rising edge of the low-speed audio clock ACK. The selection signal SL1 is used as a latch enable signal for the latch circuit (selector 64 and FF65), and the signal SL2 synchronized with the bus clock BCK is used as a selection signal for the selector 66 for clock switching.

  In switching from the bus clock BCK to the audio clock ACK, the audio clock ACK is switched to the audio clock ACK at a timing two clocks after the bus clock BCK after the audio clock ACK becomes level “H”. Therefore, both the bus clock BCK and the audio clock ACK are switched in the “H” state, and a whisker-like pulse is not generated.

  The switching from the audio clock ACK to the bus clock BCK is the same. After the audio clock ACK becomes “H”, the audio clock ACK is switched at the timing two clocks after the bus clock BCK. Therefore, both the bus clock BCK and the audio clock ACK are switched in the “H” state, and a whisker-like pulse is not generated.

  As described above, the clock selection circuit 60 according to the second embodiment can perform normal switching without generating a whisker-like pulse even when the audio clock ACK and the bus clock BCK are switched at an arbitrary timing. Therefore, by providing the clock selection circuit 60 in place of the selector 54 in FIG. 1, the bus clock BCK can be switched and used as the memory clock MCK of the RAM 20 without stopping the audio clock ACK. As a result, when the music data in the RAM 20 decreases to a certain amount or less, the interrupt signal INT is output from the I / F 10A to the CPU 1A, and the music data in the RAM 20 can be supplemented from the CPU 1A. There is an advantage that the capacity can be reduced.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) Although the transfer of music data has been described as an example, it can be similarly applied as a data transfer circuit in a system in which the bus clock and the data transfer clock have different speeds.
(B) Although the circuit on the data transmission side has been described, the present invention can be similarly applied to the circuit on the data reception side. In that case, a receiving circuit is provided instead of the transmitting circuit 30 in FIG. 1, and the data received from the data processing device by this receiving circuit is written into the RAM 20 according to the audio clock ACK, and a certain amount of data is accumulated in the RAM 20. Sometimes, the data of the RAM 20 may be read from the CPU 1A according to the bus clock BCK.
(C) As a memory for storing data for transfer, a general RAM that reads and writes data to and from the address according to the memory address MAD has been shown, but a FIFO that reads data in the order in which it was written without giving an address signal from the outside. If a (first-in first-out) buffer is used, the circuit configuration can be simplified.

It is a block diagram of the data transfer circuit which shows Example 1 of this invention. It is a block diagram which shows an example of the conventional data transfer circuit. It is a circuit diagram of a clock selection circuit showing a second embodiment of the present invention. FIG. 4 is a signal waveform diagram illustrating the operation of FIG. 3.

Explanation of symbols

1A CPU (Central Processing Processor)
2 System bus 3A, 40A Clock generation circuit 10A I / F (interface circuit)
20 RAM (Read / write memory as needed)
30 Transmission Circuit 51 Differentiation Circuit 52 NOR (Negative OR Gate)
53, 54 selector 55 address counter 56 FF (flip-flop)
60 Clock selection circuit

Claims (3)

A data transfer circuit for transmitting data in accordance with a second clock signal from a central processing processor operating in accordance with a first clock signal;
A memory for accumulating data output from the central processor according to a memory clock signal;
A first clock generation circuit that starts outputting the first clock signal according to a reset signal, and stops outputting the first clock signal when a stop signal is given from the central processing processor;
A second clock generation circuit for outputting the second clock signal according to the control of the central processor;
A clock selection circuit that selects the first or second clock signal in accordance with a clock selection signal supplied from the central processor and supplies the memory clock signal to the memory;
A transmission circuit for reading data from the memory according to the second clock signal and outputting the data to the data processing device;
An interface circuit that outputs the reset signal when data in the memory reaches a predetermined amount;
A data transfer circuit comprising: A data transfer circuit that receives data according to a second clock signal between a central processing processor that operates according to a first clock signal and a data processing device,
A receiving circuit for receiving the data according to the second clock signal from the data processing device;
A memory for storing the data received by the receiving circuit according to a memory clock signal;
A first clock generation circuit that starts outputting the first clock signal in accordance with a reset signal and stops outputting the first clock signal when a stop signal is given from the central processing processor;
A second clock generation circuit for outputting the second clock signal according to the control of the central processor;
A clock selection circuit that selects the first or second clock signal in accordance with a clock selection signal provided from the central processing processor and supplies the selected clock signal to the memory as the memory clock signal;
An interface circuit that outputs the reset signal when data in the memory reaches a predetermined amount;
A data transfer circuit comprising: The clock selection circuit includes:
A differentiating circuit for generating a first selection signal of one pulse from a rising edge of the second clock signal in synchronization with the first clock signal;
A latch circuit that selects the clock selection signal according to the first selection signal, holds the selected clock selection signal in accordance with the first clock signal, and generates a second selection signal;
A selection circuit that selects the first or second clock signal according to the second selection signal and outputs the memory clock;
3. The data transfer circuit according to claim 1, wherein the data transfer circuit is configured.

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