JP2008182277A - Production process of semiconductor device - Google Patents

Production process of semiconductor device Download PDF

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JP2008182277A
JP2008182277A JP2008109791A JP2008109791A JP2008182277A JP 2008182277 A JP2008182277 A JP 2008182277A JP 2008109791 A JP2008109791 A JP 2008109791A JP 2008109791 A JP2008109791 A JP 2008109791A JP 2008182277 A JP2008182277 A JP 2008182277A
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insulating substrate
semiconductor
resin
semiconductor chips
semiconductor device
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JP4780136B2 (en
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Masatoshi Yasunaga
雅敏 安永
Michitaka Kimura
通孝 木村
Satoshi Yamada
聡 山田
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a production process to improve the productivity and reliability of a package type semiconductor device. <P>SOLUTION: A plurality of semiconductor chips are attached and bump-connected on an insulation substrate with an attaching insulation resin; the chips are collectively encapsulated on the insulation substrate with a transfer molding resin; then the resultant is divided into individual semiconductor devices. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、半導体装置の製造方法に関し、特にその組み立て工程に関するものである。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an assembly process thereof.

図５を参照して、従来の半導体装置の製造方法について述べる。
従来、半導体チップを組み立てて半導体装置を製造する際、図５（ａ）に示すように、絶縁基板１を用意し、図５（ｂ）に示すように、絶縁基板１上に取付用樹脂２を用いて半導体チップ３を搭載する。次に、図５（ｃ）に示すように、半導体チップ３上の電極と絶縁基板１上に設けられた導電性のパターンを接続ワイヤ４にて電気的に接続したのち、図５（ｄ）に示すように、トランスファーモールド樹脂５によって絶縁基板１上の半導体チップ３を搭載した片側の全体を一括して封止する。
この後、図５（ｅ）に示すように、絶縁基板１上の半導体チップ３を搭載しない片側に外部接続のための電極ボール６を形成し、図５（ｆ）に示すように、最終工程として上記のトランスファーモールド樹脂５および絶縁基板１を、例えはダイシング法やレーザーカッティング法などによって同時に寸断して個々の半導体装置７を得る。 A conventional method for manufacturing a semiconductor device will be described with reference to FIG.
Conventionally, when a semiconductor device is manufactured by assembling a semiconductor chip, an insulating substrate 1 is prepared as shown in FIG. 5A, and a mounting resin 2 is formed on the insulating substrate 1 as shown in FIG. The semiconductor chip 3 is mounted using Next, as shown in FIG. 5 (c), the electrode on the semiconductor chip 3 and the conductive pattern provided on the insulating substrate 1 are electrically connected by the connection wire 4, and then FIG. 5 (d). As shown in FIG. 2, the entire one side on which the semiconductor chip 3 on the insulating substrate 1 is mounted is sealed together by the transfer mold resin 5.
Thereafter, as shown in FIG. 5E, an electrode ball 6 for external connection is formed on one side of the insulating substrate 1 on which the semiconductor chip 3 is not mounted, and as shown in FIG. As described above, the transfer mold resin 5 and the insulating substrate 1 are simultaneously cut by, for example, a dicing method or a laser cutting method to obtain individual semiconductor devices 7.

国際公開第９６／４２１０７号International Publication No. 96/42107

このような従来の半導体装置の製造方法に於いては、トランスファーモールド樹脂５によって封止する際に、比較的大きい絶縁基板１上を一括して封止するために、樹脂の注入速度や注入圧力を大きくする必要があり、このために接続ワイヤ４の変形、接続ワイヤ同士の電気的短絡、ワイヤ４接続部のはがれやワイヤ自身の断線による電気的開放等の致命的な欠陥を発生しやすい問題があった。
また、電気的接続方法として接続ワイヤを用いるため、このワイヤを張る領域が必要となり、半導体装置のサイズを小さくすることが困難であった。
この発明は、このような従来の課題を解決するためになされたもので、フリップチップ接続した一括封止タイプの製造方法により、生産性と信頼性を向上させることを目的とする。 In such a conventional method for manufacturing a semiconductor device, when sealing with the transfer mold resin 5, in order to collectively seal a relatively large insulating substrate 1, the resin injection speed and the injection pressure are used. For this reason, it is easy to cause fatal defects such as deformation of the connection wire 4, electrical short-circuit between the connection wires, peeling of the connection portion of the wire 4 or electrical release due to disconnection of the wire itself. was there.
Further, since a connection wire is used as an electrical connection method, a region for stretching this wire is required, and it is difficult to reduce the size of the semiconductor device.
The present invention has been made to solve such a conventional problem, and an object of the present invention is to improve productivity and reliability by a batch sealing type manufacturing method in which flip chips are connected.

請求項１の発明にかかる半導体装置の製造方法は、絶縁基板上に複数の半導体チップをバンプ接続する工程と、上記複数の半導体チップが一つのトランスファーモールド樹脂に覆われるように、上記複数の半導体チップを上記絶縁基板上に封止する工程と、上記絶縁基板上に樹脂封止された上記複数の半導体チップを個別の半導体装置に分離する工程とを含み、上記封止する工程の前に、上記絶縁基板と上記複数の半導体チップの間に設けられるように１個の板状の取付用絶縁樹脂を形成することを特徴とするものである。   According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a step of bump-connecting a plurality of semiconductor chips on an insulating substrate; and the plurality of semiconductor chips so that the plurality of semiconductor chips are covered with one transfer mold resin. Including a step of sealing a chip on the insulating substrate and a step of separating the plurality of semiconductor chips resin-sealed on the insulating substrate into individual semiconductor devices, and before the sealing step, One plate-like insulating resin for mounting is formed so as to be provided between the insulating substrate and the plurality of semiconductor chips.

請求項２の発明にかかる半導体装置の製造方法は、請求項１に記載の製造方法において、上記複数の半導体チップを、所定個数の半導体チップを含む未完全分離のチップ群状態でそれぞれ上記絶縁基板に取付けることを特徴とするものである。   According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect, wherein the plurality of semiconductor chips are each in an incompletely separated chip group state including a predetermined number of semiconductor chips. It is characterized by being attached to.

請求項３の発明にかかる半導体装置の製造方法は、請求項１に記載の製造方法において、上記複数の半導体チップを、未分離のウェーハ状態で上記絶縁基板に取付けることを特徴とするものである。   According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect, wherein the plurality of semiconductor chips are attached to the insulating substrate in an unseparated wafer state. .

本発明によれば、半導体チップを絶縁基板上にバンプ接続して一括封止した後、これを個々の半導体装置に分離するので、個々の半導体装置のサイズを小さくすることが可能となり、また半導体装置の取れ数を増大させることも可能となる。また、生産性を向上させることもできる。   According to the present invention, the semiconductor chip is bump-connected on the insulating substrate and collectively sealed, and then separated into individual semiconductor devices, so that the size of each semiconductor device can be reduced, and the semiconductor It is also possible to increase the number of devices to be taken. In addition, productivity can be improved.

実施の形態１．
以下に、この発明の実施の形態について説明する。図中、同一または相当する部分には同一の符号を付してその説明を簡略化ないし省略することがある。
本発明の実施の形態１を、図１を参照して説明する。
先ず、図１（ａ）に示すように、絶縁基板１０を用意する。
次に、図１（ｂ）に示すように、絶縁基板１０の上に取付用絶縁樹脂２０を用いて半導体チップ３０を搭載する。この際、同時に例えば半田や金からなる接続バンプ４０を介して、半導体チップ３０上の電極と絶縁基板上の導電性のパターンを電気的に接続する。 Embodiment 1 FIG.
Embodiments of the present invention will be described below. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof may be simplified or omitted.
A first embodiment of the present invention will be described with reference to FIG.
First, as shown in FIG. 1A, an insulating substrate 10 is prepared.
Next, as shown in FIG. 1B, the semiconductor chip 30 is mounted on the insulating substrate 10 using the mounting insulating resin 20. At this time, the electrodes on the semiconductor chip 30 and the conductive pattern on the insulating substrate are simultaneously electrically connected via the connection bumps 40 made of, for example, solder or gold.

次に、図１（ｃ）に示すように、トランスファーモールド樹脂５０によって絶縁基板１０上の半導体チップ３０を搭載した片側１０ａの全体を一括して封止する。
この後、図１（ｄ）に示すように、絶縁基板１０上の半導体チップ３０を搭載しない片側１０ｂに外部接続のための電極ボール６０を形成してもよい。
次に、図１（ｅ）に示すように、最終工程として上記のトランスファーモールド樹脂５０および絶縁基板１０を、例えばダイシング法やレーザーカッティング法などによって同時に寸断して個々の半導体装置７０を得る。 Next, as shown in FIG. 1C, the entire one side 10 a on which the semiconductor chip 30 on the insulating substrate 10 is mounted is collectively sealed with a transfer mold resin 50.
Thereafter, as shown in FIG. 1D, an electrode ball 60 for external connection may be formed on one side 10b on which the semiconductor chip 30 on the insulating substrate 10 is not mounted.
Next, as shown in FIG. 1E, as a final process, the transfer mold resin 50 and the insulating substrate 10 are simultaneously cut by, for example, a dicing method or a laser cutting method to obtain individual semiconductor devices 70.

尚、取付用絶縁樹脂２０のかわりに、絶縁樹脂中に導電性の微粒子が含まれたもの、即ち異方性導電樹脂を用いても同様の効果が得られる。
本実施の形態に於いては、半導体チップ３０上の電極と絶縁基板上の導電性のパターンの電気的接線に、接続ワイヤではなく接続バンプ４０を用いるため、トランスファーモールド樹脂５０によって封止する際に接続ワイヤの変形、電気的短絡、電気的開放などの致命的な欠陥の発生を防止することができる。 The same effect can be obtained by using an insulating resin containing conductive fine particles instead of the mounting insulating resin 20, that is, an anisotropic conductive resin.
In the present embodiment, since the connection bump 40 is used instead of the connection wire for the electrical tangent of the conductive pattern on the insulating chip and the electrode on the semiconductor chip 30, when sealing with the transfer mold resin 50. In addition, it is possible to prevent the occurrence of fatal defects such as deformation of the connection wire, electrical short circuit, and electrical release.

また、接続バンプ４０は半導体チップ３０の直下に設けられるため、接続ワイヤのように半導体チップ以外の特別な領域を必要とせず、個々の半導体装置７０のサイズを小さくすることか可能となり、また半導体装置の取れ数を増大させることも可能となる。   Further, since the connection bumps 40 are provided directly below the semiconductor chip 30, it is possible to reduce the size of each semiconductor device 70 without requiring a special region other than the semiconductor chip like the connection wires. It is also possible to increase the number of devices to be taken.

実施の形態２．
本発明の第２の実施の形態を、図２を参照して説明する。
先ず、図２（ａ）に示すように、絶縁基板１０を用意する。
次に、図２（ｂ）に示すように、絶縁基板１０上に取付用絶縁樹脂２１を用いて半導体チップ３０を搭載する。この際、この図１（ｂ）のように取付用絶縁樹脂２０を個別の半導体チップ３０毎に設けるのではなく、1個の絶縁基板１０に対して１個の取付用絶縁樹脂２１を用いて、複数個の半導体チップ３０を搭載する。この取付用絶縁樹脂２１は、薄い平板状で一体のものである。
この後、図２（ｃ）に示す封止工程、図２（ｄ）に示すボール形成工程を同様に経る。 次に、図２（ｅ）に示すように、最終工程において、トランスファーモールド樹脂５０、取付用絶縁樹脂２１、絶縁基板１０を同時に寸断して個々の半導体装置７１を得る。 Embodiment 2. FIG.
A second embodiment of the present invention will be described with reference to FIG.
First, as shown in FIG. 2A, an insulating substrate 10 is prepared.
Next, as shown in FIG. 2B, the semiconductor chip 30 is mounted on the insulating substrate 10 using the mounting insulating resin 21. At this time, the mounting insulating resin 20 is not provided for each individual semiconductor chip 30 as shown in FIG. 1B, but one mounting insulating resin 21 is used for one insulating substrate 10. A plurality of semiconductor chips 30 are mounted. The mounting insulating resin 21 is a thin flat plate and is integral.
Thereafter, the sealing process shown in FIG. 2C and the ball formation process shown in FIG. Next, as shown in FIG. 2E, in the final step, the transfer mold resin 50, the mounting insulating resin 21, and the insulating substrate 10 are simultaneously cut to obtain individual semiconductor devices 71.

この実施の形態によれば、フリップチップ接続した一括封止タイプで半導体装置の製造ができ、モールド時のワイヤ変形不良を防止できること、パッケージサイズを小さくできること、また、パッケージの取れ数を増大させることなどの効果がある。
また、1個の絶縁基板１０に対して１個の薄い板状の取付用絶縁樹脂２１を用いて、複数の半導体チップ３０を取りつけるようにしたので、生産性を向上させる効果もある。 According to this embodiment, a semiconductor device can be manufactured by a flip-chip connected batch sealing type, wire deformation failure during molding can be prevented, the package size can be reduced, and the number of packages to be taken can be increased. There are effects such as.
Further, since a plurality of semiconductor chips 30 are attached to one insulating substrate 10 using one thin plate-like mounting insulating resin 21, there is an effect of improving productivity.

実施の形態３．
本発明の第３の実施の形態を、図３を参照して説明する。
先ず、図３（ａ）に示すように、絶縁基板１０を用意する。
次に、図３（ｂ）に示すように、絶縁基板１０上に１個の絶縁基板１０に対して１個の取付用絶縁樹脂２１を用いて、個別の半導体チップではなく一体となった複数の半導体チップ群３１を複数個搭載する。この半導体チップ群３１は、個々の半導体チップを所定数含むもので、ウェーハからは大きな単位で分割したものである。 Embodiment 3 FIG.
A third embodiment of the present invention will be described with reference to FIG.
First, as shown in FIG. 3A, an insulating substrate 10 is prepared.
Next, as shown in FIG. 3B, a plurality of integrated insulating substrates 21 are used instead of individual semiconductor chips by using one insulating resin 21 for one insulating substrate 10 on the insulating substrate 10. A plurality of semiconductor chip groups 31 are mounted. The semiconductor chip group 31 includes a predetermined number of individual semiconductor chips, and is divided into large units from the wafer.

この後、図３（ｃ）に示す封止工程、図３（ｄ）に示すボール形成工程を同様に経る。
次に、図３（ｅ）に示すように、最終工程において、トランスファーモールド樹脂５０、一体となった複数の半導体チップ群３１、取付用絶縁樹脂２１、絶縁基板１０を同時に寸断して個々の半導体装置７２を得る。 Thereafter, the sealing process shown in FIG. 3C and the ball formation process shown in FIG.
Next, as shown in FIG. 3 (e), in the final process, the transfer mold resin 50, the plurality of integrated semiconductor chip groups 31, the mounting insulating resin 21, and the insulating substrate 10 are cut simultaneously to form individual semiconductors. Device 72 is obtained.

この実施の形態によれば、フリップチップ接続した一括封止タイプで半導体装置の製造ができ、モールド時のワイヤ変形不良を防止できること、パッケージサイズを小さくできること、また、パッケージの取れ数を増大させることなどの効果がある。
また、複数の所定個数の半導体チップを含み、１個１個のチップに分離されていない未分離のチップ（半導体チップ群）を絶縁基板１０に取りつけるので、生産性を向上させる効果もある。 According to this embodiment, a semiconductor device can be manufactured by a flip-chip connected batch sealing type, wire deformation failure during molding can be prevented, the package size can be reduced, and the number of packages to be taken can be increased. There are effects such as.
Further, since an unseparated chip (semiconductor chip group) that includes a plurality of predetermined number of semiconductor chips and is not separated into individual chips is attached to the insulating substrate 10, there is an effect of improving productivity.

実施の形態４．
本発明の第４の実施の形態を、図４を参照して説明する。
まず、図４（ａ）に示すように、絶縁基板１０を用意する。
次に、図４（ｂ）に示すように、絶縁基板１０上に１個の絶縁基板１０に対して１個の取付用絶縁樹脂２１を用いて、個別の半導体チップではなく一体の半導体ウェーハ３２自身を搭載する。 Embodiment 4 FIG.
A fourth embodiment of the present invention will be described with reference to FIG.
First, as shown in FIG. 4A, an insulating substrate 10 is prepared.
Next, as shown in FIG. 4B, an insulating semiconductor 21 for mounting is used instead of individual semiconductor chips by using one insulating resin 21 for one insulating substrate 10 on the insulating substrate 10. Mount yourself.

この後、図４（ｃ）に示す封止工程、図４（ｄ）に示すボール形成工程を同様に経る。
最後に、図４（ｄ）に示すように、最終工程において、トランスファーモールド樹脂５０、半導体ウェーハ３２、取付用絶縁樹脂２１、絶縁基板１０を同時に寸断して個々の半導体装置７３を得る。
この実施の形態によれば、半導体装置７０を半導体チップと完全に同じサイズにまで小さくすることが可能になり、さらに半導体装置７０の取れ数を増大させることも可能となる。 Thereafter, the sealing process shown in FIG. 4C and the ball formation process shown in FIG.
Finally, as shown in FIG. 4D, in the final process, the transfer mold resin 50, the semiconductor wafer 32, the mounting insulating resin 21, and the insulating substrate 10 are cut simultaneously to obtain individual semiconductor devices 73.
According to this embodiment, the semiconductor device 70 can be reduced to the same size as the semiconductor chip, and the number of semiconductor devices 70 can be increased.

この実施の形態によれば、フリップチップ接続した一括封止タイプで半導体装置の製造ができ、モールド時のワイヤ変形不良を防止できること、パッケージサイズを小さくできること、また、パッケージの取れ数を増大させることなどの効果がある。
また、半導体ウェーハから個々のチップを分離するまえに、半導体ウェーハのままで絶縁基板１０に取付けるので、生産性を向上させる効果もある。 According to this embodiment, a semiconductor device can be manufactured by a flip-chip connected batch sealing type, wire deformation failure during molding can be prevented, the package size can be reduced, and the number of packages to be taken can be increased. There are effects such as.
In addition, before the individual chips are separated from the semiconductor wafer, the semiconductor wafer is attached to the insulating substrate 10 as it is, which has the effect of improving productivity.

本発明の実施の形態１による半導体装置の製造方法を示す断面模式図。1 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態２による半導体装置の製造方法を示す断面模式図。Sectional schematic diagram which shows the manufacturing method of the semiconductor device by Embodiment 2 of this invention. 本発明の実施の形態３による半導体装置の製造方法を示す断面模式図。Sectional schematic diagram which shows the manufacturing method of the semiconductor device by Embodiment 3 of this invention. 本発明の実施の形態４による半導体装置の製造方法を示す断面模式図。Sectional schematic diagram which shows the manufacturing method of the semiconductor device by Embodiment 4 of this invention. 従来の半導体装置の製造方法を示す断面模式図。Sectional schematic diagram which shows the manufacturing method of the conventional semiconductor device.

符号の説明Explanation of symbols

１０ 絶縁基板、２０ 取付用絶縁樹脂、 ２１ １個の取付用絶縁樹脂、 ３０ 半導体チップ、 ３１ 半導体チップ群、 ３２ 半導体ウェーハ、 ４０ 接続バンプ、 ５０ トランスファーモールド樹脂、 ６０ 電極ボール、 ７０，７１，７２，７３ 半導体装置。 DESCRIPTION OF SYMBOLS 10 Insulation board | substrate, 20 Insulation resin for attachment, 21 One insulation resin for attachment, 30 Semiconductor chip, 31 Semiconductor chip group, 32 Semiconductor wafer, 40 Connection bump, 50 Transfer mold resin, 60 Electrode ball, 70, 71, 72 73 Semiconductor device.

Claims (3)

絶縁基板上に複数の半導体チップをバンプ接続する工程と、
上記複数の半導体チップが一つのトランスファーモールド樹脂に覆われるように、上記複数の半導体チップを上記絶縁基板上に封止する工程と、
上記絶縁基板上に樹脂封止された上記複数の半導体チップを個別の半導体装置に分離する工程と
を含み、
上記封止する工程の前に、上記絶縁基板と上記複数の半導体チップの間に設けられるように１個の板状の取付用絶縁樹脂を形成することを特徴とする半導体装置の製造方法。 A step of bump-connecting a plurality of semiconductor chips on an insulating substrate;
Sealing the plurality of semiconductor chips on the insulating substrate such that the plurality of semiconductor chips are covered with one transfer mold resin;
Separating the plurality of semiconductor chips resin-sealed on the insulating substrate into individual semiconductor devices,
Prior to the sealing step, a single plate-like mounting insulating resin is formed so as to be provided between the insulating substrate and the plurality of semiconductor chips. 上記複数の半導体チップを、所定個数の半導体チップを含む未完全分離のチップ群状態でそれぞれ上記絶縁基板に取付けることを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of semiconductor chips are each attached to the insulating substrate in an incompletely separated chip group state including a predetermined number of semiconductor chips. 上記複数の半導体チップを、未分離のウェーハ状態で上記絶縁基板に取付けることを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of semiconductor chips are attached to the insulating substrate in an unseparated wafer state.
JP2008109791A 2008-04-21 2008-04-21 Manufacturing method of semiconductor device Expired - Fee Related JP4780136B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101610375B1 (en) 2009-03-09 2016-04-07 엘지이노텍 주식회사 Wireless communication module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101610375B1 (en) 2009-03-09 2016-04-07 엘지이노텍 주식회사 Wireless communication module

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