JP2008176834A - Recording and reproducing device and recording and reproducing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate stably a recording clock and a reproducing clock without increasing circuit scale and power consumption. <P>SOLUTION: The device has a wobble signal detecting means detecting a wobble signal formed in a disk type recording medium, a first clock generating means generating a first clock having a frequency relating to a wobble period based on the wobble signal detected by the wobble signal detecting means, and a second clock generating means generating a channel clock having a frequency relating to a channel period making a frequency component in which predetermined processing is performed for a control signal when the first clock generating means generates the first clock, wherein a voltage control oscillator incorporated in the first clock generating means and a voltage control oscillator incorporated in the second clock generating means have the same composition. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a recording / reproducing apparatus and a recording / reproducing method, and particularly to a technique suitable for use in recording / reproducing digital data on / from a disk-shaped recording medium.

  2. Description of the Related Art Conventionally, an apparatus for recording / reproducing digital data on an optical disk such as a DVD is known (for example, see Patent Document 1). In a DVD, spiral laser beam guide grooves (grooves) are formed from the center of the disk toward the outer periphery, and data is recorded therein. The guide groove is slightly wobbled with a predetermined amplitude and a single period in the radial direction.

Here, FIG. 2 shows a block configuration diagram when the recording clock and the reproduction clock are generated.
First, recording clock generation will be described. The optical pickup unit 202 reads the wobble formed on the optical disc 201. Then, the wobble read by the optical pickup unit 202 is output to the wobble detection unit 203, and the wobble detection unit 203 detects the wobble signal. That is, in the recording / reproducing apparatus of this embodiment, the optical pickup unit 202 and the wobble detection unit 203 function as a wobble signal detection unit.

  The wobble signal detected by the wobble detection unit 203 is output to the comparator unit 204. The comparator unit 204 compares the wobble signal with a predetermined slice level, and detects the zero cross point of the wobble signal.

  The zero cross point detected by the comparator unit 204 is output to the phase detection unit 205. The phase detection unit 205 compares the timing of the zero cross point of the input wobble signal with the phase difference of the output signal output from the frequency divider 208, and outputs a phase error signal corresponding to the phase difference.

  The phase error signal output from the phase detection unit 205 is supplied to the VCO unit 207 via the loop filter unit 206, and controls the VCO unit 207 to generate a phase-locked clock. The output of the VCO unit 207 is input to the phase detection unit 205 via the frequency divider 208. For data recording, a clock generated from the VCO unit 207 is used.

  Next, reproduction clock generation will be described. Digital data recorded on the optical disc 201 is read by the optical pickup unit 202. Then, the read digital data is supplied to the reproduction signal detection unit 209. A reproduction signal detector 209 detects a reproduction signal from the input digital data.

  The reproduction signal detected by the reproduction signal detection unit 209 is given to the comparator unit 210. The comparator unit 210 compares the input reproduction signal with a predetermined slice level, detects a zero cross point of the reproduction signal, and outputs this to the phase detection unit 211.

  The phase detection unit 211 compares the phase difference between the input zero-cross point timing and the output signal supplied from the frequency divider 214, and outputs a phase error signal corresponding to the phase difference. The phase error signal output from the phase detection unit 211 is supplied to the VCO unit 213 via the loop filter unit 212, and controls the VCO unit 213 to generate a phase-locked clock. The output of the VCO unit 213 is input to the phase detection unit 211 via the frequency divider 214. A clock generated from the VCO unit 213 is used for the reproduction process.

JP 2002-32962 A

However, in the conventional configuration, since it is necessary to provide two analog VCO units in order to obtain a recording clock synchronized with rotation and a reproduction clock synchronized with reproduction data, the circuit scale and power consumption increase. was there. In addition, there is a problem that the manufacturing cost increases with an increase in circuit scale.
The present invention has been made in view of the above-described problems, and it is an object of the present invention to stably generate a recording clock and a reproduction clock without increasing the circuit scale and power consumption.

The recording / reproducing apparatus of the present invention has a wobble signal detecting means for detecting a wobble signal formed on a disc-shaped recording medium, and a frequency related to the wobble period based on the wobble signal detected by the wobble signal detecting means. A first clock generating means for generating a first clock; and a frequency component obtained by performing a preset process on a control signal when the first clock generating means generates the first clock. And a second clock generating means for generating a channel clock having a frequency related to a channel period, and a voltage controlled oscillator incorporated in the first clock generating means, and a voltage incorporated in the second clock generating means The controlled oscillator has the same configuration.
Another feature of the recording / reproducing apparatus of the present invention is that a wobble signal detecting means for detecting a wobble signal formed on a disk-shaped recording medium and a reference phase signal formed on the disk-shaped recording medium are detected. Using the reference phase signal detection means, the reproduction signal detection means for reading the data recorded on the disc-shaped recording medium and detecting the reproduction signal, and the wobble signal detected by the wobble signal detection means, First clock generating means for generating a clock having an associated frequency, address information detecting means for detecting address information based on the clock generated by the first clock generating means, and the first clock generating Filter means for applying a gain process to the control signal of the means to remove noise components, and the filter means A second clock generation means for generating a clock having a frequency related to the channel period, and a reference detected by the reference phase signal detection means. A time difference detecting means for detecting a time difference between the phase signal and the recording clock generated by the second clock generating means; and a frequency shift between the reference phase signal and the recording clock from the time difference detected by the time difference detecting means. Offset calculating means for calculating as an offset value, offset adding means for adding the offset value calculated by the offset calculating means to the control signal of the second clock generating means, and the reproduction signal detected by the reproduction signal detecting means Equalizing means for smoothing the output data equalized by the equalizing means Smoothing means, addition means for adding the output signal of the smoothing means and the gain processing result of the gain processing performed by the filter means, and the addition result of the addition means is controlled by the second clock generation means And a third clock generating means for generating a recovered clock having a frequency related to the channel period, and a switching means for switching a clock generated by the second clock generating means in accordance with a switching signal given from the outside. It is characterized by.

The recording / reproducing method of the present invention has a wobble signal detection step for detecting a wobble signal formed on a disc-shaped recording medium, and a frequency related to the wobble cycle based on the wobble signal detected in the wobble signal detection step. A first clock generating step for generating a first clock, and a frequency component obtained by performing a preset process on the control signal for generating the first clock in the first clock generating step. And a second clock generation step of generating a channel clock having a frequency related to the channel period, and a voltage controlled oscillator used in the first clock generation step, and used in the second clock generation step The voltage controlled oscillator to be configured has the same configuration.
Another feature of the recording / reproducing method of the present invention is that a wobble signal detecting step for detecting a wobble signal formed on a disk-shaped recording medium and a reference phase signal formed on the disk-shaped recording medium are detected. Using the wobble signal detected in the wobble signal detection step, and the wobble signal detected in the wobble signal detection step. A first clock generation step for generating a clock having an associated frequency; an address information detection step for detecting address information based on the clock generated in the first clock generation step; and the first clock generation. A filter process for removing a noise component by applying a gain process to a process control signal; A second clock generation step of generating a clock having a frequency related to the channel period using the frequency component from which the noise component has been removed by the gain processing as a control signal, and the reference detected in the reference phase signal detection step A time difference detection step for detecting a time difference between the phase signal and the recording clock generated in the second clock generation step; and a frequency shift between the reference phase signal and the recording clock from the time difference detected in the time difference detection step. An offset calculation step for calculating as an offset value, an offset addition step for adding the offset value calculated in the offset calculation step to a control signal in the second clock generation step, and a reproduction signal detected in the reproduction signal detection step Equalization process and output equalized in the equalization process A smoothing step for smoothing the data, an adding step for adding the output signal output from the smoothing step and the gain processing result of the gain processing performed in the filtering step, and the addition result in the adding step As a control signal for the second clock generation step, a third clock generation step for generating a recovered clock having a frequency related to the channel period and a second clock generation step according to a switching signal given from the outside. And a switching step of switching clocks.

  According to the present invention, by switching the type of clock generated by the clock generation means by the switching signal, the circuit scale and power consumption can be increased by synchronizing with the rotation of the disk with high accuracy and by using a stable recording clock and reproducing clock. Can be generated without.

(First embodiment)

Next, an embodiment of the present invention will be described in detail with reference to FIG.
For example, the wobble signal is generated by the wobble signal detecting means that includes the optical pickup unit and the wobble detection unit described above and detects the wobble signal formed on the disc-shaped recording medium. This wobble signal is supplied to the input terminal 101 and used as a wobble signal for tracking control. The input terminal 124 is supplied with a reproduction signal of data recorded on the disk-shaped recording medium. The reproduction signal of this data is detected by reading the data recorded on the above-described disc-shaped recording medium by, for example, reproduction signal detection means configured by the optical pickup unit 202 and the reproduction signal detection unit 209 described with reference to FIG. It has been done.

  In addition, the first mode switching signal A is input to the input input terminal 129 from the outside. In accordance with the first mode switching signal A given from the outside, control is performed so as to connect to the input terminal 130 in the case of recording processing. In the case of reproduction processing, control is performed so as to connect to the input terminal 131. Further, when neither of them, that is, when address detection is performed by inserting a disk, switching control is performed so as to connect to the input terminal 134. Here, the DVD-R disc double speed is taken as an example, the clock frequency of the wobble signal is 281.29 KHz, and the frequency of recording / playback data is 52.32 MHz.

Next, recording clock generation will be described.
The phase comparison unit 103 multiplies the wobble signal converted into a digital signal by the AD conversion unit 102 and the output signal of the wobble DVCO unit (digital voltage controlled oscillator) 105 to extract the low frequency, and the phase comparison unit 103 (phase comparison) Phase comparison. Then, the phase error result output from the phase comparison unit 103 is input to the loop filter unit 104, and the wobble DVCO unit 105 is controlled via the loop filter unit 104 so as to generate a phase-locked clock.

  The address detector 122 functioning as address information detection means detects address information at a prescribed phase timing. In the recording clock generation, the integrator output of the loop filter unit 104 of the wobble PLL unit 107 is supplied to the amplifier 108 and multiplied by a gain. Next, a channel clock having a frequency related to the channel period is output from the analog PLL unit 114 by passing through a low-pass filter unit (LPF unit) 109 that removes noise components and adding it as a frequency error value to the channel DVCO unit 112. To do. Here, the integrator output of the loop filter unit 104 is used for the purpose of further stabilizing the noise component, but there is no problem in operation even if the output value of the loop filter unit 104 is connected.

Next, correction of the recording clock timing will be described.
The digital signal output from the AD conversion unit 102 is supplied to the reference phase signal detection unit 115. The reference phase signal detection unit 115 detects the reference phase signal and operates the counter unit 116 in accordance with the detection timing.

  The reference phase signal is recorded in advance as a preformat on the disk-shaped recording medium. For example, in the case of DVD-R and DVD-RW discs, a land pre-pit detection circuit for detecting a land pre-pit of a reference phase signal, and in the case of DVD + R and DVD + RW discs, an ADIP detection circuit for detecting ADIP of a reference phase signal is used as a reference. Detect a phase signal.

  Based on the count value of the counter unit 116 operating with the channel clock output from the analog PLL unit 114, the modulator 117 modulates the channel data and sends the recording data to a laser control unit (not shown) via the terminal 118. Output.

  Next, reproduction clock generation will be described. The AD conversion unit 125 converts the reproduction signal into a digital signal at the timing of the channel clock output from the analog PLL unit 114 and outputs the digital signal to the equalizer 126.

  The equalizer 126 has a frequency characteristic that raises a predetermined high-frequency component, and is composed of, for example, a 7-tap FIR filter. A phase comparison unit 127 described later functions as a phase difference detection unit that detects a phase difference between the digital data output from the equalizer 126 and the reproduction clock output from the analog PLL unit 114. Then, a phase error signal is output to the loop filter unit 128 based on the phase difference detection result by the phase difference detection means. The phase difference detection means has a function (conversion means) for converting a phase difference between a wobble clock and a clock having a frequency related to the wobble cycle (first clock) into a frequency error. Also, it has a function of converting the phase difference between the recording clock and the clock having the frequency related to the channel period (second clock) and the phase difference between the reproduction clock and the first clock into frequency errors. .

  The amplifier 108 performs gain processing on the integrator output of the loop filter unit 104 of the wobble PLL unit 107. The regenerated clock is generated by adding the output from the loop filter unit 128 and the value obtained from the gain processing result when connected to the input terminal 131 in accordance with the first mode changeover switch signal A given to the input terminal 129. Add at 133.

  The addition result of the adder 133 is added as a frequency error value of the channel DVCO unit 112, thereby outputting a reproduction clock (channel clock) from the analog PLL unit 114. The gain processing value is configured to hold the value when switching to the reproduction processing. Here, the integrator output of the loop filter unit 104 is used for the purpose of further stabilizing the noise component, but there is no problem in operation even if the output value of the loop filter unit 104 is connected.

  Next, the operation of the phase comparison unit 127 will be described with reference to FIG. The phase comparison unit 127 includes a partial response (PR (1, 1) processing circuit) 702, a pattern detection circuit 703, an inclination correction circuit 704, and the like. The equalized digital data input from the terminal 701 is subjected to PR (1,1) calculation in the partial response PR (1,1) processing circuit 702.

  The pattern detection circuit 703 performs binary determination on the calculation result, and detects a specific pattern corresponding to a zero cross point having an inclination proportional to the phase difference from the obtained data string. The inclination correction circuit 704 determines the inclination of the digital data input from the detection result of the pattern detection circuit 703, corrects the inclination to be constant according to the determination result, and outputs a phase error signal.

Next, an operation when the first mode changeover switch signal A is given to the input terminal 129 will be described.
FIG. 6 shows a timing chart at the time of switching the first mode switch signal A given to the input terminal 129. 6A shows a channel clock, and FIG. 6B shows a switching signal of the first mode changeover switch signal A given to the input terminal 129 when switching to reproduction processing.

  As shown in FIG. 6B, the first mode changeover switch signal A changes to “0” during recording and “1” during reproduction. When switching to the reproduction process, the first mode changeover switch signal A in (b) changes from “0” to “1” in synchronization with the timing of the channel clock in (a).

  FIG. 6C shows an integrator output of the loop filter unit 104 of the wobble PLL unit 107, and gain processing is performed from the ratio of the center frequency setting values of the wobble DVCO unit 105 and the channel DVCO unit 112 to the value of (c). To obtain a gain processing value (d). For example, when a DVD-R disc is taken as an example, the ratio of the center frequency setting values is 23.25 times.

  Since the first mode changeover switch signal A given to the input terminal 129 is configured to hold the gain processing value (d) at the time of switching to the reproduction processing, the value inputted to the adder 133 is (f) It becomes. The output value (e) of the loop filter unit 128 of the reproduction system is added to the addition value (f) in the adder 133, and the addition result (g) is added as the frequency error value of the channel DVCO unit 112, whereby an analog PLL is obtained. A reproduction clock is generated from the unit 114.

  Next, the operations of the wobble DVCO unit 105 and the channel DVCO unit 112 will be described with reference to FIGS. The wobble DVCO unit 105, the channel DVCO unit 112, and the subsequent ΔΣDA conversion unit 113 operate with an 81 MHz clock supplied from a crystal oscillator.

  FIG. 3A is a diagram illustrating a specific configuration of the wobble DVCO unit 105. In FIG. 3A, the terminal 301 is supplied with a set value corresponding to the target frequency of the clock. Here, the DVD-R disc double speed is taken as an example of the optical disc, the target clock frequency is 281.290 KHz, and 3640 is set. In this case, “3640 × 81e6 ÷ 2 ^ 20 = 281118 Hz”.

  The value of the center frequency from the terminal 301 and the frequency error value from the input terminal 302 are added by the adder 303. The addition result of the adder 303 is further added to the adder 304. A 20-bit value held in the register 305 is added to the other terminal of the adder 304, and the addition result is added to the register 305 again.

  Although the addition result of the register 305 may overflow, it is ignored here without carrying it. The upper 7 bits of the register 305 are input to the sign table unit 306. The sign table unit 306 expresses “a phase of 0 ° to 360 °” with, for example, a 7-bit value “value of 0 to 127”. That is, “input value 1” represents “360 ° ÷ 128 = 2.8 °”. The sine table unit 306 outputs an 8-bit sine wave value (frequency value of a sine wave signal) corresponding to the input phase to the terminal 307. These circuit configurations function as sine wave signal generation means.

  The state of bit allocation is shown in FIG. A to D in FIG. 3B correspond to the respective signals in FIG. For example, when the frequency error given to the input terminal 302 is “0” and the center frequency given to the terminal 301 is “3640”, A in the figure is “3640”.

  Since the register 305 has 20 bits and the clock has a frequency of 81 MHz oscillated from the crystal oscillator, the register 305 overflows with a period of “81e6 × 3640/2 ^ 20 = 281118 Hz”. However, in this embodiment, the upper 7 bits of this register 305 are taken out without carrying and the result is output to the sign table unit 306.

  Further, if “1” is given to the input terminal 302, A in FIG. 3 becomes “3641”, so that the clock frequency becomes “81e6 × 3641/2 ^ 20 = 281258 Hz”, and the input changes by “1”. The clock frequency changes by “77 Hz”.

FIG. 4A is a diagram illustrating a specific configuration example of the channel DVCO unit 112.
In FIG. 4A, a setting value corresponding to the target frequency of the clock is supplied to the terminal 401. Here, the DVD-R disc double speed is taken as an example of the optical disc, and the target clock frequency is multiplied by 8 to “6.54 MHz” to be 52.32 MHz, and “84630” is set. That is, “84630 × 81e6 ÷ 2 ^ 20 = 65353766 Hz”.

  The adder 403 adds the value of the center frequency input from the terminal 401 and the frequency error value input from the input terminal 402. The addition result of the adder 403 is further added to the adder 404. An addition wiring is connected to the other terminal of the adder 404, and a 20-bit value held in the register 405 is added through this addition wiring. Then, the integrator configuration is such that the addition result is added to the register 405 again.

  Although the addition result of the register 405 may overflow, it is ignored here without carrying. The upper 7 bits of the register 405 are added to the sign table unit 406. The sign table unit 406 expresses a phase of “0 ° to 360 °” with, for example, a 7-bit value “0 to 127”. That is, “input value 1” represents “360 ° ÷ 128 = 2.8 °”. The sine table unit 406 outputs an 8-bit sine wave value (frequency value of a sine wave signal) corresponding to the input phase to a terminal 407. These circuit configurations function as sine wave signal generation means. In the present embodiment, it functions as an adding means for adding the set value related to the target frequency of the sine wave signal and the frequency error converted by the converting means, and the added value of the adding means is set to a predetermined cycle. It has a function to perform integration operation.

  FIG. 4B shows the state of bit allocation. A to D in FIG. 4B correspond to the signals in FIG. For example, if the frequency error given to the input terminal 402 is “0” and the center frequency given to the terminal 401 is “84630”, A in FIG. 4 is “84630”.

  Since the register 405 has 20 bits and the clock has a frequency of 81 MHz oscillated from a crystal oscillator, the register 405 overflows with a period of “81e6 × 84630/2 ^ 20 = 6537466 Hz”. However, in this embodiment, the upper 7 bits of the register 405 are extracted without carrying, and the result is input to the sine table unit 406 to generate a sine wave.

  The ΔΣDA conversion unit 113 converts the sine wave output result into an analog voltage and outputs the analog voltage to the analog PLL unit 114. The analog PLL unit 114 includes a phase comparator, a loop filter unit, a VCO unit, and a frequency divider (all not shown), and is a known PLL unit for clock multiplication.

  For example, by multiplying, for example, a 6.54 MHz sine wave output from the ΔΣ DA conversion unit 113, a clock of “52.32 MHz” is generated and used as a recording clock signal. In the present embodiment, the frequency division ratio of the frequency divider is 1/8, but other values may be taken. For example, in the case of DVD-R disc quadruple speed, the division ratio may be 1/16. Further, although the oscillation frequency of the crystal oscillator is set to “81 MHz”, other values can be taken.

Here, the center frequency setting value of the wobble DVCO unit 105 and the channel DVCO unit 112 and the setting value of the amplifier 108 will be described.
For example, taking DVD-R disc double speed as an example, the center frequency setting value of the wobble DVCO unit 105 input to the input terminal 106 is “3640”, and the center of the channel DVCO unit 112 input from the input terminal 111. “84630” was set as the frequency setting value.

  Therefore, the center frequency setting value of the wobble DVCO unit 105 and the center frequency setting value of the channel DVCO unit 112 have a relationship of “23.25 times”. Therefore, “23.25” is set in the amplifier 108. In this case, “3640 × 23.25 = 84630”.

  In this embodiment, the wobble DVCO unit 105 and the channel DVCO unit 112 have the same configuration. Therefore, the frequency error value of the wobble DVCO unit 105 (frequency error value input to the input terminal 302 in FIG. 3) and the frequency error value of the channel DVCO unit 112 (frequency error value applied to the input terminal 402 of FIG. 4). There is a 23.25 times relationship. For example, if the integrator output value of the loop filter unit 104 of the wobble PLL unit 107 is “12” during recording, the control signal of the channel DVCO unit 112 is “12 × 23.25 + 84630 = 84909”. Accordingly, “81e6 × 84909 ÷ 2 ^ 20 × 8 = 524472145 Hz” is a channel clock having a frequency component related to the channel period.

  For example, assume that the output value of the loop filter unit 128 is “16” and the integrator output value of the loop filter unit 104 of the wobble PLL unit 107 is “12” during reproduction. In this case, since the control signal of the channel DVCO unit 112 is “16 + 12 × 23.25 + 84630 = 84925”, “81e6 × 84925 ÷ 2 ^ 20 × 8 = 52482022 Hz” is the reproduction clock frequency.

Next, the operation of the time difference detection unit 119 will be described with reference to FIG.
The time difference detection unit 119 receives the reference signal detection flag from the reference phase signal detection unit 115 and the channel clock timing from the analog PLL unit 114. The reference signal detection flag is “1” when the reference signal is detected, and is “0” when the reference signal is not detected. The reference signal detection flag is output to the offset calculation unit 120 as the signal s.

  When the channel clock and the reference phase signal are synchronized, the counter value 0 and the timing of the reference phase signal detection flag match as shown in FIG. FIG. 5B shows a case where the reference phase signal detection flag is earlier by 3 channel clocks, and FIG. 5C shows a case where the reference phase signal detection flag is later by 3 channel clocks.

  The number of clocks between the channel clock and the reference phase signal is output to the offset calculation unit 120 as a signal t. For example, when the reference phase signal detection flag is delayed by 3 channel clocks as shown in FIG. 5C, “3” is output to the offset calculation unit 120 as the signal t.

  The offset calculation unit 120 is supplied from the time difference detection unit 119 as a “signal t” with a time shift amount of the reference phase signal detection flag signal s, the reference phase signal, and the channel clock. For example, when signals s = “1” and t = “3” are input, the channel clock must be delayed by 3 channel clocks. That is, in the case of normal synchronization, 1488 clocks per frame are counted for 1491 clocks per frame. For this reason, an offset corresponding to three channel clocks is added to the control signal of the channel DVCO unit 112 to operate in synchronization with the reference phase signal. For example, if the control signal (= center frequency setting value + frequency error value) of the channel DVCO unit 112 is 84630, “84630 × (3/1488) = 170”. As a result, it is possible to generate a frequency component subjected to a preset process.

  Therefore, by adding “−170 offset” to the control signal of the channel DVCO unit 112, the reference phase signal and the channel clock can be synchronized. Further, when the reference phase signal detection flag s = “0” is input from the time difference detection unit 119, the offset calculation unit 120 is configured to hold the value. The second mode switching signal B input to the offset calculation unit 120 via the input terminal 121 has a configuration in which the gain value can be switched so that the offset addition amount can be changed.

  As described above, in the recording / reproducing apparatus of the present embodiment, the DVCO unit having the same configuration is incorporated in the wobble PLL and the channel PLL. As a result, it is possible to configure a circuit by providing only one analog VCO unit without providing two analog VCO units, thereby preventing an increase in circuit scale and power consumption. Furthermore, the cost can be kept low.

  At the time of recording, a signal obtained by extracting a low frequency component from a signal obtained by gain processing of the wobble DVCO unit control signal is used as a control signal for the channel DVCO unit 112. Further, the time lag between the reference phase signal and the channel clock is calculated and added to the control signal of the channel DVCO unit 112 as an offset amount. In this way, it is possible to generate a high-precision recording clock signal having a frequency related to the channel period that is accurately synchronized with the rotation of the disk.

  At the time of reproduction, a signal obtained by smoothing the phase error signal of the reproduction data by a loop filter and a signal obtained by gain processing of the wobble DVCO unit control signal are added, and the addition result is used as a control signal for the channel DVCO unit 112. This makes it possible to virtually increase the lock range of the reproduction PLL and generate a stable reproduction clock signal.

(Other embodiments according to the present invention)
Each means constituting the recording / reproducing apparatus and each step of the recording / reproducing method in the embodiment of the present invention described above can be realized by operating a program stored in a RAM or ROM of a computer. This program and a computer-readable storage medium storing the program are included in the present invention.

  Further, the present invention can be embodied as a system, apparatus, method, program, storage medium, or the like. Specifically, the present invention may be applied to a system composed of a plurality of devices, or may be applied to an apparatus composed of a single device.

It is a block diagram which shows the structural example of the recording / reproducing apparatus in this embodiment. It is a block diagram which shows the structural example of the conventional recording / reproducing apparatus. It is a figure explaining the wobble DVCO part in this embodiment, and its operation example. It is a figure explaining the channel DVCO part in this embodiment, and its operation example. It is a figure which shows operation | movement of the time difference detection circuit in this embodiment. It is a figure explaining the timing at the time of switching to the reproduction | regeneration processing in this embodiment. It is a block diagram explaining the structure and operation | movement of a phase comparison part in this embodiment.

Explanation of symbols

101 terminal 102 AD conversion unit 103 phase comparison unit 104 loop filter unit 105 wobble DVCO unit 106 input terminal 107 wobble PLL unit 108 amplifier 109 low pass filter unit 110 adder 111 input terminal 112 channel DVCO unit 113 ΔΣ DA conversion unit 114 analog PLL unit 115 Reference phase signal detection unit 116 Counter unit 117 Modulator 118 Terminal 119 Time difference detection unit 120 Offset calculation unit 121 Input terminal 122 Address detection unit

Claims (8)

Wobble signal detection means for detecting a wobble signal formed on a disk-shaped recording medium;
First clock generation means for generating a first clock having a frequency related to a wobble period based on the wobble signal detected by the wobble signal detection means;
The first clock generation means generates a channel clock having a frequency related to a channel period using a frequency component obtained by performing a preset process on the control signal when the first clock is generated as a control signal. Second clock generation means,
A recording / reproducing apparatus having the same configuration as the voltage controlled oscillator incorporated in the first clock generating means and the voltage controlled oscillator incorporated in the second clock generating means. Wobble signal detection means for detecting a wobble signal formed on a disk-shaped recording medium;
A reference phase signal detecting means for detecting a reference phase signal formed on the disc-shaped recording medium;
Reproduction signal detection means for detecting reproduction signals by reading data recorded on the disc-shaped recording medium;
First clock generation means for generating a clock having a frequency related to a wobble period using the wobble signal detected by the wobble signal detection means;
Address information detecting means for detecting address information based on the clock generated by the first clock generating means;
Filter means for applying a gain process to the control signal of the first clock generation means to remove a noise component;
A second clock generation means for generating a clock having a frequency related to a channel period, using the frequency component from which the noise component has been removed by the filter means as a control signal;
A time difference detection means for detecting a time difference between the reference phase signal detected by the reference phase signal detection means and the recording clock generated by the second clock generation means;
Offset calculating means for calculating a frequency shift between the reference phase signal and the recording clock as an offset value from the time difference detected by the time difference detecting means;
An offset adding means for adding an offset value calculated by the offset calculating means to a control signal of the second clock generating means;
Equalization means for equalizing the reproduction signal detected by the reproduction signal detection means;
Smoothing means for smoothing the output data equalized by the equalization means;
Adding means for adding the output signal of the smoothing means and the gain processing result of the gain processing performed by the filter means;
Third clock generation means for generating a reproduction clock having a frequency related to a channel period, using the addition result of the addition means as a control signal for the second clock generation means;
A recording / reproducing apparatus comprising: a switching unit that switches a clock generated by the second clock generation unit in accordance with a switching signal given from outside. The first clock generation unit and the second clock generation unit detect a phase difference between the first clock and the wobble clock, the second clock and the recording clock, or the second clock and the reproduction clock. Phase difference detecting means for
A sine wave signal generating means for generating a sine wave signal based on the phase difference detection result output from the phase difference detecting means;
The recording / reproducing apparatus according to claim 2, further comprising a control unit that controls the clock generation unit based on a frequency value of the sine wave output from the sine wave signal generation unit. The phase difference detection means uses the phase difference between the wobble clock and the first clock, the phase difference between the recording clock and the second clock, and the phase difference between the reproduction clock and the second clock as frequency errors. Having conversion means for converting,
The sine wave signal generation means includes an addition means for adding a set value related to a target frequency of the sine wave signal and a frequency error converted by the conversion means, and a predetermined period for the addition value of the addition means. The recording / reproducing apparatus according to claim 2, further comprising an accumulating unit for accumulating at a time. The second clock generation means includes a phase comparator, a loop filter that inputs a phase error result output from the phase comparator, an oscillator that outputs a signal having a frequency corresponding to the output of the loop filter as a clock, A PLL circuit including a frequency divider that divides the clock output from the oscillator;
3. The recording / reproducing apparatus according to claim 2, wherein the sine wave signal output from the sine wave signal generation means and the output signal of the frequency divider are input to the phase comparator.   The first clock generation unit and the second clock generation unit include a crystal oscillator that generates a predetermined operation clock frequency, and the integration unit performs the integration operation according to an operation clock output from the crystal oscillator. The recording / reproducing apparatus according to claim 2, wherein: A wobble signal detection step for detecting a wobble signal formed on a disk-shaped recording medium;
A first clock generation step of generating a first clock having a frequency related to a wobble period based on the wobble signal detected in the wobble signal detection step;
In the first clock generation step, a frequency component obtained by performing a preset process on the control signal when generating the first clock is used as a control signal, and a channel clock having a frequency related to the channel period is generated. A second clock generation step,
A recording / reproducing method, wherein the voltage controlled oscillator used in the first clock generating step and the voltage controlled oscillator used in the second clock generating step have the same configuration. A wobble signal detection step for detecting a wobble signal formed on a disk-shaped recording medium;
A reference phase signal detection step of detecting a reference phase signal formed on the disc-shaped recording medium;
A reproduction signal detecting step of reading data recorded on the disc-shaped recording medium and detecting a reproduction signal;
A first clock generation step of generating a clock having a frequency related to a wobble period using the wobble signal detected in the wobble signal detection step;
An address information detection step of detecting address information based on the clock generated in the first clock generation step;
A filter step of removing a noise component by applying a gain process to the control signal of the first clock generation step;
A second clock generation step of generating a clock having a frequency related to a channel period, using the frequency component from which the noise component has been removed in the filtering step as a control signal;
A time difference detection step of detecting a time difference between the reference phase signal detected in the reference phase signal detection step and the recording clock generated in the second clock generation step;
An offset calculation step of calculating a frequency shift between the reference phase signal and the recording clock as an offset value from the time difference detected in the time difference detection step;
An offset addition step of adding the offset value calculated in the offset calculation step to the control signal of the second clock generation step;
An equalization step for equalizing the reproduction signal detected in the reproduction signal detection step;
A smoothing step of smoothing the output data equalized in the equalization step;
An adding step of adding the output signal output from the smoothing step and the gain processing result of the gain processing performed in the filtering step;
A third clock generation step of generating a reproduction clock having a frequency related to a channel period, using the addition result in the addition step as a control signal of the second clock generation step;
And a switching step of switching a clock generated in the second clock generation step in accordance with a switching signal given from the outside.

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