JP2009158035A - Optical disk recording/playback device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical disk recording/playback device having sufficient detection performance while suppressing an increase in circuit size or power consumption. <P>SOLUTION: This device includes a wobble PLL circuit for generating carriers, a delta-sigma modulator for performing delta-sigma modulation of a wobbling signal, a bandpass filter for passing the output of the delta-sigma modulator through a filter including a passage area of a frequency corresponding to the wobbling signal or a frequency corresponding to the modulated component of the wobbling signal, a calculator for performing calculation for the output of the bandpass filter and a carrier signal, a low pass filter for passing only a low band component from the output of the calculator, and an address playback information circuit for playing back address information from the output of the low pass filter. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an optical disc recording / reproducing apparatus for recording or reproducing information on an optical disc, and more particularly to a signal processing circuit for reproducing wobbling information and the like of an optical disc.

  Conventionally, when recording / reproducing data from / on an optical disk, in order to know the position on the disk, the address information embedded in the disk is detected in advance, the desired track position on the disk is accessed, and the position is Record and play back user data. In many optical disks, the groove information on the disk is shifted slightly in the width direction of the groove, and so-called wobbling is performed to embed address information and clock information.

  In the case of the optical disk as described above, the wobbling structure is usually sinusoidal and the wobble signal to be reproduced is substantially sinusoidal. Then, a part thereof is modulated by FSK / PSK / MSK / STW or the like, or in parallel with groove wobbling, prepits are provided in lands between grooves to embed address information.

  When reproducing the address of such an optical disk, some carrier signal synchronized with the wobble signal reproduced by the signal generator is generated. Then, the detection timing of address information such as PSK modulation components and prepits arranged only in a part of the wobble is detected, and the bit value which is address information is detected based on the timing.

  Further, in order to perform the speed control that makes the linear velocity constant, the spindle control is performed based on the carrier signal so that the sine wave frequency of the wobble signal becomes constant.

  For this reason, in order to generate a carrier signal synchronized with the wobble signal, a PLL is conventionally used as disclosed in Patent Document 1. The PLL includes a phase comparator (phase error detector), a loop filter, and a voltage controlled oscillator (VCO). Hereinafter, a PLL that generates a carrier signal synchronized with the wobble signal will be referred to as a wobble PLL.

  As a phase detection method using the wobble PLL, a so-called heterodyne detection method is used in which a beat component which is a frequency difference between two signals having close frequencies is detected.

  For example, FIG. 10 is an example of a PLL device. In FIG. 10, 101 is an AD converter having a 10-bit width, 102 is a multiplier, 103 is an LPF that removes the double frequency component of the carrier, 104 is a loop filter, and 105 is a digital VCO.

  In FIG. 10, a wobble signal that has been photoelectrically converted from an optical pickup (not shown) and then reproduced by matrix calculation is converted into 10-bit digital data by an AD converter 101, and multiplied by an 8-bit carrier signal by a multiplier 102. . By multiplication, a frequency difference component and a sum component of both the wobble signal and the carrier signal are generated. The LPF 103 removes the sum component of the frequencies and passes only the frequency difference component. A control signal is appropriately generated from the difference component of the passed frequency by the loop filter 104 having loop characteristics, and is supplied to the control input of the digital VCO 105 to form a loop, so that the frequency of the carrier signal that is the output of the digital VCO 105 is set. I have control.

By adopting such a configuration, it is possible to generate a carrier signal that is phase-locked with the wobble signal. Also, a second carrier signal whose phase is shifted by 90 degrees from the phase-locked carrier signal is multiplied by the wobble signal, thereby generating a modulation component such as PSK. Address information can be detected by this modulation component.
JP 2004-362630 A

  In the conventional wobble signal processing, since a multi-bit high-speed AD converter is used, there is a problem that the circuit scale around the AD converter increases and the power consumption increases accordingly. Specifically, first, a multi-bit AD converter is used in order to accurately process a wobble signal whose amplitude or the like fluctuates depending on the laser light quantity or the disk reflectivity. Furthermore, a multiplier corresponding to the subsequent stage performs multiplication with a carrier signal expressed by multiple bits.

  Here, assuming that the frequency of the wobble signal to be reproduced is about 820 kHz, a sampling frequency of 20 times or more is required to accurately reproduce the signal. Therefore, the operating frequency of the AD converter requires about 20 MHz. . Furthermore, if the number of bits of AD is 10 bits and the number of bits of the carrier signal is 8 bits, an 18-bit multiplier as an output is required to operate at 20 MHz.

  Usually, when the operating frequency and the number of bits of the AD converter increase, the circuit of the AD converter itself becomes complicated and the power consumption increases. As the number of bits of each of the two inputs to be multiplied increases, the circuit scale also increases in the subsequent multiplier. As the circuit scale increases, the operation speed in an actual IC circuit is limited.

  On the other hand, reducing the number of bits of the wobble signal or carrier signal or lowering the sampling frequency lowers the S / N of the digital wobble signal and the S / N at the time of phase error detection, and as a result, improves the phase detection accuracy. There was a risk of deteriorating and degrading the performance of the PLL.

  Similarly, the S / N of the post-detection signal in the post-digital detection circuit is lowered, and as a result, the detection accuracy of the modulated component is deteriorated, which may degrade the address detection performance.

  Furthermore, when all or some of the circuits such as multipliers are configured by analog circuits, it becomes sensitive to temperature characteristics and element variations, and it is difficult to maintain sufficient circuit performance. From such a point, it has been desired to cope with wobble modulation having sufficient performance while suppressing an increase in circuit scale and power consumption. In addition, a higher speed AD converter is required as the speed increases.

  An object of the present invention is to provide an optical disc recording / reproducing apparatus capable of obtaining sufficient performance while suppressing an increase in circuit scale and power consumption.

  In order to solve the above problems, the following is provided. A wobble signal detector for detecting a wobble signal based on reflected light of an optical disk having a wobbled track; and a VCO whose output oscillation frequency changes in accordance with an input, the wobble signal and the output of the VCO In the optical disk recording / reproducing apparatus for controlling the VCO by the phase error of the above, a modulator that performs delta-sigma modulation on the wobble signal, and a bandpass filter that includes a frequency corresponding to the wobble signal modulated by the modulator in a band, A phase error detector for detecting the phase error from the output of the bandpass filter and the output of the VCO, and the VCO is controlled based on the output of the phase error detector. apparatus.

  According to the present invention, a 1-bit digital bit stream is output to a wobble AD converter using a delta-sigma AD converter having a simple circuit configuration, and arithmetic processing with a carrier signal is performed. It becomes possible to simplify. Furthermore, before performing arithmetic processing with the carrier signal, it passes through a band-pass filter and extracts only the frequency corresponding to the modulation component of the wobble signal, thereby simplifying the circuit scale and maintaining detection accuracy. It becomes possible.

  That is, it is possible to simplify AD conversion, which has been increased in circuit scale in the past, and to process a subsequent processing circuit since processing is performed with 1 bit. Furthermore, by providing a bandpass filter that extracts only the frequency corresponding to the modulation component of the wobble signal, the S / N after multiplication by the heterodyne method can be improved, and the error rate of address information can be improved. Can do.

  Further, since the circuit scale is simplified, not only the cost can be reduced, but also the operation can be performed faster than the conventional one, and it is possible to cope with the high speed of the optical disc.

(First embodiment)
The best mode for carrying out the present invention will be described below in detail with reference to the drawings.

  A block diagram of the wobble PLL of the optical disk recording / reproducing apparatus according to the present invention is shown in FIG.

  Reference numeral 1 in FIG. 1 denotes an optical disc on which information is recorded and reproduced. Note that the optical disk is removable. Next, the optical disk recording / reproducing apparatus of FIG. Reference numeral 2 denotes a spindle motor that rotates the disk, and reference numeral 3 denotes a control circuit that controls the rotation of the motor including a motor driver that drives the spindle motor. Reference numeral 5 denotes a pickup that performs recording / reproduction with respect to the optical disk, and reference numeral 6 denotes an analog signal processing circuit that amplifies the outputs of a plurality of sensors included in the pickup and generates a signal of a wobble component that is a push-pull output. Further, 7 is a delta sigma AD converter which is a modulator for delta sigma modulating a wobble signal, 8 is a band pass filter, 9 is a phase error detector, 10 is a loop filter, and 11 is a digital VCO.

  Next, the operation will be described. The spindle motor-2 rotates the optical disc 1 at an appropriate number of revolutions by the motor control circuit 3. Next, the semiconductor laser included in the optical pickup 5 irradiates the disk 1 with light, and the reflected light from the disk is received by a sensor in the optical pickup 5. Based on the signal from the sensor in the optical pickup 5, the irradiation light to the disk is operated and controlled along the groove while focusing on the groove existing on the disk 1 by a servo circuit (not shown).

  The reflected light from the disk having the wobbled track is subjected to matrix calculation by the analog signal processing circuit 6 based on the output signal from the sensor in the optical pickup 5 to detect the wobble signal. The analog signal processing circuit 6 is a wobble signal detector that detects a wobble signal described in claims.

  The wobble signal generated by the analog signal processing circuit 6 is converted by a delta sigma AD converter 7 into a 1-bit digital bit stream sampled at a high speed at the frequency of the input clock.

  Furthermore, the band pass filter 8 passes 820 kHz corresponding to the frequency of the wobble signal from the 1-bit digital bit stream signal. Here, the band pass filter 8 may be operated by a clock having a fixed output frequency. By operating with a clock having this fixed output frequency, the pass band of the bandpass filter can be made constant, and 820 kHz corresponding to the frequency of the wobble signal can be passed stably. On the other hand, when a clock having a non-fixed output frequency is used, if the clock disturbance is large, the pass band of the band-pass filter may fluctuate, and 820 kHz corresponding to the frequency of the wobble signal may not pass stably.

  Here, an example of the configuration of the bandpass filter will be described. For example, the band-pass filter is composed of an IIR second order, and its transfer function HBPF is expressed by the following equation (1).

This is shown in a block diagram in FIG. However, 300 to 303 are delay units, 304 to 306 are adders, and 307 to 308 are multipliers for multiplying fixed coefficients. Here, the delay device in FIG. 3 can stabilize the frequency characteristics of the band-pass filter by operating at the timing of a clock having a fixed output frequency.

  Next, the phase error is detected by the calculation of the output of the bandpass filter 8 and the carrier signal which is another input in the phase error detector 9. The details of the calculation will be described later in detail.

  The phase error signal detected by the phase error detector 9 is appropriately filtered by the loop filter 10 so as to match the loop characteristics, and output to the digital VCO 11 as a frequency control signal. In the digital VCO 11, an oscillation frequency is determined according to the input frequency control signal, and a cosine wave carrier and a sine wave carrier corresponding to the oscillation frequency are output. As described above, the output cosine wave carrier is the other input of the phase error detector 9 and is connected so as to detect a phase difference from the input.

  The digital VCO 11 is also called a numerically controlled oscillator (NCO). The numerically controlled oscillator changes the increment value of the internal counter according to the input value, and by referring to the sine wave table based on the internal counter and outputting the sine wave, the sine wave whose cycle changes according to the input Is generated.

  Of course, the digital VCO 11 may be configured to generate a clock with a higher frequency than the wobble signal and generate a sine wave by dividing the clock separately.

  By configuring the wobble PLL as described above, the phase of the carrier signal that is the output of the digital VCO 11 is locked with respect to the substantially sinusoidal wobble signal. The output of the digital VCO 11 is given to an address detector (not shown) as a reference for reading address information superimposed on the wobble signal. Although not shown in the figure, the spindle control information is connected to the spindle control unit for constant linear velocity control.

  Next, the delta sigma AD converter 7 of FIG. 1 will be described. A basic configuration of the delta-sigma AD converter is shown in FIG. The input in FIG. 2A is a wobble signal corresponding to the input of the delta sigma AD converter 7 in FIG. The delta-sigma AD converter includes a comparator 23 that binarizes the output of the integrator 22 with a predetermined threshold and generates a 1-bit output signal, and a delay device that delays the output of the comparator 23 by one clock of 20 MHz that is an operation clock. 24. Furthermore, it comprises a DA converter 25 for converting the output of the delay unit 24 into an analog binary having the threshold value as the center level, and a subtracting circuit 21 for subtracting the output of the DA converter 25 and the input signal.

  Although a detailed description is omitted, by adopting the above configuration, the delta-sigma AD can have a high-speed sampling frequency of 20 MHz while being 1-bit output. Then, by converting the noise spectrum to a high frequency, AD conversion is realized so that a low frequency component has a high S / N.

  Details of the phase error detector 8 which is the main point of the present invention will be described with reference to FIG.

  In FIG. 3, 31 is a sign inversion circuit that multiplies the signal value by −1, 32 is a switch, 33 is an LPF, and 34 is a binarization circuit.

  The output signal of the band pass filter 8 is converted by the sign inverting circuit 31 into a signal whose polarity is inverted. The switch 32 switches the output signal of the bandpass filter 8 and the output of the sign inverting circuit 31 whose sign is inverted, using the signal obtained by binarizing the carrier signal by the binarizing circuit 34 as a switching control signal. That is, when the carrier signal is 1, a signal whose sign is not inverted is selected, and when it is 0, a signal whose sign is inverted is selected. The LPF 33 removes unnecessary components from the output of the switch 32 and outputs a phase error detection signal. Note that by expressing the output signal of the bandpass filter 8 as a 2's complement, -1 times can be realized by NOT logic and adders for the number of bits, not by a multiplier circuit. That is, it can be realized by a NOT logic that inverts each bit and an adder for adding 1. The above operation is performed with the same clock as the operation clock of the delta sigma AD converter, which is the output rate of the delta sigma AD converter.

  In the present embodiment, multiplication processing is realized by switching the output signal of the bandpass filter 8 between positive and negative with a signal obtained by binarizing the carrier. By multiplying, it is possible to detect a frequency difference between the wobble signal component and the carrier signal component, that is, a change in frequency or a change in phase. In other words, the phase error component of the wobble signal is frequency converted to the DC region.

Here, if wobble is SIN (ωot) and the carrier signal is COS (ωct),
SIN (ωot) * COS (ωct)
= SIN {(ωo−ωc) · t} + SIN {(ωo + ωc) · t}
The first term represents the component of the frequency difference between the two, and the latter represents the component of the frequency sum of the two. That is, the frequency fluctuation of the wobble signal is converted into the DC domain by the heterodyne method.

  This is shown in FIG. The graph of FIG. 5 shows the phase detection amount with respect to the phase shift amount of both. As described above, the phase error detection curve has a SIN shape. In FIG. 5, the state of signals at three points indicated by dotted lines is shown corresponding to the arrows. In each figure, (a) is a wobble signal, (b) is a carrier signal, (c) is a result of multiplication processing, and (d) is a signal after LPF. As shown in (2), when the phase difference between the wobble signal and the carrier signal is 90 degrees, the phase error detection amount is zero. Further, in the case of (3) where the phases of both are substantially in phase, a positive value is output as the detected value, and in the case of (1) where the phases are opposite, a negative value is output.

  Further, in order to explain this operation, a state in the frequency domain is shown in FIG. FIG. 6A shows a signal spectrum obtained by passing the signal after the delta-sigma AD conversion through the band-pass filter 8. Next, FIG. 6B shows a signal spectrum that has been multiplied by switching the output signal of the bandpass filter 8 with a signal obtained by binarizing the carrier signal that is the output of the VCO 11. As can be seen from FIG. 6 (b), the spectrum after multiplication has frequencies in the phase error detection component existing in the vicinity of DC, which is the frequency difference between the wobble signal and the carrier signal, and the frequency sum component of the wobble signal and the carrier signal. Converted. In this case, since both frequencies are substantially the same, the latter frequency sum component is approximately 1.6 MHz, which is approximately twice the frequency of the wobble signal. Thereafter, FIG. 6 (e) shows a signal in which only the phase error detection component existing in the vicinity of DC is output by the LPF having the frequency characteristics as indicated by the one-dot chain line, with the latter frequency sum component removed. This is the spectrum.

  On the other hand, FIG. 6C shows a signal spectrum after delta-sigma AD conversion that has not been passed through the bandpass filter 8. Since the wobble signal is a substantially sine wave, it has a spectrum having a peak at about 820 kHz as its frequency, and a noise spectrum that increases as it goes up to a half band of 20 MHz as the sampling frequency.

  It can be seen that the noise spectrum due to delta-sigma is dominant as compared with the signal spectrum of FIG. When heterodyne multiplication is performed in the state where noise remains before multiplication in this way, a component due to noise is included in the phase error detection component existing in the vicinity of DC as in the signal spectrum of FIG. Thus, the S / N in the phase error detection component is deteriorated.

  Therefore, by passing only the vicinity of the frequency of the modulation component by the band pass filter 8, the S / N is improved in the phase error detection component. Therefore, the operating frequency of the delta-sigma AD converter can be realized at a frequency equivalent to that of the conventional AD converter.

  In this way, the circuit scale is reduced and the consumption is increased by configuring the AD, which has been increased in circuit scale in the conventional example, and the subsequent multiplication process with the delta-sigma AD and the switch operating with the same operation clock as the conventional one. Electric power can be reduced. In addition, since the band pass filter that passes only the frequency corresponding to the wobble signal is provided, the S / N of the phase error signal equivalent to the conventional one can be secured, and the PLL can be operated stably. . Furthermore, by operating the bandpass filter with a clock having a fixed output frequency, the passband of the bandpass filter can be made constant, and the frequency corresponding to the wobble signal can be passed stably. Further, even when the optical disc is increased in speed, the PLL can be kept stable.

(Second embodiment)
FIG. 7 is a block diagram showing an embodiment of an optical disc recording / reproducing apparatus according to the present invention. FIG. 7 mainly shows the PSK detection circuit in detail. In FIG. 7, a circuit for recording information on an optical disk, a circuit for reproducing information, a servo control circuit for performing focus control and tracking control, or a controller and mechanism for controlling the entire apparatus are omitted. Also, in FIG. 7, the numbers assigned the same reference numerals as in FIG. 1 will not be repeated.

  In FIG. 7, 12 is a wobble PLL circuit which is a signal generator for generating a sine wave carrier signal, 13 is a computing unit, 14 is a low-pass filter, and 15 is an address reproduction circuit for generating wobble address information.

  The spindle motor 2 is controlled by a motor control circuit 3 and rotationally drives the optical disc 1 at an appropriate rotational speed. Next, a laser beam of a semiconductor laser (not shown) in the optical pickup 5 is irradiated on the optical disc 1, and reflected light from the optical disc 1 is received by a sensor in the optical pickup 5. A servo control circuit (not shown) based on a signal from a sensor in the optical pickup 5 performs servo control so that the irradiation light on the optical disk 1 scans along the groove while focusing on the groove on the optical disk 1.

  An output signal from a sensor in the optical pickup 5 is supplied to an analog signal processing circuit 6, and the analog signal processing circuit 6 performs a matrix operation on the basis of the signal to detect a wobble signal.

  The wobble signal generated by the analog signal processing circuit 6 is converted by a delta sigma AD converter 7 into a 1-bit digital bit stream sampled at a high speed at the frequency of the input clock.

  Further, the band pass filter 8 passes 820 kHz corresponding to the modulation component of the wobble signal from the 1-bit digital bit stream signal. Here, the band pass filter 8 may be operated by a clock having a fixed output frequency not shown. By operating with a clock having this fixed output frequency, the pass band of the bandpass filter can be made constant, and 820 kHz corresponding to the frequency of the wobble signal can be passed stably. On the other hand, when a clock with a non-fixed output frequency is used, if the clock disturbance is large, the pass band of the band-pass filter fluctuates, and 820 kHz corresponding to the frequency of the wobble signal cannot be passed stably. There is. Also in this embodiment, the same band pass filter as that in the first embodiment is used. In addition, although the case where the component of PSK modulation is detected is described as an example this time, when the component of MSK modulation is detected, the pass band of the bandpass filter is set to about 960 kHz corresponding to the frequency of the wobble signal. Similarly, when detecting the STW modulation component, the pass band of the bandpass filter is set to about 1.9 MHz corresponding to the STW modulation component.

  On the other hand, the sine wave carrier synchronized with the wobble signal is reproduced by the wobble PLL circuit 12. The sine wave carrier is input to the calculator 13.

  The calculator 13 calculates the PSK modulation information by calculating the bandpass filter 8 output and the sine wave carrier output from the PLL circuit 8. The calculation process will be described later in detail. The PSK modulation information detected by the calculator 13 removes unnecessary high-frequency components in the subsequent low-pass filter 14 and outputs a PSK detection signal. Thereafter, the address reproduction circuit 15 detects the synchronization signal from the PSK detection signal, determines the address bit, and reproduces the address information.

  Details of the arithmetic unit 13 which is the main point of the present invention will be described with reference to FIG.

  In FIG. 8, 31 is a sign inversion circuit for multiplying the signal value by −1, 32 is a switch, 33 is an LPF, and 34 is a binarization circuit.

  The output signal of the band pass filter 8 is converted by the sign inverting circuit 31 into a signal whose polarity is inverted. The switch 32 switches the output signal of the bandpass filter 8 and the output of the sign inverting circuit 31 whose sign is inverted, using the signal obtained by binarizing the carrier signal by the binarizing circuit 34 as a switching control signal. That is, when the carrier signal is 1, a signal whose sign is not inverted is selected, and when it is 0, a signal whose sign is inverted is selected. The LPF 33 removes unnecessary components from the output of the switch 32 and outputs PSK modulation information. Note that by expressing the output signal of the bandpass filter 8 as a 2's complement, -1 times can be realized by NOT logic and adders for the number of bits, not by a multiplier circuit. That is, it can be realized by a NOT logic that inverts each bit and an adder for adding 1. The above operation is performed with the same clock as the operation clock of the delta sigma AD converter, which is the output rate of the delta sigma AD converter.

  In the present embodiment, multiplication processing is realized by switching the output of the bandpass filter 8 between positive and negative with a signal obtained by binarizing the carrier signal. By multiplying, the phase difference between the wobble signal component and the carrier signal component can be detected. That is, the original modulation information is reproduced by frequency-converting the PSK component of the wobble signal into the DC region.

Here, the wobble signal is expressed as SIN (θ + α). However, α = 0 during no modulation and α = π during PSK modulation. Further, the carrier signal is SINθ. The multiplication result can be calculated as follows.
SIN (θ + α) × SIN (θ)
= (1/2) · {COS (α) −COS (2θ + α)}
In this equation, the first term represents the phase change, that is, the component modulated by PSK, and the second term represents the sum component of the phase. That is, the first term is COS (0) = 1 at the time of no modulation and COS (π) = − 1 at the time of PSK modulation. Since the second term is a component having a frequency twice the wobble, it is removed by the downstream LPF.

  It should be noted that not only PSK described in the present embodiment but also MSK and STW can be detected with the same configuration.

  Here, as shown in FIG. 9, a configuration may be used in which the output of the bandpass filter 8 is supplied to the wobble PLL circuit 12 to generate a carrier signal. However, since the operation of each block in FIG. 9 is the same as that of the present embodiment, the description will not be repeated.

  As described above, in the present embodiment, the circuit scale is increased by configuring the AD, which has been increased in circuit scale in the conventional example, and the subsequent multiplication processing by using the delta sigma AD and the switch that operate with the same operation clock as the conventional one. And power consumption can be reduced. In addition, since the band pass filter that passes only the frequency corresponding to the modulation component of the wobble signal is provided, the S / N of the detected modulation information equivalent to the conventional one can be secured, and the error rate of the address information Can be improved. Furthermore, the error rate of the address information can be maintained even when the optical disc is increased in speed. Further, by operating the bandpass filter with a clock having a fixed output frequency, the passband of the bandpass filter can be made constant, and the frequency corresponding to the wobble signal can be passed stably. Further, even when the optical disc is increased in speed, the PLL can be kept stable.

  In addition to the above-described effect, when the configuration for generating the carrier signal based on the output of the bandpass filter 8 is used, the S / N of the phase error signal can be secured, and the PLL circuit operates stably. Can be made. Therefore, the error rate of the address information can be further improved.

The block diagram for demonstrating the whole structure of this invention Basic block diagram of AD converter using delta-sigma modulation and diagram showing signal and noise spectrum in delta-sigma modulation An example of a block diagram of a bandpass filter in the present invention Block diagram of the phase error detector in the first embodiment The figure which showed the situation of the phase error detector detected corresponding to the phase difference The figure explaining the spectrum of each part in the multiplication by a heterodyne system The block diagram for demonstrating the whole structure in a 2nd Example. Block diagram of a computing unit in the second embodiment Block diagram of a computing unit in the third embodiment Block diagram of phase error detector in conventional example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Optical disk 2 Spindle motor 3 Motor control circuit 5 Optical pick-up 6 Analog signal processing circuit 7 Delta-sigma AD converter 8 Band pass filter 9 Phase error detection circuit 10 Decimation filter 11 Digital VCO
12 wobble PLL circuit 13 arithmetic unit 14 low-pass filter 15 address information reproduction circuit 21 adder 22 comparator 23 DA converter 24 delay unit 31 sign inversion circuit 32 switch 33 low-pass filter 34 binarization circuit 101 10-bit AD
102 Multiplier 103 Carrier Cut Filter 104 Loop Filter 105 Digital VCO

Claims (6)

A wobble signal detector for detecting a wobble signal based on reflected light of an optical disk having a wobbled track;
And a VCO whose output oscillation frequency changes according to the input,
In an optical disc recording / reproducing apparatus for controlling the VCO by a phase error between the wobble signal and the output of the VCO,
A modulator for delta-sigma modulating the wobble signal;
A bandpass filter including a frequency corresponding to the wobble signal modulated by the modulator in a band;
A phase error detector for detecting the phase error from the output of the bandpass filter and the output of the VCO;
An optical disc recording / reproducing apparatus that controls the VCO based on an output of the phase error detector. In an optical disc recording / reproducing apparatus for recording or reproducing information with respect to an optical disc on which address information is recorded by wobbling a track and modulating the wobbling,
A wobble signal detector for detecting a wobble signal based on reflected light from the optical disc;
A modulator for delta-sigma modulating the wobble signal;
A bandpass filter including a frequency corresponding to the wobble signal modulated by the modulator or a frequency corresponding to a modulation component of the wobble signal in a passband;
A signal generator for generating a carrier signal whose phase is synchronized with the wobble signal;
An arithmetic unit for calculating the output of the bandpass filter and the carrier signal;
An optical disc recording / reproducing apparatus comprising: a reproducing circuit for reproducing the address information based on an output of the computing unit. In an optical disc recording / reproducing apparatus that records or reproduces information on an optical disc on which address information is recorded by wobbled on a track and modulating the wobble,
A wobble signal detector for detecting a wobble signal by the wobble based on reflected light from the optical disc;
A modulator for delta-sigma modulating the wobble signal;
A bandpass filter including a frequency corresponding to the wobble signal modulated by the modulator or a frequency corresponding to a modulation component of the wobble signal in a passband;
A VCO whose output oscillation frequency changes according to the input;
A phase error detector for detecting a phase error from the output of the bandpass filter and the output of the VCO;
Means for controlling the output of the VCO based on the output of the phase error detector;
A signal generator for generating a carrier signal whose phase is synchronized with the wobble signal;
An arithmetic unit for calculating the output of the bandpass filter and the carrier signal;
An optical disc recording / reproducing apparatus comprising: a reproduction circuit that reproduces the address information based on an output of the computing unit.   The said phase error detector detects the said phase error by calculating by the heterodyne system based on the output of the said band pass filter, and the output of the said VCO, The Claim 1 or 3 characterized by the above-mentioned. Optical disc recording / reproducing apparatus.   The arithmetic unit detects the modulation component by performing a calculation by a heterodyne method based on the output of the bandpass filter and the carrier signal that is the output of the VCO. 4. An optical disc recording / reproducing apparatus according to 3.   4. The optical disk recording apparatus according to claim 1, wherein the band-pass filter is operated by a clock having a fixed output frequency.

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