JP2008176832A - Recorder and control method of recorder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate a recording clock synchronizing stably with rotation of a disk. <P>SOLUTION: The recording device which detects a wobble signal by reading wobble formed in a disk type recording medium and which generates a clock signal for recording based on the wobble signal, is provided with a first clock generating means generating a clock having a frequency relating to a wobble period of the disk type recording medium, and a second clock generating means generating a clock having a frequency relating to a channel period for recording data in the disk type recording medium, wherein the second clock generating means is composed by incorporating a same DVCO part as a DVCO part incorporated in the first clock generating means. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a recording apparatus and a control method for the recording apparatus, and more particularly to a technique suitable for use in recording data on a disk-shaped recording medium.

  2. Description of the Related Art Conventionally, an apparatus for recording / reproducing digital data on an optical disk such as a DVD is known (for example, see Patent Document 1). In a DVD, a spiral laser beam guide groove (groove) is formed from the center of the disk toward the outer periphery, and digital data is recorded therein. The guide groove slightly wobbles with a predetermined (preset) amplitude and a single period in the radial direction.

Here, a configuration example of a circuit for generating a recording clock is shown in a block diagram of FIG.
In FIG. 2, the wobble formed on the optical disc 201 is read by the optical pickup 202, and the wobble signal is detected by the wobble detection unit 203. Next, the wobble signal detected by the comparator unit 204 is compared with a predetermined (preset) slice level to detect the zero cross point of the wobble signal.

  The phase detection unit 205 compares the zero-cross timing with the phase difference between the output signals output from the frequency divider 208 and outputs a phase error signal corresponding to the phase difference. The phase error signal is supplied to the VCO unit 207 via the loop filter unit 206 and controls the VCO unit 207 so as to generate a phase-locked clock. The output of the VCO unit 207 is input to the phase detection unit 205 via the frequency divider 208. For data recording, a clock signal generated in the VCO unit 207 is used.

JP 2002-32962 A

  However, in the “clock signal generator” described in Patent Document 1, a PLL circuit is configured by an analog circuit. For this reason, there has been a problem that the characteristics of the circuit are likely to fluctuate due to changes in the surrounding environment such as temperature changes and changes with time. In addition, there is a problem that adjustment and sorting are necessary.

  SUMMARY OF THE INVENTION In view of the above-described problems, the present invention has an object to generate a recording clock that is stably synchronized with the rotation of a disk.

The recording apparatus of the present invention is a recording apparatus that reads a wobble formed on a disk-shaped recording medium, detects a wobble signal, and generates a recording clock signal based on the wobble signal. First clock generating means for generating a clock having a frequency related to the wobble period of the medium, and a second clock for generating a clock having a frequency related to the channel period for recording data on the disc-shaped recording medium Generation means, and the second clock generation means is configured by incorporating the same digital VCO section as the digital VCO section incorporated in the first clock generation means.
Another feature of the recording apparatus of the present invention is that the wobble signal detecting means for reading the wobble signal formed on the disk-shaped recording medium and the reference phase signal formed on the disk-shaped recording medium are read. A reference phase signal detection means, a first clock generation means for generating a clock having a frequency related to a wobble cycle using the wobble signal detected by the wobble signal detection means, and the first clock generation means. Based on the generated clock, address detection means for detecting address information, filter processing for removing a noise component by applying gain processing to the control signal of the first clock generation means, the gain processing and the The frequency component from which the noise component has been removed by the filter means is used as the control signal, and the frequency associated with the channel period A second clock generating means for generating a clock having the first clock generating means, the first clock generating means and the second clock generating means, wherein the first clock and the wobble clock, and the second clock and the channel clock. Phase difference detection means for detecting a phase difference, sine wave signal generation means for generating a sine wave signal based on a phase difference detection result output from the phase difference detection means, and a sine output from the sine wave signal generation means Time difference detection for detecting a time difference between the reference phase signal detected by the phase difference detecting means and the control means for controlling the first and second clock generating means and the channel clock based on the frequency value of the wave signal And the frequency difference between the reference phase signal and the channel clock is calculated as an offset value from the time difference detected by the time difference detecting means. An offset calculating means that, characterized in that it comprises an offset value adding means for adding an offset value calculated by the offset calculating means to a control signal of the second clock generating means.

The control method for a recording apparatus of the present invention is a control method for a recording apparatus that reads a wobble formed on a disk-shaped recording medium, detects a wobble signal, and generates a recording clock signal based on the wobble signal. A first clock generating step for generating a clock having a frequency related to the wobble period of the disk-shaped recording medium, and a clock having a frequency related to a channel period for recording data on the disk-shaped recording medium. A second clock generation step for generating the second clock generation step, wherein the same digital VCO unit as that used in the first clock generation step is also used in the second clock generation step. A clock having a frequency is generated.
Another aspect of the control method of the recording apparatus of the present invention is that a wobble signal detecting step for reading a wobble signal formed on a disc-shaped recording medium and a reference phase formed on the disc-shaped recording medium are provided. A reference phase signal detection step of reading a signal, a first clock generation step of generating a clock having a frequency related to a wobble period using the wobble signal detected in the wobble signal detection step, and the first clock An address detection step for detecting address information based on the clock generated in the generation step; a filter step for applying a gain process to the control signal in the first clock generation step to remove a noise component; and the gain The frequency component from which noise components have been removed in the processing and the filtering step is used as a control signal, In the second clock generation step for generating a clock having a frequency related to the clock cycle, the first clock generation step and the second clock generation step, the first clock and the wobble clock, the second clock generation step, A phase difference detection step for detecting a phase difference between a clock and a channel clock; a sine wave signal generation step for generating a sine wave signal based on a phase difference detection result output from the phase difference detection step; and the sine wave signal A control step for controlling the first and second clock generation steps based on a frequency value of the sine wave signal output from the generation step; the reference phase signal and the channel clock detected in the phase difference detection step; Detecting a time difference between the reference phase signal and the channel clock from the time difference detected in the time difference detection step. An offset calculating step of calculating a wave number shift as an offset value, characterized in that it comprises an offset value adding step for adding an offset value calculated in the offset calculating step the control signal in the second clock generation step.

The program of the present invention is a program that reads a wobble formed on a disc-shaped recording medium, detects a wobble signal, and causes a computer to execute a step of generating a recording clock signal based on the wobble signal, A first clock generating step for generating a clock having a frequency related to the wobble period of the disk-shaped recording medium; and a clock having a frequency related to a channel period for recording data on the disk-shaped recording medium. A second clock generation step, and using the same digital VCO unit as that used in the first clock generation step also in the second clock generation step, a frequency related to the channel period is set. A computer is caused to execute a process of generating a clock having To.
Another feature of the program of the present invention is that a wobble signal detection step for reading a wobble signal formed on a disk-shaped recording medium and a reference for reading a reference phase signal formed on the disk-shaped recording medium are provided. A phase signal detection step, a first clock generation step for generating a clock having a frequency related to a wobble cycle using the wobble signal detected in the wobble signal detection step, and a generation in the first clock generation step An address detecting step for detecting address information based on the clocks; a filter step for applying a gain process to the control signal in the first clock generating step to remove a noise component; the gain process and the filter The frequency component from which noise components have been removed in the process is used as the control signal, and the channel period In a second clock generation step for generating a clock having a related frequency, and in the first clock generation step and the second clock generation step, the first clock and the wobble clock, the second clock and the channel From a phase difference detection step for detecting a phase difference with a clock, a sine wave signal generation step for generating a sine wave signal based on a phase difference detection result output from the phase difference detection step, and the sine wave signal generation step Based on the frequency value of the output sine wave signal, the control step for controlling the first and second clock generation steps, and the time difference between the reference phase signal detected in the phase difference detection step and the channel clock is calculated. A time difference detection step to detect, and a frequency difference between the reference phase signal and the channel clock from the time difference detected in the time difference detection step. And an offset value adding step of adding the offset value calculated in the offset calculating step to the control signal in the second clock generating step. .

  According to the reproducing apparatus of the present invention, it is possible to generate a recording clock that is highly accurate and stably synchronized with the rotation of the disc. As a result, it is possible to provide a recording apparatus that can reduce fluctuations in circuit characteristics due to changes in the surrounding environment such as changes in temperature and changes over time, and that can be easily adjusted and selected.

(First embodiment)
An embodiment of the present invention will be described with reference to FIG.
In FIG. 1, a wobble signal for tracking control output by an optical pickup (not shown) is supplied to a terminal 101. Here, as an example, a DVD-R disc is used as a disc-shaped recording medium, and the DVD-R disc is rotated at a double speed. Then, meandering (wobble) of the guide groove formed on the disk-shaped recording medium is detected as a wobble signal. The wobble signal has a clock frequency of 281.29 KHz and a recording data frequency of 52.32 MHz.

  Here, recording clock generation will be described. The phase comparison unit 103 multiplies the wobble signal converted into the digital signal by the output signal of the wobble DVCO unit (digital VCO unit) 105 and extracts the low frequency to perform phase comparison. Then, the result of the phase comparison is supplied as a clock having a frequency related to the wobble period to the wobble DVCO unit 105 via the loop filter unit 104, thereby generating a phase-locked wobble clock unit. 105 is controlled. The address detector 122 detects address information at a prescribed phase timing.

  Further, the integrator output of the loop filter unit 104 provided in the wobble PLL unit 107 is passed through the amplifier 108 and multiplied by a predetermined (preset) gain. Next, a recording clock (channel clock) is output from the analog PLL unit 114 by passing through a low-pass filter unit (LPF unit) 109 for removing noise components and adding the frequency error value to the channel DVCO unit 112 in the adder 110. To do. Here, the integrator output of the loop filter unit 104 is used for the purpose of further stabilizing the noise component, but there is no problem in operation even if the output value of the loop filter unit 104 is connected.

Next, correction of the recording clock timing will be described.
A reference phase signal is detected from a digital signal output from the AD conversion unit 102 by a reference phase signal detection unit 115 functioning as a phase difference detection unit, and the counter unit 116 is operated in accordance with the detection timing. The reference phase signal is recorded in advance as a preformat on a disk-shaped recording medium. For example, in the case of DVD-R and DVD-RW discs, a land pre-pit detection unit that detects a land pre-pit of a reference phase signal, and in the case of DVD + R and DVD + RW discs, an ADIP detection unit that detects an ADIP of a reference phase signal is used as a reference. Detect a phase signal.

  Based on the count value of the counter unit 116 operating with the channel clock output from the analog PLL unit 114, the modulation unit 117 modulates the channel data, and the recording data is output to the laser control unit (not shown) via the output terminal 118. Output to.

Next, the operation of the time difference detection unit 119 will be described with reference to FIG.
The time difference detector 119 receives the reference signal detection flag from the reference phase signal detector 115 and the channel clock timing from the analog PLL unit 114. The reference signal detection flag is “1” when the reference signal is detected, and is “0” when the reference signal is not detected. The reference signal detection flag is output to the offset calculation unit 120 as “signal s”.

  When the channel clock and the reference phase signal are synchronized, as shown in FIG. 5A, the timing of the “counter value 0” and the reference phase signal detection flag coincide. FIG. 5B shows a case where the reference phase signal detection flag is earlier by 3 channel clocks, and FIG. 5C shows a case where the reference phase signal detection flag is later by 3 channel clocks.

  The number of clocks between the channel clock and the reference phase signal is output to the offset calculation unit 120 as “signal t”. For example, as shown in FIG. 5C, when the reference phase signal detection flag is delayed by 3 channel clocks, “3” is output as “signal t” to the offset calculation unit 120.

  The offset calculation unit 120 is supplied from the time difference detection unit 119 as the “reference phase signal detection flag signal s” and the time shift amount between the reference phase signal and the channel clock as the “signal t”. For example, when signals s = “1” and t = “3” are input, the channel clock must be delayed by 3 channel clocks.

  That is, in the case of normal synchronization, since 1488 clocks per frame are counted for 1491 clocks, 3 channel clocks for the control signal of the channel DVCO unit 112 Add an offset for minutes. Then, it is operated so as to be synchronized with the reference phase signal. For example, if the control signal (= center frequency setting value + frequency error value) of the channel DVCO unit 112 is 84630, “84630 × (3/1488) = 170”.

  Therefore, by adding “−170 offset” to the control signal of the channel DVCO unit 112, the reference phase signal and the channel clock can be synchronized. Further, when the reference phase signal detection flag s = “0” is input from the time difference detection unit 119, the offset calculation unit 120 is configured to hold the value.

  The mode switching signal input to the offset calculation unit 120 via the input terminal 121 is configured such that the gain value can be switched so that the added amount of offset can be changed.

Next, the operations of the wobble DVCO unit 105 and the channel DVCO unit 112 will be described with reference to FIGS.
The wobble DVCO unit 105, the channel DVCO unit 112, and the subsequent ΔΣDA conversion unit 113 operate with an 81 MHz clock supplied from a crystal oscillator.

  FIG. 3A is a diagram illustrating a specific configuration example of the wobble DVCO unit 105. In FIG. 3A, the terminal 301 is supplied with a set value corresponding to the target frequency of the clock. Here, the DVD-R disc double speed is taken as an example of the optical disc, the target clock frequency is 281.290 KHz, and 3640 is set. In this case, “3640 × 81e6 ÷ 2 ^ 20 = 281118 Hz”.

  The value of the center frequency input from the terminal 301 and the frequency error value input from the terminal 302 are added by the adder 303. The addition result of the adder 303 is further added to the adder 304. An addition wiring is connected to the other terminal of the adder 304, and a 20-bit value held in the register 305 is added through this addition wiring. Then, the integrator configuration is such that the addition result is added to the register 305 again. That is, a circuit including the adder 304, the register 305, and the addition wiring functions as an integration unit that performs an operation of integrating the added value at a predetermined period.

  Although the addition result of the register 305 may overflow, it is ignored here without carrying it. The upper 7 bits of the register 305 are input to the sign table 306. The sign table 306 represents, for example, a “0 ° to 360 ° phase” with a 7-bit value “0 to 127”. That is, “input value 1” represents “360 ° ÷ 128 = 2.8 °”. The sine table 306 outputs an 8-bit sine wave value (frequency value of a sine wave signal) corresponding to the input phase to a terminal 307. That is, these circuit configurations function as sine wave signal generation means.

  The state of bit allocation is shown in FIG. A to D in FIG. 3B correspond to the respective signals in FIG. For example, if the frequency error given to the terminal 302 is “0” and the center frequency given to the terminal 301 is “3640”, A in the figure is “3640”.

  Since the register 305 has 20 bits and the clock has a frequency of 81 MHz oscillated from the crystal oscillator, the register 305 overflows with a period of “81e6 × 3640/2 ^ 20 = 281118 Hz”. However, in this embodiment, the upper 7 bits of this register 305 are taken out without carrying and the result is output to the sign table 306.

  Further, if “1” is given to the terminal 302, A in FIG. 3 becomes “3641”, so that the clock frequency becomes “81e6 × 3641/2 ^ 20 = 281258 Hz”, and every time the input changes by “1”. The clock frequency changes by “77 Hz”.

FIG. 4A is a diagram illustrating a specific configuration example of the channel DVCO unit 112.
In FIG. 4A, a setting value corresponding to the target frequency of the clock is supplied to the terminal 401. Here, the DVD-R disc double speed is taken as an example of the optical disc, and the target clock frequency is multiplied by 8 to “6.54 MHz” to be 52.32 MHz, and “84630” is set. That is, “84630 × 81e6 ÷ 2 ^ 20 = 65353766 Hz”.

  The adder 403 adds the value of the center frequency input from the terminal 401 and the frequency error value input from the terminal 402. The addition result of the adder 403 is further added to the adder 404. An addition wiring is connected to the other terminal of the adder 404, and a 20-bit value held in the register 405 is added through this addition wiring. Then, the integrator configuration is such that the addition result is added to the register 405 again. That is, a circuit including the adder 404, the register 405, and the addition wiring functions as an integration unit that performs an operation of integrating the added value at a predetermined period.

  Although the addition result of the register 405 may overflow, it is ignored here without carrying. The upper 7 bits of register 405 are added to sign table 406. The sign table 406 expresses a phase of “0 ° to 360 °” with, for example, a 7-bit value “0 to 127”. That is, “input value 1” represents “360 ° ÷ 128 = 2.8 °”. The sine table 406 outputs an 8-bit sine wave value (frequency value of a sine wave signal) corresponding to the input phase to a terminal 407. That is, these circuit configurations function as sine wave signal generation means.

  FIG. 4B shows the state of bit allocation. A to D in FIG. 4B correspond to the signals in FIG. For example, if the frequency error given to the terminal 402 is “0” and the center frequency given to the terminal 401 is “84630”, A in FIG. 4 is “84630”.

  Since the register 405 has 20 bits and the clock has a frequency of 81 MHz oscillated from the crystal oscillator, the register 405 overflows with a period of “81e6 × 84630/2 ^ 20 = 6537466 Hz”. However, in this embodiment, the upper 7 bits of this register 405 are taken out without carrying, and the result is input to the sine table 406 to generate a sine wave.

  The ΔΣDA conversion unit 113 converts the sine wave output result into an analog voltage and outputs the analog voltage to the analog PLL unit 114. The analog PLL unit 114 includes a phase comparator, a loop filter unit, a VCO unit, and a frequency divider (all not shown), and is a known PLL unit for clock multiplication.

  For example, by multiplying, for example, a 6.54 MHz sine wave output from the ΔΣ DA conversion unit 113, a clock of “52.32 MHz” is generated and used as a recording clock signal. In the present embodiment, the frequency division ratio of the frequency divider is 1/8, but other values may be taken. For example, in the case of DVD-R disc quadruple speed, the division ratio may be 1/16. Further, although the oscillation frequency of the crystal oscillator is set to “81 MHz”, other values can be taken.

Here, the center frequency setting value of the wobble DVCO unit 105 and the channel DVCO unit 112 and the setting value of the amplifier 108 will be described.
For example, taking DVD-R disc double speed as an example, the center frequency setting value of the wobble DVCO unit 105 input to the input terminal 106 is “3640”, and the center of the channel DVCO unit 112 input from the input terminal 111. “84630” was set as the frequency setting value.

  Therefore, the center frequency setting value of the wobble DVCO unit 105 and the center frequency setting value of the channel DVCO unit 112 have a relationship of “23.25 times”. Therefore, “23.25” is set in the amplifier 108. In this case, “3640 × 23.25 = 84630”.

  In this embodiment, the wobble DVCO unit 105 and the channel DVCO unit 112 have the same configuration. Therefore, the relationship of “23.25 times” is also applied to the frequency error value 302 of the wobble DVCO unit 105 in FIG. 3 and the frequency error value 402 of the channel DVCO unit 112 in FIG. For example, if the integrator output value of the loop filter unit 104 of the wobble PLL unit 107 is “12”, the control signal of the channel DVCO unit 112 is “12 × 23.25 + 84630 = 84909”. Therefore, the recording clock frequency is “81e6 × 84909 ÷ 2 ^ 20 × 8 = 52472145 Hz”, and the relationship of “23.25 times” is established.

  As described above, according to the recording apparatus of the present embodiment, the DVCO unit having the same configuration is incorporated in the wobble PLL unit 107 and the channel PLL. As a result, an increase in circuit scale and power consumption can be prevented with a single circuit configuration of the analog VCO unit without providing two analog VCO units, and the cost can be reduced.

  In addition, since the time difference between the reference phase signal and the channel clock is calculated and added as an offset amount to the control signal of the channel DVCO unit 112, a highly accurate recording clock signal that is accurately synchronized with the rotation of the disk is generated. Made it possible.

(Other embodiments according to the present invention)
Each means constituting the recording apparatus and each step of the control method of the recording apparatus in the embodiment of the present invention described above can be realized by operating a program stored in a RAM or ROM of a computer. This program and a computer-readable storage medium storing the program are included in the present invention.

  Further, the present invention can be embodied as a system, apparatus, method, program, storage medium, or the like. Specifically, the present invention may be applied to a system composed of a plurality of devices, or may be applied to an apparatus composed of a single device.

  In the present invention, a software program that implements the functions of the above-described embodiments may be directly applied to a system or apparatus. Alternatively, it may be achieved by supplying from a remote location and the computer of the system or apparatus reads and executes the supplied program code.

  Accordingly, since the functions of the present invention are implemented by computer, the program code installed in the computer also implements the present invention. In other words, the present invention includes a computer program itself for realizing the functional processing of the present invention.

  In that case, as long as it has the function of a program, it may be in the form of object code, a program executed by an interpreter, script data supplied to the OS, and the like.

  Examples of the storage medium for supplying the program include a floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, MO, CD-ROM, CD-R, and CD-RW. Moreover, a magnetic tape, a non-volatile memory card, ROM, DVD (DVD-ROM, DVD-R), etc. are also included.

  As another program supply method, the program can be supplied by connecting to a homepage on the Internet using a browser of a client computer and downloading the computer program of the present invention from the homepage. Alternatively, it can be supplied by downloading a compressed file including an automatic installation function to a storage medium such as a hard disk.

  It can also be realized by dividing the program code constituting the program of the present invention into a plurality of files and downloading each file from a different homepage. That is, a WWW server that allows a plurality of users to download a program file for realizing the functional processing of the present invention on a computer is also included in the present invention.

  Also, the program of the present invention is encrypted, stored in a storage medium such as a CD-ROM, distributed to users, and encrypted from a homepage via the Internet to users who have cleared predetermined (preset) conditions. Download key information to solve the problem. It is also possible to execute the encrypted program by using the key information and install the program on a computer.

  Further, the functions of the above-described embodiments are realized by the computer executing the read program. In addition, based on the instructions of the program, an OS or the like running on the computer performs part or all of the actual processing, and the functions of the above-described embodiments can also be realized by the processing.

  Further, the program read from the storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. Thereafter, the CPU of the function expansion board or function expansion unit performs part or all of the actual processing based on the instructions of the program, and the functions of the above-described embodiments are realized by the processing.

1 is a block diagram illustrating an exemplary configuration of a recording apparatus according to an embodiment of the present invention. It is a block diagram which shows the structural example of the conventional recording device. It is a figure which shows embodiment of this invention and shows the wobble DVCO part and its operation | movement. It is a figure which shows embodiment of this invention and shows a channel DVCO part and its operation | movement. It is a figure which shows embodiment of this invention and shows operation | movement of a time difference detection part.

Explanation of symbols

101 terminal 102 AD conversion unit 103 phase comparison unit 104 loop filter unit 105 wobble DVCO unit 106 input terminal 107 wobble PLL unit 108 amplifier 109 low pass filter unit 110 adder 111 input terminal 112 channel DVCO unit 113 ΔΣ DA conversion unit 114 analog PLL unit 115 Reference phase signal detection unit 116 Counter unit 117 Modulation unit 118 Output terminal 119 Time difference detection unit 120 Offset calculation unit 121 Input terminal 122 Address detection unit

Claims (10)

A recording device that reads a wobble formed on a disk-shaped recording medium, detects a wobble signal, and generates a recording clock signal based on the wobble signal,
First clock generating means for generating a clock having a frequency related to a wobble period of the disc-shaped recording medium;
Second clock generating means for generating a clock having a frequency related to a channel period for recording data on the disc-shaped recording medium,
The recording apparatus according to claim 1, wherein the second clock generation means is configured by incorporating the same digital VCO section as the digital VCO section incorporated in the first clock generation means. Wobble signal detection means for reading a wobble signal formed on a disk-shaped recording medium;
A reference phase signal detection means for reading a reference phase signal formed on the disc-shaped recording medium;
First clock generation means for generating a clock having a frequency related to a wobble period using the wobble signal detected by the wobble signal detection means;
Address detecting means for detecting address information based on the clock generated by the first clock generating means;
Filter means for applying a gain process to the control signal of the first clock generation means to remove a noise component;
A second clock generation unit configured to generate a clock having a frequency related to a channel period using the frequency component from which the noise component has been removed by the gain processing and the filter unit as a control signal;
The first clock generation unit and the second clock generation unit include a phase difference detection unit that detects a phase difference between the first clock and a wobble clock, and a second clock and a channel clock, and the phase difference detection A sine wave signal generating means for generating a sine wave signal based on the phase difference detection result output from the means, and the first and second sine wave signals based on the frequency value of the sine wave signal output from the sine wave signal generating means. A control means for controlling the clock generation means, a time difference detection means for detecting a time difference between the reference phase signal detected by the phase difference detection means and the channel clock, and a time difference detected by the time difference detection means. An offset calculating means for calculating a frequency shift between the reference phase signal and the channel clock as an offset value, and the offset calculating means Recording apparatus characterized by comprising an offset value adding means for the out offset value is added to the control signal of the second clock generating means. The phase difference detection means includes conversion means for converting the phase difference between the wobble clock and the first clock and the phase difference between the channel clock and the second clock into frequency errors, respectively.
The sine wave signal generating means includes an adding means for adding a set value related to a target frequency of the sine wave signal and the converting means, and an integrating means for performing an adding operation of the added value of the adding means at a predetermined cycle. The recording apparatus according to claim 2, further comprising: The second clock generation means includes a phase comparator, a loop filter means for inputting a phase error result output from the phase comparator, and an oscillation for outputting a signal having a frequency corresponding to the output of the loop filter means as a clock. And a PLL circuit comprising a frequency divider for dividing the clock output from the oscillation means,
The recording apparatus according to claim 2, wherein the sine wave signal output from the sine wave signal generation unit and the output signal of the frequency divider are input to the phase comparator. The first clock generation means and the second clock generation means include crystal oscillation means for generating a preset operation clock frequency,
The recording apparatus according to claim 2, wherein the integration unit performs the integration operation according to an operation clock output from the crystal oscillation unit. A control method for a recording apparatus that reads a wobble formed on a disk-shaped recording medium to detect a wobble signal and generates a clock signal for recording based on the wobble signal,
A first clock generating step for generating a clock having a frequency related to a wobble period of the disc-shaped recording medium;
A second clock generation step of generating a clock having a frequency related to a channel period for recording data on the disc-shaped recording medium,
The same digital VCO unit used in the first clock generation step is also used in the second clock generation step to generate a clock having a frequency related to the channel period. A control method for a recording apparatus. A wobble signal detection step of reading a wobble signal formed on a disk-shaped recording medium;
A reference phase signal detection step of reading a reference phase signal formed on the disc-shaped recording medium;
A first clock generation step of generating a clock having a frequency related to a wobble period using the wobble signal detected in the wobble signal detection step;
An address detection step of detecting address information based on the clock generated in the first clock generation step;
A filter step for applying a gain process to the control signal in the first clock generation step to remove a noise component;
A second clock generation step of generating a clock having a frequency related to a channel period using the frequency component from which the noise component has been removed in the gain processing and the filtering step as a control signal;
In the first clock generation step and the second clock generation step, a phase difference detection step of detecting a phase difference between the first clock and the wobble clock, the second clock and a channel clock, and the phase difference Based on the phase difference detection result output from the detection step, a sine wave signal generation step for generating a sine wave signal, and based on the frequency value of the sine wave signal output from the sine wave signal generation step, the first and From the control step for controlling the second clock generation step, the time difference detection step for detecting the time difference between the reference phase signal detected in the phase difference detection step and the channel clock, and the time difference detected in the time difference detection step An offset calculating step for calculating a frequency shift between the reference phase signal and the channel clock as an offset value; Control method for a recording apparatus, characterized in that it comprises an offset value adding step of the calculated offset value is added to the control signal in the second clock generation step in step. A program for reading a wobble formed on a disk-shaped recording medium to detect a wobble signal and causing a computer to execute a process of generating a recording clock signal based on the wobble signal,
A first clock generating step for generating a clock having a frequency related to a wobble period of the disc-shaped recording medium;
A second clock generation step of generating a clock having a frequency related to a channel period for recording data on the disc-shaped recording medium,
The same digital VCO unit used in the first clock generation step is also used in the second clock generation step, and a step of generating a clock having a frequency related to the channel period is executed on the computer. A program characterized by letting A wobble signal detection step of reading a wobble signal formed on a disk-shaped recording medium;
A reference phase signal detection step of reading a reference phase signal formed on the disc-shaped recording medium;
A first clock generation step of generating a clock having a frequency related to a wobble period using the wobble signal detected in the wobble signal detection step;
An address detection step of detecting address information based on the clock generated in the first clock generation step;
A filter step for applying a gain process to the control signal in the first clock generation step to remove a noise component;
A second clock generation step of generating a clock having a frequency related to a channel period using the frequency component from which the noise component has been removed in the gain processing and the filtering step as a control signal;
In the first clock generation step and the second clock generation step, a phase difference detection step of detecting a phase difference between the first clock and the wobble clock, the second clock and a channel clock, and the phase difference Based on the phase difference detection result output from the detection step, a sine wave signal generation step for generating a sine wave signal, and based on the frequency value of the sine wave signal output from the sine wave signal generation step, the first and From the control step for controlling the second clock generation step, the time difference detection step for detecting the time difference between the reference phase signal detected in the phase difference detection step and the channel clock, and the time difference detected in the time difference detection step An offset calculating step for calculating a frequency shift between the reference phase signal and the channel clock as an offset value; A program characterized by executing the offset value addition step of adding the offset value calculated in the step control signal in the second clock generation process to the computer.   A computer-readable storage medium storing the program according to claim 8 or 9.

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