JP2008170566A - Scanning driver ic for plasma display drive - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a scanning electrode drive circuit of a PDP suppressing the overcurrent in an initialization period without increasing an address period. <P>SOLUTION: A scanning pulse generation section included in a plasma display panel scanning electrode drive circuit having a plurality of output transistors, has a switch circuit which switches the response speed of an output from the output transistors by adjusting the voltage between the gate/source of the output transistors. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a scan driver IC for driving a plasma display panel, a plasma display, and a method for driving scan electrodes of a plasma display panel.

  A plasma display is a display device that utilizes a light emission phenomenon associated with gas discharge. Plasma display panels (hereinafter referred to as PDPs) are advantageous over other display devices in terms of large screens, thinning, and wide viewing angles. This PDP is roughly classified into a DC type that operates with a DC pulse and an AC type that operates with an AC pulse. The AC type PDP has high luminance and a simple structure, and is suitable for mass production and high definition.

  The AC type PDP usually has a three-electrode surface discharge type structure. In this structure, address electrodes are arranged in the vertical direction on the rear substrate of the PDP, and sustain electrodes and scanning electrodes (usually referred to as X electrode and Y electrode, respectively) are alternately arranged on the front substrate of the PDP. It is arranged in the horizontal direction. Here, the address electrodes and the scan electrodes generally change individual potentials one by one.

  A discharge cell is provided at the intersection of the above-described sustain electrode, scan electrode, and address electrode, and a pulse voltage is applied to each electrode.

  By the way, the PDP driving device controls the potentials of the sustain electrode, the scan electrode, and the address electrode in accordance with an ADS (Address Display-period Separation) method. This ADS method is a kind of subfield method. In the subfield method, one field of an image is composed of a plurality of subfields. Further, one subfield includes an initialization period, an address period, and a discharge sustain period. In the ADS system, the above three periods are set in common for all discharge cells of the PDP.

  First, in the initialization period, an initialization pulse voltage is applied between the sustain electrode and the scan electrode. This makes the wall charges uniform in all the discharge cells.

  Next, in the address period, a scan pulse voltage is sequentially applied to the scan electrodes, and an address pulse voltage is applied to some of the address electrodes. When a scan pulse voltage is applied to one of the scan electrodes and an address pulse voltage is applied to one of the address electrodes, a discharge cell at the intersection of the scan electrode and the address electrode emits light. Due to the discharge, wall charges are accumulated on the surface of the discharge cell.

  Next, in the sustain period, a sustain discharge pulse voltage is applied simultaneously and periodically to all pairs of sustain electrodes and scan electrodes. The sustaining voltage pulse here is lower than the discharge start voltage. However, in a discharge cell in which wall charges are accumulated during the address period, a voltage (wall voltage) due to the wall charges is added to the sustaining voltage pulse. Therefore, since the voltage between the sustain electrode and the scan electrode exceeds the discharge start voltage, the discharge is maintained.

  By the way, high efficiency is currently demanded for image display of PDP. Development of increasing the partial pressure of Xe, which is a gas in the discharge cell (high Xe partial pressure), is being promoted as one technique for realizing the high efficiency. However, when the partial pressure of Xe is increased, the wall charge of the discharge cell may be easily released. This is because priming floating in the discharge cell space due to initialization in the initialization period or sustain discharge in the discharge sustain period, electrons released from MgO of the protective film activated by the sustain discharge, etc. are waiting for writing This is because the wall charges accumulated by the initialization are gradually neutralized by the electric field in the discharge cell. The loss of the wall charges of the discharge cell may cause a delay in discharge and frequent write (address) mistakes, making it difficult to form good image quality. As a measure for preventing such omission, there is generally a technique of increasing the scanning pulse voltage (V1) to weaken the electric field in the discharge cell during address standby and suppress neutralization of wall charges. It has been taken.

There are Patent Documents 1 and 2 as prior art documents related to the present application. Patent Document 1 discloses an electronic device in which a transient power supply current increase is smaller than that in a conventional case when forcing all outputs of a column driver to either “H” or “L” in order to reset a display panel. An output circuit for a display device driving circuit is disclosed. Patent Document 2 discloses an output circuit in which noise generation associated with a transient response during switching of a transistor in an output stage is suppressed and a factor for increasing power consumption is removed.
JP-A-5-313597 Japanese Patent Laid-Open No. 11-41083

  In recent years, with regard to PDP image display, high definition, that is, full HD (High Definition) has been demanded. In a PDP with full HD, the number of scan electrodes and sustain electrodes increases, and the panel capacity of the entire panel increases. By the way, in the scan operation of the scan driver IC in the address period, the transistor of the scan driver IC (Lo side transistor) is turned on with a considerably high slew rate for the sake of discharge stability, that is, to avoid discharge failure. It is requested to do. Furthermore, if the slew rate of the address period is increased, the entire address period becomes longer, and there may be a problem that it is difficult to increase the gradation in the PDP. In particular, it can be said that this problem can occur in a high-definition PDP or a single-scan PDP (PDP in which the PDP address electrodes are not divided at the top and bottom of the panel but set in one vertical line). From the above points, the transistor of the scan driver IC needs to have a slew rate at turn-on higher than a predetermined value.

  On the other hand, in the initialization period and the sustain period, the scan driver IC changes all the scan electrodes from H (High) (all high) to L (Low) (all low) or L (Low) (all low). You must switch to H (High) (all high). As described above, the scan pulse voltage (V1) is normally set to be high due to the high Xe voltage division, the panel capacity is increased due to full HD, and the slew rate of the scan operation is large. When the output of the scan driver IC is switched all at once, a transiently large peak current tends to occur in the output of the scan driver IC. As a result, the current flowing into the components (for example, the switch elements) on the current path around the increase increases the number of parallel use of these components.

The relationship between the panel capacitance Cp, the scan pulse voltage V1, the scan driver output current IOUT, and the slew rate T is generally expressed by the following equation (1). From this equation (1), it can be seen that the peak current IOUT increases as the panel capacitance Cp increases, the scan pulse voltage V1 increases, and the slew rate T increases.
Cp × V1 = IOUT × T (1)

  The present invention has been made to solve the above-described problems, and prevents the occurrence of overcurrent due to simultaneous switching of the transistors of the scan driver IC during the initialization period and the sustain period, while preventing the address period from becoming longer. An object of the present invention is to provide an output circuit for driving.

The present invention has been made to achieve the above object. The scan pulse generator according to claim 1 of the present invention comprises:
A scan pulse generator included in a plasma display panel scan electrode drive circuit having a plurality of output transistors,
It further has a switch circuit that adjusts the gate-source voltage of the output transistor to switch the response speed of the output from the output transistor.

The scan pulse generator according to claim 2 according to the present invention comprises:
2. The switch circuit temporarily reduces a response speed of an output from the output transistor by temporarily relaxing an increase or decrease in a gate-source voltage of the output transistor. It is a scanning pulse generation part of description.

The scan pulse generator according to claim 3 according to the present invention,
The second switching element circuit includes a first resistor;
3. The scan pulse generator according to claim 2, wherein the first resistor is used to temporarily moderate the rise or fall of the gate-source voltage of the output transistor.

The scan pulse generator according to claim 4 according to the present invention comprises:
The second switching element circuit includes a first capacitor;
3. The scan pulse generator according to claim 2, wherein the first capacitor is used to temporarily moderate the rise or fall of the gate-source voltage of the output transistor.

The scan pulse generator according to claim 5 according to the present invention,
The switch circuit temporarily decreases a response speed of an output from the output transistor by temporarily narrowing a range of increase or decrease of the gate-source voltage of the output transistor. 1 is a scanning pulse generation unit according to 1;

The scan pulse generator according to claim 6 of the present invention includes:
The third switching element circuit includes a first diode;
6. The scan pulse generator according to claim 5, wherein the first diode is used to temporarily narrow the range of increase or decrease of the gate-source voltage of the output transistor.

A plasma display panel scan electrode drive circuit according to claim 7 of the present invention is provided.
A plasma display panel scan electrode drive circuit including the scan pulse generator according to claim 1.

The display device according to claim 8 according to the present invention includes:
A display device on which the plasma display panel scan electrode drive circuit according to claim 7 is mounted.

According to the present invention, the slew rate of the gate voltage applied to the output transistor can be switched at an arbitrary timing by the switch circuit. Thereby, only when the scanning switch is switched from ALL-H to ALL-L (or ALL-L to ALL-H), the slew rate of the gate voltage can be reduced and the response speed of the output of the output transistor can be reduced. In addition, it is possible to use an output transistor having a high slew rate that is required in the address period, and to suppress the occurrence of overcurrent at the time of simultaneous switching of the output transistors. Further, since the effective value of the current also decreases, the number of parallel use of parts (switch elements and the like) on the current flow path can be reduced.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, exemplary embodiments of the invention will be described with reference to the accompanying drawings.

[Embodiment 1]
FIG. 1 is an equivalent circuit diagram showing a schematic circuit configuration of a scan electrode driving circuit 10 of a PDP according to Embodiment 1 of the present invention.

  As shown in FIG. 1, the scan electrode drive circuit 10 includes a scan pulse generator 1Y (scan driver IC 11Y), an initialization pulse generator 2Y, a discharge sustain pulse generator 3Y, and a recovery circuit 4Y. Note that the panel capacitance of the PDP driven by the scan electrode driving circuit 10 shown in FIG. 1 is assumed to be Cp. Hereinafter, the operation of each unit will be described.

(Scanning pulse generator)
FIG. 2 is a detailed circuit diagram of the scan pulse generator 1Y (scan driver IC11Y) in the scan electrode drive circuit 10 shown in FIG. The scan pulse generator 1Y (scan driver IC11Y) includes a push-pull output circuit including a first constant voltage source V1, a Hi side (high side) transistor Q1Y and a Lo side (low side) transistor Q2Y, a level shift circuit 14, and a transistor. A switch circuit 18 for adjusting the change speed (response speed) of the output voltage of Q2Y is included.

  The switch circuit 18 includes a resistor R1 connected to the gate of the Lo-side transistor Q2Y and switching elements QS3 and QS4 that are switched according to the period. The switching element QS3 is connected in parallel to the series circuit of the resistor R1 and the switching element QS4. The drain of the switching element QS3 and one end of the resistor R1 are connected to the gate of the Lo-side transistor Q2Y. The gate terminals of the switching elements QS3 and QS4 are connected to the control terminal S1. Switching element QS3 is composed of a P-channel MOS, switching element QS4 is composed of an N-channel MOS, and these switching elements QS3 and QS4 operate in a complementary manner.

  Here, FIG. 18 shows a detailed circuit diagram of the scan driver IC 13Y in the conventional scan electrode driving circuit. The scan driver IC 11Y of this embodiment shown in FIG. 2 is different from the conventional scan driver IC 13Y shown in FIG.

  The switch circuit 18 transmits the control signal IN3 to the gate of the switching element Q2Y directly or via the resistor R1 by switching the switching elements QS3 and QS4. That is, in the switch circuit 18, the switching element QS3 is turned off and the QS4 is turned on, thereby connecting the resistor R1 to the gate of the Lo-side transistor Q2Y. At this time, the control signal IN3 is transmitted to the gate of the Lo-side transistor Q2Y via the resistor R1, and the rising (or falling) speed (slew rate) of the control signal IN3 is decreased by the resistor R1. As a result, the drive capability of the Lo-side transistor Q2Y is reduced, and the speed (response speed) at which the transistor is turned on is reduced. As a result, as will be described in detail later, the peak of current generated when the Lo-side transistor Q2Y is turned on can be suppressed. In FIG. 2, the Hi-side transistor Q1Y and the Lo-side transistor Q2Y are CMOS, but these may be bipolar or IGBT.

  In the scan pulse generator 1Y (scan driver IC11Y) shown in FIG. 2, the positive electrode of the first constant voltage source V1 is connected to the source of the Hi-side transistor Q1Y. The drain of the Hi side transistor Q1Y is connected to the drain of the Lo side transistor Q2Y, and the connection point between them is connected to the scan electrode. The source of the Lo-side transistor Q2Y is connected to the negative electrode of the first constant voltage source V1. The switch circuit 18 is connected to the gate of the Lo-side transistor Q2Y.

  The level shift circuit 14 is connected to the gate of the Hi-side transistor Q1Y and is applied with the first constant voltage source V1. Further, the output control signals IN1 and IN2 are connected to the level shift circuit 14, and the external terminal of the output control signal IN3 is connected to the source of the switching element QS3 and the drain of the switching element QS4. Accordingly, the scan driver output voltage VOUT is controlled by the control signals IN1, IN2, and IN3.

  Note that the number of push-pull output circuits including the Hi-side transistor Q1Y and the Lo-side transistor Q2Y is actually provided in the same number as the scanning electrodes.

(Initialization pulse generator)
Next, a schematic configuration of the initialization pulse generator 2Y will be described. As shown in FIG. 1, the initialization pulse generator 2Y includes a second constant voltage source V2, a Hi side ramp waveform generation (positive initialization) unit QR1, a Lo side ramp waveform generation (negative initialization) unit QR2, 3 constant voltage sources V3, a first separation switch QS1, and a second separation switch QS2.

  The Hi side ramp waveform generation (positive initialization) part QR1 and the Lo side ramp waveform generation (negative initialization) part QR2 are each composed of an N-channel MOSFET (NMOS) and a capacitor connecting the gate and drain of the NMOS. The When the ramp waveform generators QR1 and QR2 are turned on, the voltage between the drain and source of the NMOS constituting them becomes zero at a constant speed.

  The positive electrode of the second constant voltage source V2 is connected to the drain of the Hi side ramp waveform generation (positive initialization) part QR1. The source of the Hi-side ramp waveform generation (positive initialization) part QR1 is connected to the negative electrode of the first constant voltage source V1. The negative electrode of the second constant voltage source V2 is grounded. The drain of the Lo side ramp waveform generation (negative initialization) part QR2 is connected to the negative electrode of the first constant voltage source V1. The source of the Lo side ramp waveform generation (negative initialization) part QR2 is connected to the negative electrode of the third constant voltage source V3. The positive electrode of the third constant voltage source V3 is grounded.

  The source of the second separation switch QS2 is connected to the negative electrode of the first constant voltage source V1. The drain of the second separation switch QS2 is connected to the drain of the first separation switch QS1, and the source of the first separation switch QS1 is connected to a connection point with the discharge sustaining pulse generator 3Y.

(Discharge sustain pulse generator)
Next, a schematic configuration of the sustaining pulse generator 3Y will be described. As shown in FIG. 1, the discharge sustain pulse generator 3Y includes a series circuit of a DC power supply Vs, a Hi-side sustain switch element Q7Y, and a Lo-side sustain switch element Q8Y.

  The DC power source Vs maintains the positive electrode potential higher than the negative electrode potential by a constant voltage Vs. The positive electrode of DC power supply Vs is connected to the drain of Hi side sustain switch element Q7Y, and the source of Hi side sustain switch element Q7Y is connected to the drain of Lo side sustain switch element Q8Y. The source of the Lo-side sustain switch element Q8Y is connected to the negative electrode of the DC power supply Vs. The negative electrode of the DC power supply Vs is grounded.

(Recovery circuit)
Next, the recovery circuit 4Y includes, for example, a recovery inductor, a recovery capacitor, a recovery diode, and a MOSFET. The MOSFET here may be an IGBT or a bipolar.

  FIG. 3 is a diagram showing a sequence of signals in one subfield in scan electrode driving circuit 10 shown in FIG. The operation of each signal in the subfield in scan electrode driving circuit 10 according to the first embodiment of the present invention will be described below.

(Initialization period)
During the initialization period, the Lo-side transistor Q2Y is turned off and the Hi-side transistor Q1Y is turned on while the first separation switch element QS1, the second separation switch element QS2 and the Lo-side sustain switch element Q8Y are maintained in the on state. And the remaining switches are kept off. As a result, the potential of the scan electrode rises from the ground potential to the first power supply voltage V1. Here, due to the voltage increase of V1 and the integration current of the panel capacitance charge Cp, the current flows simultaneously to the scan electrode portion of the scan driver IC11Y.

  Next, the first separation switch QS1 and the Lo side sustain switch element Q8Y are turned off while the Hi side transistor Q1Y and the second separation switch Q2Y are maintained in the on state, and the Hi side ramp waveform is generated (positive initialization). Part QR1 is turned on. The remaining switches are kept off. As a result, the potential of the scan electrode rises to Vr (V1 + V2) obtained by adding the voltage V2 from the potential V1 at a constant speed. At this time, the drain potential of the first separation switch element QS1 also rises via the second separation switch element QS2. When the drain potential of the first separation switch QS1 becomes the voltage V2 by the second constant voltage source V2, the Hi-side sustain switch element Q7Y is turned on.

  Next, the Hi-side ramp waveform generator (positive initialization) QR1 is turned off while the Hi-side transistor Q1Y, the second separation switch element QS2, and the Hi-side sustain switch element Q7Y are maintained in the ON state, and the first The separation switch QS1 is turned on. The remaining switches are kept off. Thereby, the potential of the scan electrode is maintained at (Vs + V1).

  Next, the Hi-side transistor Q1Y is turned off and the Lo-side transistor Q2Y is turned on while the first separation switch element QS1, the second separation switch element QS2, and the Hi-side sustain switch element Q7Y are maintained in the on state. . Here, the current flows through the scan electrode portion of the scan driver IC11Y all at once due to the voltage drop of V1 and the integration current of the charge Cp of the panel capacitance.

  As a result, an overcurrent tends to flow through the Lo-side transistor Q2Y. However, in the switch circuit 18, by switching the signal of the control terminal S1 from the L signal to the H signal, the switching element QS3 composed of the P channel MOS is turned off and the switching element QS4 composed of the N channel MOS is turned on. . By doing so, the resistor R1 is added to the gate of the Lo side transistor Q2Y, and the voltage between the gate and the source gradually rises to the maximum value by this resistor R1, and the overcurrent in the Lo side transistor Q2Y is suppressed. . One switching element Q2S is maintained in the off state.

  Next, the Hi-side sustain switch element Q7Y and the second isolation switch element QS2 are turned off while the Lo-side transistor Q2Y and the first isolation switch QS1 are maintained in the ON state, and Lo-side ramp waveform generation (negative initialization) ) Part QR2 is turned on. The remaining switches are kept off. As a result, the potential of the scan electrode drops to the potential −V3 at a constant speed.

(Address period)
During the address period, the Lo side ramp waveform generation (negative initialization) part QR2 and the Hi side transistor Q1Y are maintained in the on state, and the Lo side transistor Q2Y is maintained in the off state. Here, the current flows all at once in the scan electrode portion of the scan driver IC 11Y due to the integration of the voltage rise of V1 and the charge Cp of the panel capacitance.

  At this time, the source of the Hi-side transistor Q1Y is maintained at a potential (V1-V3) that is higher by the voltage V1 of the first constant voltage source V1 than −V3, and the source of the Lo-side transistor Q2Y is maintained at −V3. . Further, the potential of the scan electrode sequentially follows a switching operation between -V3 and (V1-V3).

  In the present embodiment, in the initialization period and the sustain period, the switching element QS3 composed of the P-channel MOS is turned off and the switching element QS4 composed of the N-channel MOS is turned on, while in the address period, the switching element QS4 is turned on. Switching element QS3 composed of channel MOS is turned on, and switching element QS4 composed of N channel MOS is turned off. As a result, the resistor R1 added to prevent overcurrent in the initialization period is disconnected from the gate of the Lo-side transistor Q2Y in the address period. Therefore, in the initialization period, while suppressing the occurrence of overcurrent due to simultaneous switching of the transistors, a large slew rate in designing the transistor Q2Y can be secured in the address period, and the address period can be prevented from being prolonged.

(Maintenance period)
At the end of the address period, the Hi-side transistor Q2Y is turned off, and the Lo-side transistor Q2Y, the second separation switch QS2, and the Lo-side sustain switch element Q8Y are turned on. The first separation switch element QS1 is kept on.

  Here, due to the voltage drop from (V1−V3) to zero and the integration current of the charge C of the panel capacitance, current flows all at once in the scan electrode portion of the scan driver IC11Y. As a result, an overcurrent tends to flow through the Lo-side transistor Q2Y. However, by switching the signal of the control terminal S1 from the outside of the gates of the switching elements QS3 and QS4 from the L signal to the H signal, the switching element QS3 configured by the P channel MOS is turned off and configured by the N channel MOS. The switching QS4 is turned on. By doing so, the resistor R1 is added to the gate of the Lo side transistor Q2Y, the gate-source voltage gradually rises to the maximum value, and the overcurrent in the Lo side transistor Q2Y is suppressed.

  Further, since the Lo-side sustain switch element Q8Y is turned on, the voltage across the panel capacitor Cp is first maintained at 0V.

  Next, the Lo side sustain switch element Q8Y is turned off, the Hi side sustain switch element Q7Y is turned on, and the potential of the scan electrode is maintained at Vs.

  Next, the Hi-side sustain switch element Q7Y is turned off, the Lo-side sustain switch element Q8Y is turned on, and the voltage across the panel capacitance Cp decreases (again) to 0V.

  The above is the outline of the operation of each signal in the subfield in scan electrode drive circuit 10 according to the first exemplary embodiment of the present invention. Each signal sequence repeats from the initialization period to the sustain period.

  FIG. 4 is an example of a driving timing chart in the conventional scan driver IC 13Y (see FIG. 18). The chart includes a gate signal input terminal IN3 of the Lo-side transistor Q2Y, a gate-source voltage VGS of the Lo-side transistor Q2Y, an output voltage VOUT of the push-pull output circuit, and a current IOUT that flows through the push-pull output circuit to ground. . VDD is a constant voltage source for applying a low voltage to the scan driver IC 13Y. “VGS (B)” in FIG. 4 indicates a gate-source voltage at point B in FIG.

  As shown in FIG. 4, the gate-source voltage VGS of the Lo-side transistor Q2Y is steep from L to H, that is, from 0 V to the set voltage of the constant voltage source VDD, by the signal at the gate signal input terminal IN3 of the Lo-side transistor Q2Y. Stand up to. As a result, as shown in FIG. 4, the output voltage VOUT of the push-pull output circuit also falls steeply from H to L, that is, from the constant voltage source V1 to 0V. As a result, as shown in FIG. 4, the current IOUT flowing to the ground in the push-pull output circuit becomes a high peak current.

  On the other hand, FIG. 5 is an example of a drive timing chart in the scan driver IC 11Y according to the first embodiment of the present invention. A chart of signals from the external control terminal S1 is also shown. In FIG. 5, “VGS (B)” indicates a gate-source voltage at point B in FIG.

  In the drive timing chart shown in FIG. 5, due to the action of the resistor R1, the gate-source voltage VGS of the Lo-side transistor Q2Y gradually rises from L to H, that is, from 0 V to the set voltage of the constant voltage source VDD. As a result, the output voltage VOUT of the push-pull output circuit also falls gently from H to L, that is, from the set voltage of the constant voltage source V1 to 0V. As a result, the peak (sharpness) of the current IOUT flowing to the ground through the push-pull output circuit is suppressed as compared with FIG.

  In the scan pulse generator 1Y (scan driver IC 11Y) according to the first embodiment of the present invention, the switch circuit 18 is connected to the gate of the Lo-side transistor Q2Y, and the output of the scan driver IC starts from ALL-H (all high). The control signal IN3 is transmitted to the gate of the Lo side transistor Q2Y via the resistor R1 only in the forced mode in which all the signals are switched to ALL-L (all low) at the same time. A circuit may be provided. For example, like the scan driver IC 14Y shown in FIG. 6, the switch circuit 18 including the resistor R1 and the switching elements QS3 and QS4 is connected to the gate of the Hi-side transistor Q1Y, and the output of the scan driver is ALL-L (all. The circuit setting may be such that the resistor R1 is used in the forced mode in which the mode is switched from low to ALL-H (all high) all at once.

  FIG. 7 is a diagram showing a sequence of signals in one subfield in scan electrode driving circuit 10 according to the first embodiment, incorporating scan driver IC 14Y shown in FIG. In the forced mode in which the outputs of the scan driver are simultaneously switched from ALL-L (all low) to ALL-H (all high), that is, when the high-side transistors Q1Y are simultaneously turned on, the switching elements QS3 and QS4 The signal from the outside to the control terminal S1 is switched from the L signal to the H signal.

  Further, FIG. 8 is an example of a driving timing chart when the gate-source voltage VGS of the Hi-side transistor Q1Y sharply falls from H to L in the conventional scan driver IC 13Y (see FIG. 18). 7 is a drive timing chart example when the gate-source voltage VGS of the Hi-side transistor Q1Y gently falls from H to L in the scan driver IC 14Y shown in FIG. 8 and 9, “C” indicates the potential at the point C in FIGS. 18 and 6, and “VGS (A)” indicates the gate-source voltage at the point A in FIGS. Show. Comparing FIG. 8 and FIG. 9, it can be seen that the peak (sharpness) is suppressed in the current IOUT flowing through the push-pull output circuit shown in FIG. 9 to the ground, similarly to the drive timing chart shown in FIG.

  In the scan driver IC 11Y according to the first embodiment described above, the switching element QS3 is a P-channel MOS and the switching element QS4 is an N-channel MOS. However, another semiconductor element may be used. The same applies to the following embodiments.

  As described above, in this embodiment, the switch circuit 18 is provided in front of the gates of the transistors Q1Y and Q2Y in the scan driver IC 14Y, and the slew rate of the gate voltage applied to the transistors Q1Y and Q2Y of the scan driver IC is switched at an arbitrary timing. I was able to do that. Thus, only when the scanning switch is switched from ALL-H to ALL-L (or ALL-L to ALL-H), the slew rate of the gate voltage can be reduced and the response speed of the output transistor can be reduced. Therefore, it is possible to use an output transistor having a high slew rate required in the address period, and to suppress the occurrence of overcurrent when the transistors Q1Y and Q2Y of the scan driver IC are simultaneously switched.

[Embodiment 2]
FIG. 10 is a detailed circuit diagram of scan pulse generator 1Y (scan driver IC 12Y) included in scan electrode circuit 10 of the PDP according to the second exemplary embodiment of the present invention. The scan driver IC 12Y according to the second embodiment is substantially the same as the scan driver IC 11Y according to the first embodiment, and the same parts are denoted by the same reference numerals and description thereof is omitted.

  The scan pulse generator 1Y (scan driver IC 12Y) according to the second embodiment includes a first constant voltage source V1, a push-pull output circuit including a Hi-side transistor Q1Y and a Lo-side transistor Q2Y, a level shift circuit 14, and a transistor Q2Y. The switch circuit 18 ′ for adjusting the change speed (response speed) of the output voltage is included.

  The switch circuit 18 'includes switching elements QS3 and QS4 and a diode D1 that are switched according to a period. The switching element QS3 is connected in parallel to the series circuit of the diode D1 and the switching element QS4. The drain of the switching element QS3 and the source of the switching element QS4 are connected to the gate of the Lo-side transistor Q2Y. The gate terminals of the switching elements QS3 and QS4 are connected to the control terminal S1. Switching element QS3 is composed of a P-channel MOS, switching element QS4 is composed of an N-channel MOS, and these switching elements QS3 and QS4 operate in a complementary manner.

  The source of the switching element QS3 and the anode of the diode D1 are connected to the external terminal of the output control signal IN3. The cathode of the diode D1 is connected to the drain of the switching element QS4.

  In the scan driver IC 12Y according to the second embodiment, the switching element QS4 is turned on and the switching element QS3 is turned off by a signal from the control terminal S1 from the outside, whereby the control signal IN3 is sent to the Lo-side transistor Q2Y via the diode D1. When the signal is transmitted to the gate, the voltage applied between the gate and the source is lower than the voltage of the original control signal IN3 due to the forward voltage drop of the diode D1. As a result, the drive capability of the Lo-side transistor Q2Y decreases. If this timing is matched when the Lo-side transistor QY2 is turned on, the speed at which the Lo-side transistor QY2 is turned on becomes slow. As a result, the change rate (response speed) of the output voltage of the Lo-side transistor QY2 can be reduced, and the peak of current that occurs when the Lo-side transistor QY2 is turned on can be suppressed. In FIG. 10, the Hi-side transistor Q1Y and the Lo-side transistor Q2Y are assumed to be CMOS, but these may be bipolar or IGBT.

  Since the initialization pulse generator 2Y and the sustaining pulse generator 3Y included in the scan electrode circuit 10 of the PDP according to the second embodiment of the present invention are the same as those in the first embodiment, the description will be given. Omitted.

  FIG. 11 is an example of a driving timing chart in the scan driver IC 12Y according to the second embodiment of the present invention. A chart of signals from the external control terminal S1 is also shown. Also in FIG. 11, “VGS (B)” indicates a gate-source voltage at point B in FIG.

  In the drive timing chart shown in FIG. 11, the maximum value of the gate-source voltage of the Lo-side transistor Q2Y drops from VDD to (VDD−VT) due to the presence of the threshold voltage VT of the diode D1, and thus the Lo-side transistor Q2Y. The driving ability of the is reduced. As a result, the output voltage VOUT of the push-pull output circuit also falls gently from H to L (that is, the changing speed of the output voltage VOUT decreases). As a result, the peak (sharpness) is suppressed in the current IOUT flowing to the ground through the scan electrode of the push-pull output circuit. Note that after the Lo-side transistor Q2Y is turned on, the signal from the external control terminal S1 is turned off and the switching element that is turned on is switched from the switching element QS4 to the switching element QS3. The gate-source voltage (its maximum value) has returned to VDD.

  In the scan pulse generator 1Y (scan driver IC 12Y) according to the second embodiment of the present invention, the switch circuit 18 ′ is connected to the gate of the Lo-side transistor Q2Y, and the output of the scan driver IC is ALL-H (all high). The control signal IN3 is transmitted to the gate of the Lo-side transistor Q2Y through the diode D1 only in the forced mode in which the switching from ALL to L-ALL (all low) is performed simultaneously. May be provided with a switch circuit 18 '. For example, as in the scan driver IC 15Y shown in FIG. 12, the switch circuit 18 ′ including the diode D1 and the switching elements QS3 and QS4 is connected to the gate of the Hi-side transistor Q1Y, and the output of the scan driver is ALL-L (all A circuit setting may be made such that the diode D1 is used in the forced mode in which switching from low to ALL-H (all high) is performed simultaneously.

  Further, FIG. 13 is a drive timing chart example when the gate-source voltage VGS of the Hi-side transistor Q1Y gradually falls from H to L in the scan driver IC 15Y shown in FIG. In FIG. 13, “C” indicates the potential at point C in FIG. 12, and “VGS (A)” indicates the gate-source voltage at point A in FIG. Here, comparing FIG. 8 and FIG. 13 (showing an example of a driving timing chart related to the conventional scan driver IC 13Y), the push-pull output circuit shown in FIG. 13 flows to the ground as in the driving timing chart shown in FIG. It can be seen that the peak (sharpness) can be suppressed in the current IOUT.

[Embodiment 3]
FIG. 14 is a detailed circuit diagram of scan pulse generator 1Y (scan driver IC 16Y) included in scan electrode circuit 10 of the PDP according to Embodiment 3 of the present invention. The scan driver IC 16Y according to the third embodiment is substantially the same as the scan driver IC 11Y according to the first embodiment, and the same portions are denoted by the same reference numerals and description thereof is omitted.

  The scan pulse generator 1Y (scan driver IC 16Y) according to the third embodiment includes a push-pull output circuit including a first constant voltage source V1, a Hi-side transistor Q1Y, and a Lo-side transistor Q2Y, a level shift circuit 14, and a transistor Q2Y. The switch circuit 18 ″ for adjusting the change speed (response speed) of the output power of the output power is included.

  The switch circuit 18 ″ includes a switching element QS5 that is turned on or off depending on a period, and a capacitor C1. The switching element QS5 and the capacitor C1 are between the gate of the Lo-side transistor Q2Y and the negative electrode of the first low voltage source V1. The gate terminal of the switching element QS5 is connected to the control terminal S1, and the switching element QS5 is composed of an N-channel MOS.

  The drain of the switching element QS5 is connected to the gate of the Lo-side transistor Q2Y. Furthermore, the gate of the Lo-side transistor Q2Y is connected to the external terminal of the output control signal IN3.

  In the scan driver IC 16Y according to the third embodiment, when the switching element QS5 is turned on by the signal from the control signal terminal S1 from the outside, and the control signal IN3 is also transmitted to the capacitor C1, the action of the capacitor C1 The voltage applied between the gate and the source is lower than the original voltage of the control signal IN3. As a result, the drive capability of the Lo-side transistor Q2Y decreases. Matching this timing when the Lo-side transistor Q2Y is turned on slows down the speed at which the Lo-side transistor QY2 is turned on. As a result, the change rate (response speed) of the output voltage of the Lo-side transistor QY2 can be reduced, and the peak of current that occurs when the Lo-side transistor QY2 is turned on can be suppressed. In FIG. 14, the Hi-side transistor Q1Y and the Lo-side transistor Q2Y are CMOS. However, these may be bipolar or IGBT.

  Since the initialization pulse generator 2Y and the sustaining pulse generator 3Y included in the scan electrode circuit 10 of the PDP according to the third embodiment of the present invention are the same as those in the first embodiment, the description will be given. Omitted.

  FIG. 15 is an example of a driving timing chart in the scan driver IC 16Y according to the third embodiment of the present invention. A chart of signals from the external control terminal S1 is also shown. In FIG. 15 as well, “VGS (B)” indicates the gate-source voltage at point B in FIG.

  In the drive timing chart shown in FIG. 15, the drive capability of the Lo-side transistor Q2Y decreases due to the action of the capacitor C1. As a result, the output voltage VOUT of the push-pull output circuit also falls gently from H to L. As a result, the peak (sharpness) is suppressed in the current IOUT flowing through the push-pull output circuit to the ground.

  In the scan pulse generator 1Y (scan driver IC 16Y) according to the third embodiment of the present invention, the switch circuit 18 ″ is connected to the gate of the Lo-side transistor Q2Y, and the output of the scan driver is ALL-H (all high). The control signal IN3 is transmitted to the capacitor C1 only in the forced mode in which switching from ALL to ALL-L (all low) is performed at once. However, a switch circuit 18 ″ may be provided at the gate of the Hi-side transistor Q1Y. . For example, as in the scan driver IC 17Y shown in FIG. 16, a switch circuit 18 ″ including a capacitor C1 and a switching element QS6 is connected to the gate of the Hi-side transistor Q1Y, and the output of the scan driver is ALL-L (all-low ) To ALL-H (all high) at the same time, the circuit setting may be such that the capacitor C1 is used in the forced mode.

  Further, FIG. 17 is a drive timing chart example when the gate-source voltage VGS of the Hi-side transistor Q1Y gradually falls from H to L in the scan driver IC 17Y shown in FIG. In FIG. 17, “C” indicates the potential at point C in FIG. 16, and “VGS (A)” indicates the gate-source voltage at point A in FIG. Here, comparing FIG. 8 and FIG. 17 (showing an example of a driving timing chart related to the conventional scan driver IC 13Y), the push-pull output circuit shown in FIG. 13 flows to the ground as in the driving timing chart shown in FIG. It can be seen that the peak (sharpness) can be suppressed in the current IOUT.

  INDUSTRIAL APPLICABILITY The present invention is useful for a plasma display driving apparatus that requires high definition and a variety of gradation display or low power consumption.

1 is an equivalent circuit diagram showing a schematic circuit configuration of a scan electrode drive circuit of a PDP according to a first embodiment of the present invention. FIG. 2 is a detailed circuit diagram of a scan driver IC in the scan electrode driving circuit shown in FIG. 1. It is a figure which shows the sequence of each signal of one subfield in the scanning electrode drive circuit shown in FIG. FIG. 19 is an example of a driving timing chart in the conventional scan driver IC shown in FIG. 18. FIG. 3 is an example of a driving timing chart in the scan driver IC according to the first embodiment of the present invention. FIG. 6 is a circuit diagram of another configuration example of the scan driver IC according to the first embodiment of the present invention. FIG. 7 is a diagram showing a sequence of signals in one subfield in the scan electrode driving circuit according to the first embodiment in which the scan driver IC shown in FIG. 6 is incorporated. FIG. 19 is a drive timing chart example when the gate-source voltage of the Hi-side transistor sharply falls from H to L in the conventional scan driver IC shown in FIG. 7 is an example of a driving timing chart when the gate-source voltage of the Hi-side transistor gently falls from H to L in the scan driver IC shown in FIG. 6. FIG. 6 is a detailed circuit diagram of a scan driver IC included in a scan electrode circuit of a PDP according to a second embodiment of the present invention. It is an example of a drive timing chart in the scan driver IC according to the second embodiment of the present invention. FIG. 10 is a circuit diagram of another configuration example of the scan driver IC according to the second embodiment of the present invention. 13 is a drive timing chart example when the gate-source voltage of the Hi-side transistor Q1Y gently falls from H to L in the scan driver IC shown in FIG. It is a detailed circuit diagram of a scan driver IC included in the scan electrode circuit of the PDP according to the third embodiment of the present invention. It is an example of a drive timing chart in the scan driver IC according to the third embodiment of the present invention. FIG. 10 is a circuit diagram of another configuration example of the scan driver IC according to the third embodiment of the present invention. 17 is an example of a driving timing chart when the gate-source voltage of the Hi-side transistor gently falls from H to L in the scan driver IC shown in FIG. 16. It is a detailed circuit diagram of a scan driver IC in a conventional scan electrode drive circuit.

Explanation of symbols

14 level shift circuit,
18, 18 ', 18 "switching element section,
1Y scanning pulse generator,
2Y initialization pulse generator,
3Y sustain pulse generator,
4Y recovery circuit,
11Y, 12Y, 13Y, 14Y, 15Y, 16Y, 17Y Scan driver IC,
Q1Y Hi side transistor,
Q2Y Lo side transistor,
Q7Y Hi side sustain switch element,
Q8Y Lo side sustain switch element,
QR1 Hi side ramp waveform generator,
QR2 Lo side ramp waveform generator,
QS1, QS2 switching element,
R1 resistance,
D1 diode,
C1 capacitor,
VOUT output voltage,
IOUT output current,
S1 Switching switching element control terminal.

Claims (11)

A scan pulse generator included in a plasma display panel scan electrode drive circuit having a plurality of output transistors,
A scan pulse generator, further comprising a switch circuit that adjusts a gate-source voltage of the output transistor to switch a response speed of an output from the output transistor.   2. The switch circuit according to claim 1, wherein the response speed of the output from the output transistor is temporarily reduced by temporarily relaxing the rise or fall of the gate-source voltage of the output transistor. The scanning pulse generator described. The second switching element circuit includes a first resistor;
3. The scan pulse generator according to claim 2, wherein the first resistor is used to temporarily moderate the rise or fall of the gate-source voltage of the output transistor. The second switching element circuit includes a first capacitor;
3. The scan pulse generator according to claim 2, wherein the first capacitor is used to temporarily moderate the rise or fall of the gate-source voltage of the output transistor.   The switch circuit temporarily reduces a response speed of an output from the output transistor by temporarily narrowing a range of increase or decrease of the gate-source voltage of the output transistor. The scanning pulse generator according to 1. The third switching element circuit includes a first diode;
6. The scan pulse generator according to claim 5, wherein the first diode is used to temporarily narrow the range of increase or decrease of the gate-source voltage of the output transistor.   A plasma display panel scan electrode drive circuit including the scan pulse generator according to claim 1.   A display device on which the plasma display panel scan electrode driving circuit according to claim 7 is mounted. A method of driving a scan electrode of a plasma display panel,
A driving method comprising: adjusting a gate-source voltage and switching a response speed of an output from an output transistor in a plurality of output transistors included in a scan pulse generation unit included in a scan electrode driving circuit included in a plasma display panel.   10. The driving method according to claim 9, wherein the response speed of the output from the output transistor is temporarily reduced by temporarily relaxing the rise or fall of the gate-source voltage of the output transistor. .   The drive according to claim 9, wherein a response speed of an output from the output transistor is temporarily reduced by temporarily narrowing a range of increase or decrease of the gate-source voltage of the output transistor. Method.

Images