KR20020088768A - Driving Circuit for AC-type Plasma Display Panel - Google Patents

Abstract

PURPOSE: A driving circuit of an AC type plasma display panel is provided to prevent a lowering effect of driving efficiency due to heat when a driving circuit using a ramp wave driving method performs a switching operation. CONSTITUTION: A Y driving circuit(300) is formed by a scan/sustain pulse generation circuits(P1 to PM) of M number corresponding to the number of Y electrodes(Y1 to YM) and an initialization pulse generation circuit(310). The initialization pulse generation circuit(310) is formed with an inductor(L1), a diode(D1), the third control switch(Q6), and the fourth control switch(Q7). An anode of the diode(D1) is connected with the inductor(L1). A ramp wave generation circuit(311) is used for generating a ramp wave by using anti-resonance operations of panel capacitors(CP1 to CPM) and the inductor(L1).

Description

Driving Circuit for AC Plasma Display Panel {Driving Circuit for AC-type Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a plasma display panel (PDP). In particular, an AC type plasma display panel capable of preventing a reduction in driving efficiency due to heat generation during a switching operation in a driving circuit according to a lamp wave driving method. For the driving circuit of.

In general, a plasma display panel (hereinafter referred to as a 'PDP') is a light emitting device that displays an image by exciting a phosphor formed in a discharge cell, which is a stock exchange because of its simple manufacturing process and its thin and large screen. In recent years, the use of video display devices used in bulletin boards, video conference displays, and large-screen wall-mounted TVs has been increasing.

1 is a block diagram schematically showing the configuration of a conventional AC PDP apparatus.

In FIG. 1, reference numeral 10 denotes M scan / hold electrodes Y _{1 to} Y _M (hereinafter referred to as 'Y electrodes') and sustain electrodes X _{1 to} X _M (hereinafter referred to as “X electrodes”). The PDPs are arranged in parallel with each other and N address electrodes A _{1 to} A _N are orthogonally arranged with a predetermined space therebetween with the Y electrodes Y _{1 to} Y _M and the X electrodes X _{1 to} X _M. It's a panel. And is also in the X electrodes (X ₁ ~X _M) is the common sustain electrodes (X ') X electrodes (X ₁ ~X _M) are parallel-connected in the first configuration through.

In FIG. 1, the panel 10 includes R (Red) and G (at each intersection of the Y electrodes Y _{1 to} Y _M , the X electrodes X _{1 to} X _M , and the address electrodes A _{1 to} A _N. Discharge cells S, which are divided into Green) and B (Blue) cells, are formed, and the discharge cells S display an image of M × N resolution in the form of a matrix.

In FIG. 1, reference numeral 20 denotes a scan / hold electrode driver provided with a drive circuit (hereinafter referred to as a “Y drive circuit”) connected to the Y electrodes Y _{1 to} Y _M to supply scan / hold pulses. 30 is a sustain electrode driver connected to the X electrodes X _{1 to} X _M through a common sustain electrode X 'and provided with a driving circuit (hereinafter, referred to as an' X driving circuit ') to supply a sustain pulse. Reference numeral 40 is an address electrode driver for selectively supplying write pulses to the discharge cells S through the address electrodes A _{1 to} A _N before the sustain discharge (oil dielectric discharge) is performed.

In FIG. 1, reference numeral 50 denotes the scan / sustain electrode driver to control an output of the input image signal IMAGE based on an external input signal CLK, horizontal sync signal HS, and vertical sync signal VS. 20, a control unit for controlling the operation of the sustain electrode driver 30 and the address electrode driver 40. FIG.

Hereinafter, a driving method of a conventional AC PDP device having the configuration of FIG. 1 will be described with reference to FIG. 2. In the following, detailed description of parts not relevant to the gist of the present invention will be omitted.

First, in the case of the AC PDP, an ADS (Addressing Display Separated) method of dividing and driving one frame into a plurality of subfields is mainly used according to the gray level to be implemented. When each subfield is subdivided, it is divided into a reset section, an address section, a sustain section, and an erasing section as shown in FIG. To implement, one frame consists of eight or more subfields.

In FIG. 2, the reset section A generates a wall charge in all the discharge cells S of the panel 10 after the sustain discharge of the previous subfield is made and then erases it again. As a section for initializing the wall charges in the discharge cell S, as shown in FIG. 2, an initializing pulse in the form of a rising ramp wave of + V _R voltage is supplied to all Y electrodes Y ₁ to Y _M. In the discharge cell S in which the sustain discharge occurred in the previous subfield, an initializing discharge in which the discharge current flows from the Y electrodes Y ₁ to Y _M to the address electrodes A _{1 to} A _N occurs.

In FIG. 2, the address section B is a section in which image discharge of the image data is selectively performed, that is, address discharge is performed on each discharge cell S after the reset section A, and the sustain section C is the above-mentioned. A section in which image display is performed by repeatedly performing sustain discharge (oil-dielectric discharge) with respect to the discharge cell S in which the write discharge has occurred in the address section B. The number of discharges in each subfield is weighted according to the number of gray scales to be displayed. do.

In FIG. 2, the erasing section D is sustained by applying an erase pulse in the form of a falling ramp wave of a -V _S voltage through the common holding electrode X 'connected in parallel to all the X electrodes X _{1 to} X _M. It is a section for stopping the discharge with respect to the discharge cell S which had discharged.

3A and 3B are circuit diagrams showing the internal structure of a conventional PDP driving circuit to which the driving method of FIG. 2 is applied, which is a Y driving circuit (FIG. 3A) and an X driving circuit described in Japanese Patent Laid-Open No. 11-133914. The circuit configuration of Fig. 3B is shown.

That is, FIG. 3A illustrates a Y driving circuit 100 provided in the scan / sustain electrode driver 20 of FIG. 1, which includes a plurality of scan / sustain pulse generating circuits P ₁ to P _M and an initializing pulse generating circuit ( 110 is provided. The Y driving circuit 100 and the X driving circuit to be described later will include a plurality of control switches including a metal-oxide semiconductor field-effect transistor (MOSFET) and an anti-parallel diode.

In FIG. 3A, the scan / sustain pulse generation circuits P ₁ to P _M are each of M first control switches Q _H1 to Q _HM having drains connected to an output terminal a of the initialization pulse generation circuit 110. And M second control switches Q _L1 to Q _LM having a drain connected to a source of the first control switches Q _H1 to Q _HM and a source connected to an operating power supply having a voltage of -V _S. It is composed.

In addition, the scan / hold pulse generating circuits P ₁ to P _M are connected to a source of the second control switches Q _L1 to Q _LM , and thus constitute a well-known push pull circuit. The connecting nodes of the first control switches Q _H1 to Q _HM and the second control switches Q _L1 to Q _LM are connected to the Y electrodes Y ₁ to Y _M of the panel 10 of FIG. 1, respectively. do. In FIG. 3A, reference numerals C _P1 to C _PM denote capacitive components of the panel 10, that is, panel capacitors.

In FIG. 3A, the initialization pulse generating circuit 110 includes a third control switch Q1 having a drain connected to an operating power supply having a voltage of + V _R , and a resistor having one end connected to a gate of the third control switch Q1. R1), a capacitor C1 connected between the gate and the drain of the third control switch Q1, and a fourth control switch having a drain connected to the source of the third control switch Q1 and grounded. It is comprised with Q2).

In addition, in FIG. 3A, the third control switch Q1, the resistor R1, and the capacitor C1 form a ramp wave generation circuit 111 that generates a linear ramp wave pulse in the reset section A of FIG. 2. do. The ramp wave generating circuit 111 uses a general Miller integrating circuit.

Hereinafter, an operation of the Y driving circuit 100 having the configuration of FIG. 3A will be described with reference to FIG. 2.

First, the first and fourth control switches Q _H1 to Q _HM and Q2 of FIG. 3A are turned on so that the voltages applied to the Y electrodes Y ₁ to Y _M are 0V. When the control switches Q _H1 to Q _HM and Q1 are driven on, the operating path of + V _R- > third control switch Q1-> current path of the first control switch Q _H1 to Q _HM Through the Y-Y (Y ₁ ~ Y _M ) through the initialization pulse of the ramp wave form shown in FIG. Therefore, in the discharge cell S in which the sustain discharge occurred in the previous subfield, an initializing discharge in which a discharge current flows from the Y electrodes Y ₁ to Y _M to the address electrodes A _{1 to} A _N occurs.

At this time, the initialization pulse is in the form of a ramp wave rising linearly according to the switching operation of the ramp wave generation circuit 111 of FIG. That is, as the switching operation of the third control switch Q1 is performed in the active region instead of the saturation region in the ramp wave generating circuit 111, the current flowing through the third control switch Q1 reaches the saturation region. It gradually increases until, the reset pulse supplied to all the Y electrodes (Y ₁ ~ Y _M ) has a ramp wave form that increases linearly to the voltage + V _R.

3A, the Y driving circuit 100 of FIG. 3A has a sustain section C in which sustain discharge is performed on an address section B in which image data is written and discharged, and a discharge cell S in which write discharge is performed. ), Image display for one subfield is performed. Detailed description thereof will be omitted.

3B illustrates an X driving circuit 200 provided in the sustain electrode driver 30 of FIG. 1, which includes a sustain pulse generator circuit 210 and an erase pulse generator circuit 220. The pulse generator circuit 220 has the same circuit configuration as the ramp wave generator circuit 111 of FIG. 3A.

In FIG. 3B, the sustain pulse generating circuit 210 has a source connected to a first control switch Q3 having a drain grounded, an operating power supply having a voltage of -V _S , and a drain thereof at a source of the first control switch Q3. It is comprised including this connected 2nd control switch Q4. The connection nodes of the first and second control switches Q3 and Q4 are connected to all the X electrodes X ₁ to X _M , respectively, through the common holding electrode X '. In FIG. 3A, reference numerals C _P1 to C _PM denote capacitive components, that is, panel capacitors, of the panel 10 of FIG. 1.

In FIG. 3B, the erase pulse generation circuit 220 includes a third control switch Q5 having a source connected to an operating power supply having a voltage of -V _S , and a drain connected to the common sustain electrode X ′, and the third control switch. A resistor R2 connected to the gate of Q5 and a capacitor C2 connected between the gate and the drain of the third control switch Q5 are configured.

Hereinafter, an operation of the X driving circuit 200 having the configuration of FIG. 3B will be described with reference to FIG. 2.

First, only the first control switch Q3 is turned on in the reset section A and the address section B of FIG. 2 so that a voltage of 0 V is continuously applied to all the X electrodes X ₁ to X _M. Thereafter, in the sustain period C of FIG. 2, the second control switch Q4 in the sustain pulse generating circuit 210 of FIG. 3B periodically repeats the on / off driving according to a predetermined control signal, and all the X electrodes X ₁ to X _M ) is periodically supplied with a sustain pulse of the -V _S voltage as shown in FIG. 2. In this case, the Y driving circuit 100 of FIG. 3A and the X driving circuit 200 of FIG. 3B supply alternating sustain pulses to the panel 10 of FIG. 1, and gray scale display of the display image is performed.

When the first control switch Q3 in the sustain pulse generation circuit 210 and the third control switch Q5 in the erase pulse generation circuit 220 of FIG. 3B are turned on after reaching the erase period D of FIG. 2, X electrodes (X ₁ to X _M )-> common holding electrode (X ')-> third control switch (Q5)->-V _S The current path of the operating power is formed, whereby all X electrodes (X ₁ to X _M ) is supplied with a ramp wave pulse (erasing pulse) that decreases linearly from 0V to -V _S voltage to completely stop the discharge operation of the discharge cell S having sustained discharge.

That is, the conventional PDP driving circuit described with reference to FIGS. 3A and 3B supplies a ramp wave pulse (initialization pulse / erase pulse) rising / falling linearly to change the discharge current in the PDP device, and to change the electrode (Y electrode, X electrode). In order to supply stable ramp wave pulses to the panel 10 of FIG.

However, the above-described conventional PDP driving circuit uses a Miller integrator circuit having a capacitor inserted into the initialization pulse generating circuit 110 of FIG. 3A and the erasing pulse generating circuit 220 of FIG. There was a problem. This is because the switching operation of the control switches Q1 and Q5 in the Miller integrating circuit is performed in the active region of the field effect transistor. In addition, when the heat generation amount of the PDP device becomes high, this acts as a main cause of lowering the driving efficiency of the PDP, and a solution for this is required.

Accordingly, the present invention has been made in view of the above circumstances, and provides a driving circuit of an AC plasma display panel which is capable of preventing a reduction in driving efficiency due to heat generation during a switching operation in a driving circuit according to a lamp wave driving method. There is a purpose.

1 is a block diagram schematically showing the configuration of a conventional AC PDP apparatus.

FIG. 2 is a voltage waveform diagram illustrating a driving method of a conventional AC PDP device having the configuration of FIG. 1. FIG.

3A and 3B are circuit diagrams illustrating an internal configuration of a conventional PDP driving circuit to which the driving method of FIG. 2 is applied.

4 is a block diagram schematically showing the configuration of an AC-type PDP apparatus according to the present invention.

5 is a voltage waveform diagram illustrating a driving method of an AC-type PDP device according to the present invention;

6A and 6B are circuit diagrams illustrating an internal configuration of a PDP driving circuit according to the present invention to which the driving method of FIG. 5 is applied.

*** Explanation of symbols for the main parts of the drawing ***

10: panel, 20, 60: scan / hold electrode driver,

30, 70: sustain electrode driver, 40: address electrode driver,

50: control unit, 100, 300: X driving circuit,

200, 400: Y driving circuit, 110, 310: Initialization pulse generating circuit,

111, 311: ramp wave generator circuit, 210: sustain pulse generator circuit,

220, 410: erase pulse generating circuit, Y ₁ ~ Y _M : scanning / holding electrode (Y electrode),

X _{1 to} X _M : sustain electrode (X electrode), P ₁ to P _M : scan / hold pulse generating circuit,

Q _H1 ~ Q _HM , Q _L1 ~ Q _LM , Q1 ~ Q8: Control switch, C1, C2: Capacitor,

L1, L2: inductor, D1, D2: diode.

In the driving circuit of the AC plasma display panel according to the present invention for achieving the above object, M Y electrodes and X electrodes are arranged in parallel with each other, and N address electrodes are disposed between the Y electrode and X electrode in a predetermined space. And a panel arranged orthogonally, and connected between the panel and the plurality of operating power supplies to generate a driving pulse for each section consisting of a reset section, an address section, a sustain section, and an erase section, and generate the reset section and / or the erase section. A driving circuit of an AC plasma display panel, wherein a driving pulse is a ramp wave driving pulse, wherein the driving circuit includes an inductor for forming an anti-resonance circuit with the panel capacitor of the panel, wherein the reset section and / or the erase section are provided. The drive pulse is characterized in that configured to be supplied through the anti-resonant circuit.

In addition, a driving circuit of an AC plasma display panel according to the present invention includes a panel in which M Y electrodes and X electrodes are arranged in parallel with each other, and N address electrodes are orthogonally arranged with a predetermined space therebetween. And a driving pulse connected to the panel and a plurality of operating power supplies to generate a driving pulse for each section including a reset section, an address section, a sustain section, and an erase section, wherein the drive pulse of the reset section and / or the erase section is a ramp wave. In a driving circuit of an AC plasma display panel which is a driving pulse, an initialization pulse coupled between a first operating power supply, a ground terminal, and the Y electrode to supply a ramp wave pulse that gradually rises to the Y electrode in the reset section. A generation circuit, coupled between an output terminal of the initialization pulse generation circuit and the Y electrode and a second operating power source; It provides a current path of a pulse pulse and a scan / hold pulse generating circuit for supplying a predetermined scan pulse and a sustain pulse to the Y electrode, wherein the initialization pulse generating circuit forms a panel capacitor and an anti-resonance circuit of the panel. Characterized in that it comprises an inductor for.

In addition, a driving circuit of an AC plasma display panel according to the present invention includes a panel in which M Y electrodes and X electrodes are arranged in parallel with each other, and N address electrodes are orthogonally arranged with a predetermined space therebetween. And a driving pulse connected to the panel and a plurality of operating power supplies to generate a driving pulse for each section including a reset section, an address section, a sustain section, and an erase section, wherein the drive pulse of the reset section and / or the erase section is a ramp wave. A driving circuit of an AC plasma display panel, which is a driving pulse, comprising: an erasing pulse generating circuit coupled between a first operating power supply and the X electrode to supply a ramp wave pulse that gradually descends to the X electrode in the erasing section; And coupled to the erase pulse generator circuit, the X electrode, the ground terminal, and a second operating power supply to the X electrode. And a sustain pulse generating circuit for supplying a pulse, wherein the erase pulse generating circuit includes an inductor for forming an anti-resonance circuit with a panel capacitor of the panel.

Hereinafter, embodiments of the present invention will be described with reference to the drawings of FIGS. 4 to 6A and 6B.

4 and 6A and 6B, the same components as those shown in FIGS. 1 and 3A and 3B are denoted by the same reference numerals, and detailed description thereof will be omitted. 6A and 6B may use an insulated gate bipolar transistor (IGBT) as well as a field effect transistor.

FIG. 4 is a block diagram schematically showing the configuration of an AC PDP device according to the present invention. In FIG. 4, reference numeral 60 denotes a Y drive circuit connected to Y electrodes Y ₁ to Y _M to supply scan / maintenance pulses. A scan / hold electrode driver is provided with a furnace, and 70 is a sustain electrode driver provided with an X drive circuit connected to the X electrodes X ₁ to X _M through the common sustain electrode X 'to supply a sustain pulse. A detailed description of the Y driving circuit and the X driving circuit will be described later.

FIG. 5 is a voltage waveform diagram illustrating a driving method of an AC PDP device according to the present invention. The voltage waveform shown in FIG. 5 includes a reset section A and an address section B as shown in FIG. According to the ADS driving method which divides and drives the sustain section (C) and the erase section (D).

Hereinafter, operations of each section constituting one subfield of FIG. 5 will be briefly described. In addition, the initialization pulse and the erase pulse shown in the reset section A and the erase section D of FIG. 5, respectively, are not general ramp wave pulses such as the linear ramp wave pulse of FIG. 2 but gradually increase / decrease to a predetermined voltage. Since the voltage waveform has a voltage waveform, the initialization pulse and the erase pulse of Fig. 5 are also referred to as ramp wave pulses for convenience of description.

That is, in FIG. 5, the reset section A is a section for initializing wall charges in each discharge cell S after the sustain section C and the erase section D of the previous subfield are finished. Y electrode in a ramp wave pulse (initialization pulse), all the Y electrodes (Y ₁ ~ Y _M) to the discharge cells (S), a sustain discharge occurred in the previous sub-field is supplied, which gradually rises to V _R voltage (Y ₁ ~ Y Initialization discharge occurs between _M ) and the address electrodes A ₁ -A _N.

In FIG. 5, the address section B is a section in which write discharge (address discharge) is selectively performed with respect to the discharge cell S in which image data is displayed. In this section, the write pulse of the + V _W voltage is the address electrode A. FIG. ₁ to A _N ), and a scanning pulse of a -V _S voltage is sequentially supplied from the first Y electrode Y ₁ to the M th Y electrode Y _M to select the selected address electrode A ₁ to A _M. ) And the address discharge (address discharge) occurs between the Y electrodes Y ₁ to Y _M.

In FIG. 5, the sustain period C adjusts the number of discharges of the discharge cells S in which the write discharge has occurred in the address period B, thereby increasing the luminance of light emitted from each subfield and thereby displaying the gray scale display of the display image. In this section, as shown in FIG. 5, an alternating sustain pulse having a voltage of -V _S is supplied to the common holding electrode X 'and all the Y electrodes Y ₁ to Y _M to supply the Y electrodes Y ₁ to. The alternating sustain discharge (oil fat discharge) occurs between Y _M ) and the X electrodes (X ₁ to X _M ).

In FIG. 5, the erasing section D is a section for completely stopping the discharging operation of the discharge cell S having sustained discharge in the sustain section C. In this section, the ramp wave pulse is lowered to a voltage of -V _S. The erasing pulse is supplied to the common holding electrode X 'to cause the erase discharge to occur in the discharge cell S in which the sustain discharge occurred.

Hereinafter, a PDP driving circuit (Y driving circuit and X driving circuit) to which the ramp wave driving method described in FIG. 5 is applied will be described with reference to FIGS. 6A and 6B.

That is, FIG. 6A illustrates the Y driving circuit 300 provided in the scan / hold electrode driver 60 of FIG. 4, which is M scan / hold pulses provided corresponding to the number of Y electrodes Y ₁ to Y _M. Generator circuits P ₁ to P _M and an initialization pulse generator 310 are provided.

In FIG. 6A, one end of the initialization pulse generating circuit 310 is + An inductor L1 connected to an operating voltage of a voltage, a diode D1 having an anode connected to the other end of the inductor L1, and a third control switch Q6 having a drain connected to a cathode of the diode D1. And a fourth control switch Q7 whose drain is connected to the source of the third control switch Q6 and whose source is grounded. 3A, the output terminal a of the initialization pulse generating circuit 310 is coupled to the scan / sustain pulse generating circuits P ₁ to P _M.

In FIG. 6A, reference numeral 311 denotes a lamp wave generator circuit having the lamp wave generator circuit 111 described in FIG. 3A in another form, and the lamp wave generator circuit 311 includes panel capacitors C _P1 to C _PM and an inductor. The anti-resonance circuit using the anti-resonance operation of (L1) is used.

That is, in the ramp wave generation circuit 111 of FIG. 3A, the third control switch Q1 is used as an inverting amplifier, and a current limiting element, that is, a resistor R1 is connected to the input terminal (gate) thereof, A Miller capacitor, that is, a capacitor C1 is provided between the drain and the input terminal (gate) to operate as a current power source.

Accordingly, the voltage and current are applied to the third control switch Q1 in the reset section A in which the ramp wave pulse generated through the ramp wave generation circuit 111 of FIG. 3A charges the panel capacitors C _P1 to C _PM . The power consumption corresponding to the product of is achieved.

The power consumption increases in proportion to the size of the panel capacitors C _P1 to C _PM or the current amount and frequency of the ramp wave pulses generated by the Miller amplification operation. The power consumption of the third control switch Q1 varies depending on the size of the panel 10, but generally reaches about 3 to 6 W. FIG. Therefore, since the heat sink having a predetermined size or more is to be attached to the third control switch Q1, space constraints and heat generation constraints in the driving circuit configuration follow.

However, in the ramp wave generation circuit 311 of FIG. 6A according to the present invention, the ramp shown in the reset section A of FIG. 5 using the anti-resonant operation of the inductor L1 and the panel capacitors C _P1 to C _PM . Since a wave pulse (initialization pulse) is generated, the operating point of the third control switch Q6 of FIG. 6A is set in the saturation region, thereby preventing the above-described heat generation problem.

In addition, in the ramp wave generation circuit 311 of FIG. 6A, a stable ramp wave pulse is supplied to the panel 10 even when the discharge current is changed or the electrode float capacity is changed by the current continuity characteristic of the inductor L1 itself.

Hereinafter, the operation of the Y driving circuit 300 having the configuration of FIG. 6A will be described with reference to FIG. 5.

First, the first and fourth control switches Q _H1 to Q _HM and Q7 of FIG. 6A are turned on so that the voltages applied to all the Y electrodes Y ₁ to Y _M are 0V. 3 When the control switch (Q _H1 to Q _HM , Q6) is ON, To the reset section (A) of FIG. 5 on all Y electrodes (Y ₁ to Y _M ) through the current path of the operating power source-> third control switch (Q6)-> first control switch (Q _H1 to Q _HM ). The rising ramp wave pulse (initialization pulse) shown is supplied. Therefore, in the discharge cell S in which the sustain discharge occurred in the previous subfield, an initializing discharge occurs between the Y electrodes Y ₁ to Y _M and the address electrodes A _{1 to} A _N.

In addition, the initialization pulse of the voltage supplied to the Y electrodes (Y ₁ ~ Y _M ) in accordance with the anti-resonant operation of the inductor (L1) and panel capacitors (C _P1 ~ C _PM ) in the ramp wave generation circuit 311 of FIG. The level has a ramp wave shape that gradually increases to the + V _R voltage.

Thereafter, in the address section B of FIG. 5, a writing pulse of + V _W voltage is selectively supplied to the address electrodes A ₁ to A _N through the address electrode driver 40 of FIG. 4, _and the second control of FIG. 6A is performed. When the switches Q _L1 to Q _LM are sequentially driven on and the scan pulse is supplied to the Y electrodes Y ₁ to Y _M , the selected address electrodes A ₁ to A _M and Y electrodes Y ₁ to Y _M Write discharges occur between them.

In the sustain period C of FIG. 5, the second pull control switch Q _L1 to Q _LM performs a push pull operation of repeating on / off driving, and the Y electrodes Y ₁ to Y _M Alternating sustain discharge occurs between the X electrodes X ₁ to X _M.

6B illustrates an X driving circuit 400 provided in the sustain electrode driver 70 of FIG. 4, which includes a sustain pulse generating circuit 210 and an erase pulse generating circuit 410. The pulse generating circuit 410 has the same circuit configuration as the ramp wave generating circuit 311 of FIG. 6A.

In FIG. 6B, the erase pulse generation circuit 410 includes an inductor L2 having one end connected to the common sustain electrode X ', a diode D2 having an anode connected to the other end of the inductor L2, and the diode. A drain is connected to the cathode of (D2), And a third control switch Q8 having a source connected to the operating power source of the voltage.

The circuit configuration shown in the ramp wave generating circuit 311 of FIG. 6A and the erasing pulse generating circuit 410 of FIG. 6B shows an example according to the present invention, and as shown in FIGS. 6A and 6B, an inductor ( It is not necessary to connect L1 and L2, diodes D1 and D2, and control switches Q6 and Q8 in this order, and anti-resonant operation is performed between the inductors L1 and L2 and the panel capacitors C _P1 to C _PM . It is possible to configure in other forms.

For example, in FIGS. 6A and 6B, the ramp wave generator 311 and the erase pulse generator 410 are connected in the order of the diodes D1 and D2, the inductors L1 and L2, and the control switches Q6 and Q8. Alternatively, it may be preferable to replace the diodes (D1, D2) used for the reverse current prevention with a control switch (not shown).

In this case, the control switch replacing the diodes D1 and D2 functions as a switching element that blocks the reverse current flowing in the direction of the operating power (+ V _R ) from the panel capacitors C _P1 to C _{PM in} FIG. 6A, respectively. In the case of Figure 6b operating power (- It functions as a switching element that blocks the reverse current flowing from the circuit board to the panel capacitors (C _P1 to C _PM ).

Hereinafter, an operation of the X driving circuit 400 having the configuration of FIG. 6B will be described with reference to FIG. 2.

First, the operation of the X driving circuit 400 in the reset section A, the address section B, and the sustain section C of FIG. 5 is performed in the same manner as the X driving circuit 200 of FIG. 3B. Will be omitted.

Subsequently, when the first control switch Q3 in the sustain pulse generation circuit 210 and the third control switch Q8 in the erase pulse generation circuit 410 are turned on in the erase period D of FIG. 5, FIG. 6b X electrode (X ₁ ~ X _M )-> Common holding electrode (X ')-> Inductor (L2)-> Diode (D2)-> Third control switch (Q8)->- The current path of the operating power is formed and gradually decreases from 0 V to -V _S voltage on all X electrodes (X ₁ to X _M ) according to the anti-resonant operation of the panel capacitors C _P1 to C _PM and the inductor L2. The ramp wave pulse (erase pulse) to be supplied is supplied to completely stop the discharge operation of the discharge cell S that has undergone the sustain discharge.

Therefore, according to the above-described embodiment, the PDP driving circuit is used to generate the ramp wave pulses (initializing pulse, erasing pulse) by using the anti-resonance circuit of the inductor and the panel capacitor when generating the initialization pulse of the Y driving circuit and the erasing pulse of the X driving circuit. It is possible to minimize the heat problem. In addition, since the current flowing through the inductor has a continuity when generating a ramp wave pulse, a stable ramp wave pulse can be supplied to the panel even when the discharge current or the electrode subcapacity changes.

As described above, according to the present invention, it is possible to prevent the deterioration of the driving efficiency of the PDP driving circuit by minimizing the heat generated by the switching operation when generating the ramp wave pulses such as the initialization pulse and the erasing pulse of the PDP driving circuit.

Claims (5)

M Y electrodes and X electrodes are arranged in parallel with each other, and N address electrodes have a panel orthogonally arranged with a predetermined space therebetween, and are connected between the panel and a plurality of operating power sources. In the driving circuit of the AC plasma display panel, the driving pulse for each section including a reset section, an address section, a sustain section, and an erase section is generated, and the drive pulse of the reset section and / or the erase section is a ramp wave driving pulse. The driving circuit includes an inductor for forming an anti-resonance circuit with the panel capacitor of the panel, and the driving pulse of the reset section and / or the erase section is configured to be supplied through the anti-resonance circuit. Display circuit drive circuit. M Y electrodes and X electrodes are arranged in parallel with each other, and N address electrodes have a panel orthogonally arranged with a predetermined space therebetween, and are connected between the panel and a plurality of operating power sources. In the driving circuit of the AC plasma display panel, the driving pulse for each section including a reset section, an address section, a sustain section, and an erase section is generated, and the drive pulse of the reset section and / or the erase section is a ramp wave driving pulse. An initialization pulse generation circuit coupled between a first operating power source and a ground terminal and the Y electrode for supplying a ramp wave pulse gradually rising to the Y electrode in the reset section; Generation between the output terminal of the initialization pulse generating circuit and the Y electrode and the second operating power supply to provide a current path of the ramp wave pulse and to generate a scan / hold pulse for supplying a predetermined scan pulse and a sustain pulse to the Y electrode. With a circuit, And the initialization pulse generating circuit comprises an inductor for forming a panel capacitor and an anti-resonance circuit of the panel. The method of claim 2, The initialization pulse generating circuit includes an inductor having one end connected to the first operating power source, A diode having an anode connected to the other end of the inductor, At least two control switches sequentially connected to the cathode of the diode are configured in series, And one of the output terminals of the control switch is an output terminal of the initialization pulse generating circuit. M Y electrodes and X electrodes are arranged in parallel with each other, and N address electrodes have a panel orthogonally arranged with a predetermined space therebetween, and are connected between the panel and a plurality of operating power sources. In the driving circuit of the AC plasma display panel, the driving pulse for each section including a reset section, an address section, a sustain section, and an erase section is generated, and the drive pulse of the reset section and / or the erase section is a ramp wave driving pulse. An erase pulse generation circuit coupled between a first operating power supply and the X electrode for supplying a ramp wave pulse that gradually descends to the X electrode in the erase period; A sustain pulse generator circuit coupled between the erase pulse generator circuit, the X electrode, a ground terminal, and a second operating power supply to supply a predetermined sustain pulse to the X electrode; And said erasing pulse generating circuit comprises an inductor for forming a panel capacitor and an anti-resonance circuit of said panel. The method of claim 4, wherein The erase pulse generation circuit may include an inductor having one end connected to the X electrode, A diode having an anode connected to the other end of the inductor, And at least one control switch sequentially connected in series between the diode of the diode and the first operating power supply.