JPH04137819A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize a Bi-CMOS circuit composed a bipolar transistor(TR) operated only at an active region by providing an output voltage compensation circuit and a means interrupting the base current of the bipolar TR on this integrated circuit. CONSTITUTION:A 1st current interrupting circuit 11 is inserted between the output node A of a CMOS inverter 3 and the base of an additional charging bipolar TR Q1, an output voltage compensation circuit 13 is inserted between the emitter of the TR Q1 and the output node A, and a 2nd base current interruption circuit 15 is inserted between a connection node B between MOS TRs M3, M4 and the base of a load discharge bipolar TR Q2. The supply of a base current is interrupted from the bipolar TRs Q1, Q2 before they are operated in the pseudo saturation region in the base current interrupting circuits 11, 15. Thus, since the bipolar TR is operated only at an active region, the Bi- CMOS circuit is realized at a high speed with high reliability.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit, and in particular to a semiconductor integrated circuit that combines CMo5 and bipolar transistors.
- Regarding the CMO5 circuit.

(Prior Art) In recent years, digital integrated circuits such as semiconductor memories and gate arrays have been used as a means of achieving high integration and high-speed operation. Bi-MO5 circuits with high integration density are widely used. Especially M
BiCMO3 circuits using CMOS transistors as OS transistors are attracting attention because of their excellent low power consumption characteristics.

FIG. 6 shows an example of the basic configuration of a buffer circuit made of Bi-CMo3.

This B1-CMOS buffer circuit includes a CMOS inverter 3, a charging circuit 5 for charging a load (not shown) connected to an output terminal 9 controlled by an output node A of this CMOS inverter 3, and a charge circuit 5 at the output terminal 9. It is composed of a discharge circuit 7 for discharging.

The input terminal 1 is connected to the respective gates of a CMOS inverter 3 and an N-channel MoS transistor M3, which are configured by commonly connecting the drain of a P-channel MOS transistor M1 and the drain of an N-channel MOS transistor M2.

The source of Mo8) transistor M1 of this CMOS inverter 3 is connected to the high potential side power supply potential Vcc, and Mo3)
) The source of transistor M2 is at the low voltage side power supply potential Vss.
It is connected to the. The output node A of this CMOS inverter 3 is connected to the base of a load charging transistor Q1, which is a charging circuit 5. The collector of this transistor Q1 is connected to the power supply potential Vcc on the high potential side. In addition, the emitter of the transistor Q1 is connected to the low voltage side power supply potential Vss (npn for load discharge)
It is connected to the collector of transistor Q2 and to output terminal 9.

The drain of the N-channel MOS transistor M3 is connected to the output terminal 9, and the source is connected to the base of the load discharging npn transistor Q2 and the drain of the MOS transistor M4. The source of this MOS transistor M4 is connected to the power supply potential Vss on the low voltage side, and the gate is connected to the output node A. These transistors Q
2゜M3. A discharge circuit 7 is configured by M4.

An N-channel MOS transistor M3 connected between the output terminal 9 and the base of the load discharge npn transistor Q2.
is controlled by the input signal Vin of the controlled CMOS inverter 3 input to its gate. In other words, this MOS
The transistor M3 is a MOS transistor for turning on the transistor Q2, and serves to selectively short-circuit the collector and base of the transistor Q2 according to the input signal Vin of the CMOS inverter 3.

The base of transistor Q2 and the power supply potential Vss on the low potential side
N-channel M OS transistor M connected between
4 is controlled by the voltage at the output node A of the CMOS inverter 3 applied to its gate. In other words, this MOS transistor M4 is a transistor Q that selectively discharges the base charge accumulated in the load discharging npn transistor Q2 according to the output of the CMOS inverter 3.
This is the second off-drive MOS transistor.

When the input signal Vin input to the B1-CMOS bath circuit configured in this way changes from the "H" level to the "L" level, a channel is formed in the MOS transistor M1, and a channel is formed in the MOS transistor M2. is not formed, and the voltage at output node A is the same as that of MOS transistor M1.
It becomes Vcc through. As a result, the load charging NPN transistor Q1 of the charging circuit 5 is turned on. At this time, since the on-drive MOS transistor M3 is off and the off-drive MOS transistor M4 is on, the base charge accumulated in the load discharge npn transistor Q2 is discharged through the MO3I transistor 4. As a result,
The output signal Vout becomes "H" level.

Next, when the input signal Vin input to the B i -CMOS buffer circuit changes from the "L" level to the "H2" level, a channel is formed in the MOS transistor M2, and the MO
No channel is formed in the S transistor M1, and the voltage at the output node A is Vss through the MOS transistor M2.
Take. As a result, the load charging npn h transistor Q1 of the charging circuit 5 is turned off. At this time, MOS transistor M3 is turned on and MOS transistor M4 is turned off, so the charge accumulated in the load is transferred to MOS transistor M3.
．． It is discharged through bipolar transistor Q2. As a result, the output signal V out becomes "L" level.

FIG. 7 shows the static characteristics of an np/n bipolar transistor formed on a p-type substrate. That is, it is a diagram showing the relationship between the collector-emitter voltage, the collector current 1c, and the substrate current 1sub when the base current is kept constant in a bipolar transistor with a common emitter.

The region in which the collector current 1c flows can generally be divided into three regions: a saturation region, a pseudo-saturation region, and an active region.

The saturated region is the region indicated by (1) in the figure.

In this region, since the collector voltage is lower than the base voltage, both the emitter-base and base-collector regions are biased in the forward direction, and the bipolar transistor no longer operates normally. Furthermore, by forward biasing between the base and the collector, a parasitic PNP transistor consisting of the base, collector, and substrate operates, and a substrate current 1sub flows.

The pseudo-saturated region is the region indicated by (II) in the figure. In this region, the collector terminal voltage is higher than that of the base. However, near the junction between the base and collector, due to the current flowing through the collector and the voltage drop due to the collector resistance,
Since the base voltage is higher than the collector voltage, it becomes forward biased.

The active region is the region indicated by (DI) in the figure.

In this region, the voltage between the base and collector is between the terminal electrodes,
Both junction surfaces are biased in the opposite direction, and the bipolar transistor operates normally.

By the way, in the B1-CMOS buffer circuit, it is necessary to charge and discharge a large load capacitance at high speed, so a bipolar transistor Q is used.
1, it is necessary to flow a large current through Q2. Further, since the output signal V out changes in a range close to the full amplitude from voltage Vss to voltage Vcc, the collector-emitter voltage of the transistor also has a value approximately from voltage Vss to Vcc.

FIGS. 8(a) and 8(b) respectively show operating waveforms of the load charging npn bipolar transistor Q1 and the load discharging npn bipolar transistor Q2 during a transient response of the B1 CMOS buffer circuit. The same figure (a
), it can be seen that when the collector-emitter voltage VCR is around 1V, the collector current 1c passes through a pseudo-saturation region of around 10 mA. Further, as shown in FIG. 2B, the load discharging bipolar transistor Q2 also passes through a pseudo-saturation region where the collector-emitter voltage vcE is around 1V and the collector current 1c is around 10mA.

What should be noted here is that the substrate current 1sut> flows in the pseudo-saturation region (n). When a substrate current of 1 sub flows in a BiCMO8 circuit, the substrate voltage increases, so the threshold voltage of a field transistor formed for element isolation decreases, and the isolation characteristics deteriorate. This problem becomes more noticeable as the device becomes finer, resulting in a problem that the reliability of the circuit decreases.

In the pseudo-saturation region, compared to the active region, even if the same base current is passed, the collector current that can be extracted is smaller. That is, in the pseudo-saturation region, the current amplification factor becomes small, and a larger base current than during active region operation is required to extract the same collector current. As a result, the amount of charge stored in the base increases, so when turning off the bipolar transistor Q2, it takes time to extract the charge stored in the base, making high-speed operation difficult.

(Problems to be Solved by the Invention) As described above, in the conventional Bi-CMO5 circuit, the bipolar transistor operates in the pseudo-saturation region and the active region.

In the pseudo-saturation region, the parasitic transistor formed by the base, collector, and substrate operates, so the substrate current increases,
This caused a problem in that the reliability of the circuit decreased. Furthermore, in the pseudo-saturation region, the current amplification factor becomes small, so a large base current is required to obtain a predetermined collector current. As a result, there is a problem in that it takes time to draw out the base charge, making high-speed operation difficult.

The present invention has been made in consideration of the above circumstances, and its purpose is to provide a BiCMO8 circuit consisting of bipolar transistors that operate only in the active region.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a semiconductor integrated circuit of the present invention includes a CMOS gate circuit having at least one input terminal, and a collector connected to a first power supply potential. a first bipolar transistor whose base is connected to the output node of the cMOS gate and whose emitter is connected to an output terminal connected to a load; the base of the first bipolar transistor and the output node of the CMOS gate; and a first bipolar transistor that is controlled by the output node to cut off the base current of the first bipolar transistor before the voltage between the collector and emitter of the first bipolar transistor becomes equal to or less than a predetermined value. base current interrupting means; an output voltage compensation circuit provided between the output node of the CMOS gate and the emitter of the first bipolar transistor; a collector connected to the output terminal; a second bipolar transistor of the same type as the first bipolar transistor connected to a potential;
The CM is inserted between the base of the second bipolar transistor and the output terminal, and selectively shorts the base and collector of the second bipolar transistor.
a short-circuiting means for discharging, through the second bipolar transistor, the charge that has been charged in the load when the voltage at the output node of the OS gate has increased to the point where the first bipolar transistor is turned off; is inserted between the base of the second bipolar transistor and controlled by the output node of the CMOS gate, and before the voltage between the collector and emitter of the second bipolar transistor becomes equal to or less than a predetermined value; and a second base current cutoff means for cutting off the base current of the second bipolar transistor.

(Function) According to the semiconductor integrated circuit of the present invention, the voltage at the output node of the CMOS gate circuit increases, the base current is supplied to the first bipolar transistor, the collector current flows into the load, and the voltage between the collector and emitter increases. Even if the voltage difference becomes small, when the base voltage rises to a predetermined value, the first base current cutoff means provided between the base and the output node operates, and the base current stops flowing. It cannot go below the value. Therefore, by adjusting the operating voltage of the first base current cutoff means, the collector-emitter voltage can be maintained at a desired voltage or higher. As a result, the first bipolar transistor can be prevented from operating in the pseudo-saturation region. At this time, the first bipolar transistor cannot supply current to the load, but the output voltage compensation circuit connected between the output node of the CMOS gate circuit and the output terminal can supply current to the load, so the voltage at the output terminal is Increases to a predetermined value. Also,
The voltage at the output node of the CMOS gate circuit drops and the first
Even if the second bipolar transistor is turned off and the charge stored in the load is discharged through the second bipolar transistor, and the voltage difference between the collector and emitter becomes smaller, the voltage difference between the base and the output terminal becomes smaller. The second
The base current cutoff means operates and the base current stops flowing, so that it does not fall below a certain value. Therefore, like the first bipolar transistor, it is possible to prevent the first bipolar transistor from operating in the pseudo-saturation region. At this time, the second bipolar transistor cannot discharge the charge accumulated in the load, but the charge is transferred to the output voltage compensation circuit.

Since the discharge passes through the CMOS gate, the voltage at the output terminal drops to a predetermined value.

(Example) Examples will be described below with reference to the drawings.

FIG. 1 shows a BiCM OS according to the first embodiment of the present invention.
/< buffer circuit is shown. Note that portions corresponding to those in the conventional example in FIG. 6 are designated by the same reference numerals as in FIG. 6, and detailed description thereof will be omitted.

The B1-CMOS buffer circuit of this embodiment differs from the conventional one in that a first base current cutoff circuit 11 is inserted between the output node A of the CMOS inverter 3 and the base of the additional charging NPN bipolar transistor Q1. , an output voltage compensation circuit 13 is inserted between the emitter of bipolar transistor Q1 and output node A, and a connection node B between Mo8) transistor M3 and Mo3) transistor M4 is inserted.
This is because a second base current cutoff circuit 15 is inserted between the base of the NPN bipolar transistor Q2 for load discharge and the base of the NPN bipolar transistor Q2 for load discharging.

The first base current cutoff circuit 11 consists of an N-channel MOS transistor M5 whose gate is connected to the power supply potential Vcc on the high potential side, and the output voltage compensation circuit 13 consists of a resistor element R.
The second base current cutoff circuit 15 includes an N-channel MOS transistor M6 whose gate is connected to the output node A and a P-channel MOS transistor M7 whose gate is connected to the power supply potential Vss on the low potential side, which are connected in parallel. It has a similar configuration.

An input signal Vin that changes from the "H" level (Vcc) to the "L" level (Vss) as shown in FIG. 2(a) is input to the input terminal 1 of the B1-CMOS buffer circuit configured in this way. Then, the voltage VA at the output node A increases from Vss to Vcc.At this time, the MoS transistor M4 is turned on, so the MOS transistor M4 is turned on.
The voltage at the connection node B between the transistor M3 and the MOS1-transistor M4 becomes Vss. Further, since the gate voltage of the Mos transistor M7 is Vss, it is turned off, and the MOS transistor M7 is turned off.
Transistor M6 is turned on because its gate is connected to output node A.

As a result, the voltage at the connection node B' between the second base current cutoff circuit 15 and the bipolar transistor Q2 drops to VSS, so the bipolar transistor Q2 is turned off.

MOSl - transistor M5 and bipolar transistor Q
The voltage VA at the connection node A' with the base of MOS1 is
- The voltage difference between the gate and source of transistor M5 (between the gate and connection node A') drops to the threshold value VTN of MOS transistor M5, and rises until MoS transistor M5 is turned off. As a result, the voltage VA• at the connection node A' rises to VCCVTN (time t1). At this time, the output signal V out of the output terminal 9 is VCCVTN
V, becomes. However, VP is the forward rising voltage of the PN diode between the base and emitter of the transistor Q1.

When the MOS transistor M5 turns off, the collector current of the bipolar transistor Q1 stops increasing.

As a result, bipolar transistor Q1 does not enter the pseudo-saturation region and operates only in the active region.

The output signal V out after time t1 when the MOS transistor M5 is turned off is determined by the resistance element R.

The resistance element R used here is such that when the voltage at the output node A becomes Vcc, the voltage at the output terminal 9 rises to Vcc, and when the voltage at the output node A becomes Vss, the voltage at the output terminal increases. It has a characteristic that the voltage drops to Vss.

The specific configuration will be described later. Therefore, even if bipolar transistor Q1 is turned off, the output signal V out remains V
cc, and a predetermined voltage is applied to the load.

Next, the above will be explained using specific numerical values.

Collector resistance Re is 50Ω, collector current 1c is 10m
A, and the base-emitter voltage VBE at that time is I
Assume that V. Further, the voltage drop caused by the base current and base resistance is ignored because it is smaller than the voltage drop caused by the collector current and collector resistance.

Therefore, the voltage between the collector and base junctions BC, +
The collector voltage VcP when is at zero bias is: Vcg-Vap VBc, 1+Ic-Rc-1,5r
It's V-co. From this, the boundary between the pseudo-saturation region and the active region is V
It can be said that cE is 1.5V. Because the collector
This is because the transistor enters a pseudo-saturation region when a forward bias voltage is applied across the base junction.

Next, set the threshold voltage of MOS transistor M5 to 1■,
Forward rising voltage VF of bipolar transistor Q1
When is set to 0.5V, the output signal Vout when the bipolar transistor Q1 is cut off becomes Vout-VcC-VTN-Vp-Vcc-1,5 [V].

Therefore, the collector voltage VcE′ is VCE −V
cc-Vout -Vcc -(Vcc-1,5) -1,5 [V], and the collector-emitter voltage vcE just before
is equal to Therefore, an MO with a threshold voltage of 1V
By inserting the S transistor M5, the bipolar transistor Q1 can be turned off immediately before entering the pseudo saturation region. In this way, bipolar transistor Q1
The bipolar transistor Q1 can be prevented from entering the pseudo-saturation region by connecting a MOS transistor M5 having appropriate electrical characteristics depending on the electrical characteristics such as the forward rising voltage V2.

Next, the second
As shown in Figure (b), when the input signal Vin that changes from the "L" level to the "H" level is input, the voltage VA at the output node A drops from Vcc to Vss. Therefore, MO3I-transistor M connected to output node A
5 is turned off, and as a result, the voltage at the connection node A' becomes V
ss, and the bipolar transistor Q1 is turned off.

Also, MOS transistor M4. Both M6 are turned off because their gates are connected to output node A.

At this time, transistor M3 is turned on, so voltage v8 at connection node B rises, and voltage Vss is applied to the gate of P-channel MOS transistor M7, which is connected to connection node B. - voltage increases.

Here, the threshold value of the P-channel MOS transistor M7 connected to the connection node B is vtp (<0), and the voltage of the connection node B' is the patent connection node B' and the gate of the P-channel MO5I-transistor M7. The voltage difference between
VB until the threshold value Vtp of oS transistor M7 is reached.
- increases (VB・-V s s + l VTPI
) o When the voltage difference between the gate of the MOS transistor M7 and the connection note B- is higher than the threshold value Va, that is, when Vss-VB->VTP, then M
O5) Since transistor M7 is turned off, connection node B'
The voltage V8- is held at Vss-Vtp. As a result, no current is supplied to the base of bipolar transistor Q2. Therefore, bipolar transistor Q2
is turned off, so it does not operate in the pseudo-saturation region.

Bipolar] When transistor Q2 is turned off, the charge charged in the load is transferred to resistive element RMOS transistor M2.
Since the output signal v out becomes "L" level, the output signal v out becomes "L" level.

FIGS. 3(a) to 3(d) show examples of the configuration of the resistive element R.

FIG. 5A shows a device consisting of passive elements such as a diffusion layer resistor using an impurity diffusion layer and a polycrystalline silicon film resistor. FIG. 2B shows a D-type N-channel MOS transistor whose gates and drains are commonly connected. The same figure (C
) is a common connection between the gates and laths of D-type P-channel MOS transistors. Figure (d) shows an E-type N-channel MOS transistor with Vcc applied to its gate and an E-type P-channel MOS transistor with Vss applied to its gate.
A channel MOS transistor is connected in parallel. When the voltage at output node A is Vcc, the voltage at output terminal 9 becomes Vc through the P-channel MOS transistor.
c, and the voltage at output node A becomes Vs
s, the voltage at the output terminal 9 can drop to Vss via the N-channel MOS transistor.

As a result, although this resistance element uses E-type P-channel N-channel MOS transistors, by connecting these in parallel, it is not affected by the threshold voltage, and the voltage at output terminal 9 is the same as that at output node A. It can perfectly follow voltage changes.

Thus, in this embodiment, the load charging/discharging bipolar transistors Ql,
Q2 can be operated only in the active region. As a result, it is possible to obtain a highly reliable B1-CMOS buffer circuit that has a high load driving capability and can prevent the substrate charge accumulation effect and the generation of substrate current.

Note that in the above embodiment, the MOS transistor M5.
The gate voltage of M6 is Vcc.

Although explained as Vss, generally the intermediate potential Vm5゜Vm
You can also give 6. At this time, the voltage of connection node A' rises to Vm6-VTN, and connection node B' becomes MO
While the S transistor M6 is off, its voltage is VSS
It drops to +1VTPl.

FIG. 4 shows BICMO8- according to the second embodiment of the present invention.
A NAND gate circuit is shown.

Note that parts corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted.

In this embodiment, the portion corresponding to the CMOS inverter 3 in the previous embodiment is composed of series-connected N-channel MOS transistors M21. A two-man powered CM consisting of M22 and P-channel MOS transistors M11 and M12 connected in parallel.
O5-NAND gate 17. Also, CMOS
Corresponding to the fact that the gate section is powered by two people, two input signals VinlVin2 are used as the on-driving MOS transistor of the load discharging bipolar transistor Q2.
Two MOSs connected in series each controlled by
Transistor M31. MB2 is provided. As in the previous embodiment, the output node A of the CMOS inverter 17 and the load charging npn bipolar transistor Q1
A first base current cutoff circuit 11 consisting of an N-channel MOS transistor M5 is inserted between the resistance element R
is connected between the output node A and the output terminal 9, and the source and drain of the N-channel MOS transistor M6 and the source and drain of the P-channel MOS transistor M7 are respectively connected in common. Two base current cutoff circuits 15 are inserted between connection nodes B and B'.

The operation of this B i -CMO3-NAND gate is basically the same as that of the B1-CMOS buffer circuit of the previous embodiment. When at least one of the two input signals Vin1 and Vin2 is at “L” level, the NAND gate 17
The voltage at output node A of increases to Vss. Then, the voltage at the connection node A' is Vcc-V7. Well, if it rises, M
Since the OS transistor M5 is turned off, the bipolar transistor Ql is turned off. Thereafter, the voltage at the output terminal 9 increases through one or both of the MOS transistors Mll and M12 and the resistance element R. Also, at this time, M for on-drive
The OS transistor M32 turns on, and the load discharge np
The n bipolar transistor Q2 is turned off as the base accumulated charge is discharged through the MOS transistor M32. As a result, the output signal V out becomes "H rubel."

Further, when the two input signals Vinl and Vin2 are both "H", the voltage at the output node A of the NAND gate 17 becomes Vss, and the load charging npn bipolar transistor Q1 is turned off.

At this time, two on-drive MOS transistors M31
．． MB2 are both turned on, and the charge charged in the load is transferred to MO3I-transistor M7. It is discharged through bipolar transistor Q2. Then, when the output voltage of the connection node B' becomes lower than Vss+1Vtpl, the load discharging bipolar transistor Q2 is turned off, and the charge charged in the load is transferred to the resistor R and the MOS transistor M21. of the CMO5-NAND gate 17. It is discharged through M22. As a result, the output signal v out becomes "L" level.

Thus, also in this embodiment, the output signal V out
It is possible to prevent the bipolar transistors Ql and Q2 from operating in a pseudo-saturated state without causing a decrease in the output amplitude of the transistors, and it is possible to obtain the same effect as in the previous embodiment.

FIG. 5 shows a Bi-CMO8 according to the third embodiment of the present invention.
-NOR gate circuit is shown. Note that portions corresponding to those in FIG. 4 are designated by the same reference numerals as in FIG. 4, and detailed description thereof will be omitted. In this embodiment, the portion corresponding to the CMO5/NAND gate 17 in FIG.
N connected in parallel with OS transistors Mll and M12
Channel MOS transistor M21. C consisting of M22
It constitutes the MO5-NOR gate 19. In response to this change, two input signals V are used as the on-drive MOS transistor of the load discharge bipolar transistor Q2
in1. Two parallel-connected N-channel MO5I-transistors M31., each controlled by Vin2. M
32 are provided.

Although a detailed explanation of the operation as a NOR gate will be omitted, this embodiment also provides the same effects as the previous NAND gate.

Note that the present invention is not limited to the embodiments described above. In the embodiment, the cases of one and two-manpower have been described, but it is generally applicable to a B1CMOS gate expanded to N inputs. Furthermore, although the embodiment has been described using an npn type bipolar transistor, a pnp type bipolar transistor may also be used. In addition, various modifications can be made without departing from the gist of the present invention.

〔Effect of the invention〕

As described above, according to the present invention, the first. The first one cuts off the supply of base current to the base of the second bipolar transistor before the bipolar transistor operates in the pseudo-saturation region. Since the second base current cutoff circuit is connected, the bipolar transistor is turned off before operating in the pseudo-saturation region. In addition, since an output voltage compensation circuit is provided, the first. A desired output amplitude can be obtained even when the second bipolar transistor is turned off.

As a result, 1. The second bipolar transistor can be operated only in the active region. Therefore, it is possible to prevent base charge accumulation and increase in substrate current due to the generation of parasitic transistors, resulting in high-speed operation and high reliability Bi-C
A semiconductor integrated circuit consisting of MO5 circuits can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a Bi diagram according to the first embodiment of the present invention.
FIG. 4 is a diagram showing an example of the configuration of a resistance element used in a CMOS buffer circuit, and FIG.
FIG. 5 is a diagram showing a B i -CMO5-NOR gate circuit according to the third embodiment of the present invention, FIG. 6 is a diagram showing a conventional B1-CMOS buffer circuit, Figure 7 is a diagram for explaining the static characteristics of a bipolar transistor, and Figure 8 is a diagram of a conventional BICMOS.
FIG. 3 is a diagram showing an ICMOS fluctuation waveform. 1... Input terminal, 3... CMOS inverter, 5...
...Charging circuit, 7...Discharging circuit, 9...Output terminal,
11...First base current cutoff circuit, 13...Output voltage compensation circuit, 15...Second base current cutoff circuit MO
S transistor circuit, 17...CMO8-NAND gate, 19...CMO8-NOR gate, Ml,,M
7...P-channel Mos transistor, M2. M3. M
4. M5. M6. M21. M22゜MB2. MB2...
・N-channel MOS transistor, Ql, Q2...n
pn bipolar transistor, R...resistance element, VA
...Voltage of output node A, VA-...Connection node A
' voltage, ■, -... voltage at connection node B'.

Claims (5)

[Claims] (1) A CMOS gate circuit having at least one input terminal, a collector connected to a first power supply potential, and a base connected to the CMOS gate circuit.
a first bipolar transistor connected to an output node of the MOS gate and whose emitter is connected to an output terminal connected to a load; and a first bipolar transistor inserted between the base of the first bipolar transistor and the output node of the CMOS gate,
a first base current cutoff means that is controlled by the output node and cuts off the base current of the first bipolar transistor before the voltage between the collector and emitter of the first bipolar transistor becomes equal to or less than a predetermined value; an output voltage compensation circuit provided between the output node of the CMOS gate and the emitter of the first bipolar transistor; and the first bipolar transistor, the collector of which is connected to the output terminal, and the emitter of which is connected to a second power supply potential. a second bipolar transistor of the same type as the bipolar transistor; and a second bipolar transistor inserted between the base of the second bipolar transistor and the output terminal to selectively short-circuit the base and collector of the second bipolar transistor. Said commercial
short-circuiting means for discharging the charge stored in the load through the second bipolar transistor when the voltage at the output node of the OS gate increases to the point where the first bipolar transistor is turned off; The second bipolar transistor is inserted between the base of the second bipolar transistor and controlled by the output node of the CMOS gate, and before the collector-emitter voltage of the second bipolar transistor becomes equal to or less than a predetermined value. A semiconductor integrated circuit comprising: second base current cutoff means for cutting off the base current of a bipolar transistor. (2) The semiconductor integrated circuit according to claim 1, wherein the first base current cutoff means comprises a MOS transistor whose gate is connected to the first power supply potential. (3) The second base current cutoff means includes a MOS transistor having the same channel as the MOS transistor constituting the first base current cutoff means whose gate is connected to the output node of the CMOS gate, and a MOS transistor whose gate is connected to the output node of the CMOS gate. 2. The semiconductor integrated circuit according to claim 1, wherein a MOS transistor constituting the first base current cutoff means connected to a second power supply potential and a reverse channel MOS transistor are connected in parallel. (4) The semiconductor integrated circuit according to claim 1, wherein the output voltage compensation circuit is a diffusion layer resistor made of an impurity diffusion layer. (5) The shorting means includes a first MOS transistor having the same channel as the MOS transistor constituting the first base current interrupting means, whose gate is connected to the input terminal and whose drain is connected to the output terminal, and whose drain is connected to the output terminal. 1st M
It is connected to the source of the OS transistor, and the gate is connected to the C
2. The semiconductor according to claim 1, comprising a second MOS transistor having the same channel as said first MOS transistor, connected to an output node of a MOS gate and having a source connected to said second power supply voltage. integrated circuit.