JP2001154632A - Scan electrode driving ic for plasma display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a danger causing noise on a lower rank source line VSS and becoming a malfunction when a plasma display scan electrode driving IC 50 drives simultaneously whole scan electrodes from high to low. SOLUTION: A low side output transistor is divided to a first N type output transistor NO1 and a second N type output transistor NO2 to be provided, and for the period when the relevant output terminal OUT-Yi is driven to low peculiar to the terminal, the first, second both N type output transistors NO1, NO2 are turned On together, and for the period when the whole output terminals OUT-Y1,2,...M are driven to low, only the first N type output transistor NO1 is turned On, and the On resistance of the low side output transistor is enlarged, and a current flowing through the lower rank source line VSS is reduced when a terminal voltage is changed from high to low.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for driving a scan electrode of an AC type plasma display panel (hereinafter referred to as "PDP"), and more particularly to a circuit formed as a semiconductor IC.

[0002]

BACKGROUND ART PDP1 the M scan electrodes Y ₁ extending in the horizontal direction as in the circuit diagram shown in FIG. _3, Y ₂ ...... Y _M and, M extending in the horizontal direction along the respective scan electrodes Y _i comprising an electrode Z _1, Z ₂ ...... Z _M maintenance of the data electrodes X ₁ of N present extending in the vertical direction so as to intersect them, and X ₂ ...... X _N, the scan electrodes Y _i and the data electrodes cell K _ij include intersections between the intersection and the sustain electrode Z _i and the data electrode X _j and X _j is formed. Then, one pixel is formed by the three RGB cells. In order to drive the PDP ₁ , the scan electrodes Y ₁ , Y _2, ..., Y _M are connected to scan electrode drive ICs 2 each having an output terminal corresponding thereto, and the data electrodes X ₁ , X ₂ ,. _N is connected to a data electrode driving IC 3 having an output terminal corresponding to each of them.
₁ , Z ₂ ... Z _M are commonly connected to one terminal, and the sustain electrode drive circuit 4 is connected.

[0003] When explaining the operating principle of the PDP 1, cell _{K i} data electrodes corresponding to the _j X _j and the scanning electrode Y as a bright
Between the _i pulsed signal with high voltage, such as a discharge occurs, a low voltage that discharge does not occur between the data electrodes X _k and the scan electrode Y _i corresponding to the cell K _ik as a dark Is given and writing is performed. Such writing of data are performed at the same time in the cell K _i1, K _i2 ...... K _iN corresponding to one scanning electrode Y _i. When the sequential writing is performed for each scan electrodes Y _1, Y ₂ ...... Y _M, the scan electrodes Y _1, Y ₂ ...... Y _M and the sustain electrodes Z _1, Z ₂ ...... with Z _M At the same time, the discharge is maintained in the cell in which the writing has been performed, but the AC voltage having a voltage that does not cause a new discharge in the cell in which the writing has not been performed is given for a predetermined maintenance time to maintain the discharge. In this way, a plurality of subfields for displaying a predetermined sustaining time in binary display are set with different sustaining times, and one field is displayed by superimposing them. That is, writing is performed in all the subfields in the cell that is displayed brightest, and writing is performed in the subfield selected so that the total maintenance time is long in the cell that is displayed relatively bright, and is displayed relatively darkly. In the cell to be written, writing is performed in a subfield selected so as to shorten the total maintenance time, and writing is not performed in all the subfields in a cell displayed darkest.

FIG. 4 is a timing chart showing the voltage of each electrode for explaining the above operation for one subfield. The period of one subfield is divided into a preliminary discharge period, a data write period, and a sustain period. First First each of the data electrodes X ₁ is in the priming discharge period, X ₂ ...... X _N and the sustain electrodes Z _1, Z ₂ ...... Z scanning electrodes and _M in a state with the ground potential Y _1, Y ₂ ...... Y have a negative erase pulse Vap simultaneously _M, followed by each of the data electrodes X _1, X ₂ ...... X _N and the scan electrodes Y _1, Y ₂ ...... Y maintain and _M in a state with the ground potential electrode Z ₁ , Z ₂ ... Z _M are simultaneously applied with a negative erase pulse Vp to erase the display contents of the previous subfield and prepare for writing new data. In the next writing period, the sustain electrodes Z ₁ , Z ₂ ,.
Z _M is kept at a ground potential, first scan electrode Y ₁ is selected to correspond to the negative scan pulse Vw data electrodes X ₁ at the same time is given, X ₂ ...... X _N respectively bright cell to The positive data pulse Vd is given a ground potential corresponding to the dark cell. Then, the cell to which the data pulse Vd is applied is discharged, and data is written. Writing is performed by the same operations for the following line-sequentially scan electrodes Y ₂ to Y _M. In the next sustain period, the data electrodes X ₁ , X _2, ..., X _N are maintained at the ground potential,
Repeatedly applied to all the scan electrodes Y _1, Y ₂ ...... Y _M simultaneously negative sustain pulse Vs, it a negative sustain pulse Vr phase shifted by a half period to all the sustain electrodes Z _1, Z ₂ ...... Z _M The discharge is repeatedly provided to maintain the discharge for a predetermined sustain period.

Next, a description will be given of a conventional example of the scan electrode drive IC 2 for providing such drive signals to the scan electrodes Y ₁ , Y ₂ ... Y _M. FIG. 5 is a main part circuit diagram showing the output part. In FIG. 3, the scan electrode drive ICs 2 are depicted as one IC, but when the number of scan electrodes Y of the PDP is large, a plurality of scan electrode drive ICs 2 are often arranged in parallel. The scanning electrode driving IC 2 has an output terminal OU as an external terminal.
It includes a _{T-Y 1, OUT-Y} 2 ...... OUT-Y M, are respectively connected to the scanning electrodes Y _1, Y ₂ ...... Y _M of the PDP. The output terminals OUT-Y ₁ , OUT-Y ₂ ... OUT
−Y _M is provided with an output circuit section 20 as shown in FIG.
Each of the output circuit units 20 receives data input signals DIN-1 and DIN-
... DIN-M and a blanking signal input terminal LBLK for pre-discharge and sustaining discharge.
The blanking signal input terminals LBLK of the output circuit units 20 are commonly connected. The data input terminals DIN-1, DIN-2,..., DIN-M and the blanking signal input terminal LBLK are internal terminals, and signals to these are generated by a preceding circuit (not shown).

The scan electrode driving IC 2 outputs a high voltage pulse signal (for example, 100 V).
High DC voltage between the low-potential line V _SS as indicated by the high-potential line V _DD and the ground symbol of the high voltage power supply is applied indicated by the symbol, so a high-pressure portion to be driven, low include circuitry pre not shown A logic portion driven by a voltage (for example, 5 V) is included on the same substrate. Then, the substrate potential and the low-potential power supply line V _SS of high and low power. Therefore, although not shown in FIG. 5, the circuit of the logic unit is composed of a high-order line ( _{VDD 2} ) of the _second power supply and a low-order power supply line V
_A low voltage is applied between the power supply terminal and the power supply terminal _SS, and the device operates with the low voltage.

When the scan electrode drive IC 2 is connected and used as shown in FIG. 3, the high-order line _VDD of the high-voltage power supply is connected to a common ground line with the other drive circuits (3, 4). Connecting. Therefore, the output terminals OUT-Y ₁ , O
UT-Y ₂ ... OUT-Y _M is used to output a pulse signal that changes between 0 V and −100 V based on the high-order line _VDD of the high-voltage power supply. For this reason, the lower power supply line _VSS is used as a reference (0
V). Then, the output terminal OUT-Y
₁ , OUT-Y ₂ ... OUT-Y _M are described as outputting a pulse signal that changes between 100 V and 0 V.

Next, the configuration of the output circuit section 20 will be described.
High-voltage high-potential line V _DD source is connected to the P-channel MOS output transistor (hereinafter P-type output transistor P _O) and low-potential power supply line V _SS N-channel MOS output transistor whose source is connected to the ( the following N-type output transistor N _O) and provided with, the connection point is an output terminal OUT-Y _i and drains of the two transistors are connected. Further, a first P-channel M having a source connected to the high-voltage high-order line _VDD
The first N-channel MOS-type driver transistor (hereinafter a 1N-type driver transistor N ₁₎ and the two transistors having its source connected to the low-potential power supply line V _SS and OS type driver transistor (hereinafter the 1P type driver transistor P ₁₎ Are connected to each other.
Then, the 2N-channel MOS high voltage first 2P channel MOS-type driver transistor (hereinafter the 2P type driver transistor P ₂₎ and the source to the low side power supply line V _SS whose source is connected to the high side line V _DD of connected And a drain driver transistor (hereinafter referred to as a second N-type driver transistor) N ₂ having drains of both transistors connected to each other. The connection point between the drains of the _first P-type driver transistor P ₁ and the first N-type driver transistor N ₁ is connected to the gate of the P-type output transistor _{PO and to} the gate of the second P-type driver transistor P _2. ing. Then, the second P-type driver transistor P ₂ and the second N-type driver transistor N ₂
Is connected to the gate of the _first P-type driver transistor P1. Each of the above transistors P _O , N _O , P ₁ , N ₁ , P ₂ , and N ₂ is provided as a high-voltage portion and has a high withstand voltage.

A NAND circuit 21 having a data input terminal DIN-i and a blanking signal input terminal LBLK as input terminals, an input terminal connected to its output terminal, and an output terminal connected to the first N-type driver transistor N _1.
NOT circuit 22 connected to the gate of
And a second, third NOT circuits 23 and 24 connecting between the gate of the output terminal and the N-type output transistor N _O circuits 21 are serially connected. The output terminal of the NAND circuit 21 is connected to the gate of the _second N-type driver transistor N2. Then, the NAND circuit 21, the first NOT circuit 22, the second and third NOT circuits 23, 24
Each of the circuits is a logic unit driven by a low voltage source together with a preceding circuit (not shown). Here, the first P-type driver transistor P ₁ and the first N-type driver transistor N ₁ ,
And the 2P type driver transistor P _2, and the 2N-type driver transistor N _2, and the first 1NOT circuit 22 constitute a level shift circuit for converting a signal of a low voltage to a high voltage signal. Then, the second and third NOT circuits 23,
Reference numeral 24 denotes a circuit for delaying the signal in accordance with the signal delay by the level shift circuit.

Next, the operation of the output circuit section 20 will be described. FIG. 6 is a timing chart. Each output circuit 20 will be described in the first example of the circuit of the output terminal OUT-Y ₁ Since the same. Blanking signal input terminal L
As shown in FIG. 6, a signal for pre-discharge and discharge maintenance is adjusted by a preceding circuit (not shown) and supplied to BLK as a low pulse signal. As shown in FIG. 6, a signal for data writing is adjusted by a preceding circuit (not shown) and supplied to the data input terminal DIN-1 as a low pulse signal. This signal is generated once per subfield, and is similarly applied to the other data input terminals DIN-2,.

First, the relationship between the voltage at the output terminal of the NAND circuit 21 and the states of the P-type output transistor P _O and the N-type output transistor N _O will be described. (1) transistor N ₂ when the voltage of the output terminal of the NAND circuit 21 is high On, transistor N ₁ is Off
It is. Therefore, transistor P ₁ is transistor P ₂ and P-type output transistor P _O is Off since On. Then, N-type output transistor N _O a row is outputted to the output terminal OUT-Y ₁ because it On. (2) the transistor N ₂ when the voltage of the output terminal of the NAND circuit 21 is low is Off, the transistor N ₁ is On
It is. Therefore, the transistor P ₂ is to On, the transistor P ₁ is Off, P-type output transistor P _O is On
I do. Then, N-type output transistor N _O High is outputted to the output terminal OUT-Y ₁ since the Off. By the way, the voltage of the output terminal of the NAND circuit 21 becomes low only when the voltage of the blanking signal input terminal LBLK and the voltage of the data input terminal DIN-1 are both high, and the others become high. OUT-Y of the blanking signal as indicated by ₁ the low-pulse and a data input terminal DI
The driving signal waveform has a low driving pulse corresponding to both N-1 low pulses. And another output terminal OU
Pulse signal T-Y _i in the data write period also is timing is shifted is output as well.

[0012]

However [0007] drives the scan electrodes Y _1, Y ₂ ...... Y _M in the scanning electrode driving IC2 as described above, when varying the potential of the scan electrodes Y _i from high to low it is intended to discharge by applying a current to the low potential power supply line V _SS via the N-type output transistor N _O. Then, high-side line V _DD of the high voltage power supply through a P-type output transistor P _O is in the switched operation from low to high
It is intended to flow a current to the scan electrodes Y _i from. Such driving is performed during the data writing period (operation based on the signal to the data input terminal DIN-i) during the scanning electrodes Y ₁ ,
Y ₂ ... Y _M is a pulse peculiar to Y _M , and there is no problem because the timing is shifted. However, such driving in the pre-discharge period and the sustain period is performed by the blanking signal input terminal LBL.
Based on the signal given to K, all the scanning electrodes Y ₁ , Y ₂
It takes place at the same time ...... Y _M. Therefore, a large current flows into the low-potential power supply line V _SS via the N-type output transistor N _O, to vary the potential of the low-potential power supply line V _SS at the beginning of switched from high to low. High side line V scan from _DD electrodes Y ₁ of the high voltage power supply through a large current P-type output transistor P _O at the beginning to replace simultaneously switching from low to high, Y ₂ flows into ...... Y _M, the high side of the high voltage power supply The potential of the line _VDD is changed.

[0013] Therefore, in the conventional circuit, when changing from simultaneously brazing the scan electrodes Y _1, Y ₂ ...... Y _M since the low-potential power supply line V _SS is a common potential between the low voltage power supply and the high voltage power supply to the high the high voltage power supply is relatively problem free because there is no relationship to the logic unit also fluctuates the potential of the high potential side line V _DD, a common low-potential power supply line V _SS when changing from high to low at the same time There is a concern that the potential may fluctuate and cause noise to cause a malfunction in the logic unit. Therefore, the present invention reduces the current flowing when all the scan electrodes simultaneously switch from high to low even if the low potential side is set to a common potential between the low-voltage power supply and the high-voltage power supply. Slow down) to prevent malfunction.

[0014]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is to drive a scanning electrode of a plasma display having a plurality of scanning electrodes to high and low. A high-side line of a low-voltage power supply, a common low-side power supply line, a logic unit functioning with the low-voltage power supply, and an output terminal corresponding to each of the scan electrodes. An upper output transistor that connects a high-order line and the output terminal, and is provided for each output terminal corresponding to each of the scan electrodes,
A lower output transistor that connects between the lower power supply line and the output terminal. The upper and lower output transistors are complementarily On-Off driven to simultaneously perform a low pulse specific to the scan electrode and a simultaneous scan pulse for all scan electrodes. In a scan electrode driving IC of a plasma display for outputting a low pulse, the lower output transistor is composed of two pieces, and the first lower output transistor is the same as that of the scan electrode during the low pulse period in the output waveform. , And the second lower output transistor is turned on only during the low pulse period for all the scan electrodes at the same time. According to this configuration, the first
The lower output transistor is made smaller (increases the On resistance) within an allowable range in operating characteristics including an allowable current value,
When the drive signal changes from high to low for all the scan electrodes in common (based on the blanking signal), the current can be reduced as much as possible, and the scan signal is changed from high to high (based on the data signal). When changing to low, the second lower output transistor is also turned on at the same time, and the On resistance of both the first and second lower output transistors is lowered to secure a required response speed.

More specifically, the logic unit generates a data signal serving as a basis of a drive pulse specific to the scan electrode and a blanking signal serving as a basis of a drive pulse common to all scan electrodes.
An upper output transistor that connects an output circuit unit provided for each output terminal corresponding to each scan electrode between a high-order line of the high-voltage power supply and the output terminal; and an output circuit that connects the low-order power supply line and the output terminal. A first and a second lower output transistor connecting between the first and second lower output transistors, a data signal input terminal, a blanking signal input terminal, and a logical operation result of the data signal and the blanking signal; A first drive signal for outputting a predetermined drive signal to the output terminal by complementarily performing On-Off control of the lower output transistor and the lower output transistor.
And the logical operation result of the data signal and the blanking signal, the second lower output transistor is turned on only during a low period when the drive signal is based on the data signal.
n and a second logic circuit that controls to be off during the other period.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A scan electrode driving IC according to the present invention drives a scan electrode of an AC plasma display having a plurality of scan electrodes. Then, a logic unit driven by a low voltage and a high voltage unit driven by a high voltage power supply for outputting a drive signal of a high voltage scan electrode are formed on the same substrate. A dielectric isolation method is used as a high-breakdown-voltage element isolation method. A method of forming a high-breakdown-voltage transistor in a P-type well or an N-type well formed by introducing impurities is used. There may be. Therefore,
It has a high-order line for a high-voltage power supply and a high-order line for a low-voltage power supply. The lower potentials of both power supplies are set to the same potential. Each lower line may be connected inside the IC or externally.

An output circuit unit is provided for each output terminal, including an output terminal corresponding to each scanning electrode of the PDP. This output circuit section includes a high voltage section driven by a high voltage power supply and a part of a logic section driven by a low voltage source. In the high voltage section, an upper output transistor connecting the high-order line of the high-voltage power supply and the output terminal, and first and second lower output transistors connecting the low-order power supply line and the output terminal have a high withstand voltage. Included as a simple transistor. These transistors may be of a field effect type or a bipolar type, and the upper and lower transistors may be of the same conductivity type, but the drive circuit (driver stage) is simpler when they are of a complementary type.

The output circuit section has a data signal input terminal for receiving a data signal provided from a preceding circuit included in the logic section and serving as a basis for a drive pulse (pulse in an output signal) peculiar to the scan electrode. Similarly, a blanking signal input terminal for receiving a blanking signal which is a base of a drive pulse common to all scan electrodes and provided from a preceding circuit is provided as an internal terminal.

The upper output transistor generates a drive signal including a drive pulse peculiar to the scan electrode and a drive pulse common to all scan electrodes by a logical operation result of the data signal and the blanking signal by the first logic circuit. And the first lower output transistor complementarily to On-Off.
Control. Of course, if the first logic circuit is configured to be driven by a low-voltage power supply, a level shift circuit is required between the first logic circuit and the output transistor.

A second logic circuit is provided, and the second lower output transistor is turned on by a logical operation result of the data signal and the blanking signal while the drive signal is turned on only during a low period based on the data signal, and is turned on for another period. Is controlled to be Off.

Then, the first lower output transistor is made smaller (the On resistance is made larger) within an allowable range in terms of operating characteristics. Then, when all the scanning electrodes simultaneously change from high to low, the current flowing into the lower power supply line is reduced as much as possible, the generated noise is reduced, and the risk of malfunction in the logic unit is reduced. And the second
The lower output transistor is of a size to complement the first lower output transistor so that a required response speed in a write operation can be obtained.

[0022]

An embodiment of the present invention will be described with reference to the drawings. The scan electrode driving IC 50 of this embodiment is the same as the P shown in FIG.
It has the same function as the scan electrode drive IC2 in the drive circuit diagram of DP1. FIG. 1 is a main part circuit diagram showing the output part. In the figure, the same parts as those of the conventional scan electrode driving IC 2 shown in FIG. This scan electrode driving IC 50 has output terminals OUT-Y ₁ , OUT-Y ₂ ... OU as external terminals.
T-Y _M, and the scanning electrodes Y ₁ , Y ₂ ,.
... that are connected to the Y _M is the same as the conventional. Each of the output terminals OUT-Y ₁ , OUT-Y ₂ ... OUT-Y _M is provided with the output circuit section 40 shown in FIG. 1 instead of the output circuit section 20 shown in FIG. Then, each output circuit unit 40
Each is provided with data input terminals DIN-1, DIN-2,..., DIN-M for receiving signals for writing data, and is provided with a blanking signal input terminal LBLK, which is similar to the conventional circuit. Further, the point that the blanking signal input terminals LBLK of the respective output circuit units 40 are connected in common, and the data input terminals DIN-1 and DIN-2
... DIN-M and a blanking signal input terminal LBLK are internal terminals, and signals to these are generated by a preceding circuit (not shown) as in the related art. Then, ▽ given high DC voltage between the high potential side line V _DD of the high voltage power supply shown by the symbol and the low-potential line V _SS as indicated by the ground symbol,
The same is true of the fact that a high-voltage unit driven by this and a logic unit driven by a low voltage including a preceding circuit (not shown) are included on the same substrate. The same is true point commonly connecting the low-potential power supply line V _SS of high and low power.

Next, the configuration of the output circuit section 40, which is a feature of this embodiment, will be described. Examples of the upper output transistor, its source connected to the low-potential power supply line V _SS as an example of a source-connected P-type output transistor P _O and the first low side output transistor to the high side line V _DD of the high voltage A first N-channel MOS output transistor (hereinafter referred to as a first N-type output transistor N _{O 1} ),
And drains of the two transistors are connected, the connection point is an output terminal OUT-Y _i. Further, the first P in which the source is connected to the high-voltage high-side line V _DD
Type driver transistor P ₁ and the low-side power supply line _{V SS}
N-type driver transistor N whose source is connected to
₁ is provided with the drains of both transistors connected to each other. Then, the high voltage first 2P type driver transistor P ₂ and the 2N-type driver transistor N ₂ and the drains of the transistors with each other having its source connected to the low-potential power supply line V _SS whose source is connected to the high side line V _DD of Are connected and provided. The connection point between the drains of the _first P-type driver transistor P ₁ and the first N-type driver transistor N ₁ is connected to the gate of the P-type output transistor P _{O and to} the gate of the second P-type driver transistor P _2. ing. Then, the second P-type driver transistor P ₂ and the second N-type driver transistor N ₂
Is connected to the gate of the _first P-type driver transistor P1.

In the present invention, a NAND circuit 21 called a first logic circuit is provided with a data input terminal DIN-i blanking signal input terminal LBLK as an input terminal. A first NOT circuit 22 having an input terminal connected to its output terminal and an output terminal connected to the gate of the _first N-type driver transistor N1, and a NAND circuit 21
And third NOT circuit 2 that connects in series between the output terminal of the first N-type output transistor N _{O1 and} the gate of the first N-type output transistor N _O1
3, 24. The output terminal of the NAND circuit 21 is connected to the gate of the _second N-type driver transistor N2. Then, the NAND circuit 21 and the first
Each of the NOT circuit 22, the second and third NOT circuits 23 and 24 is a logic unit driven by a low voltage source together with a preceding circuit (not shown). Here, the 1P type driver transistor P ₁ and the second 1N-type driver transistor N _1, and the 2P type driver transistor P _2, and the 2N-type driver transistor N _2, and the first 1NOT circuit 22, a signal of low voltage A level shift circuit for converting into a high voltage signal is configured. Then, the second and third NOT circuits 23, 2
Reference numeral 4 denotes a circuit for delaying the signal in accordance with the signal delay by the level shift circuit. The above-described portions is only changed to N-type output transistor N _O it is smaller than the first N-type output transistor N _O1 as compared with the conventional output circuit 20 shown in FIG.

This embodiment is characteristically different from the conventional circuit in that a second N-channel output transistor as an example of a second lower output transistor (hereinafter referred to as a second N-type output transistor N _O2 ). Outputs the drain to the output terminal OUT-
Connect to Y _i, a point that is a point which is provided to connect the source to the low-potential power supply line V _SS, is provided a second logic circuit for controlling it. The second logic circuit includes a first NAND circuit 21 provided in a conventional circuit, an added second NAND circuit 41, and an added fourth NOT circuit 42
It is composed of That is, one input terminal of the second NAND circuit 41 is connected to the output terminal of the first NAND circuit 21, and the other input terminal is connected to the blanking signal input terminal LB.
LK, and the output terminal is connected to the input terminal of the fourth NOT42 circuit. Then, the fourth NOT circuit 42
Is connected to the gate of the second N-type output transistor N _O2 . Each of the above transistors P _O , N _O1 ,
N _O2 , P ₁ , N ₁ , P ₂ , and N ₂ are provided as high-voltage portions and have a high withstand voltage.

Next, the operation of the output circuit section 40 will be described. FIG. 2 is a timing chart. Each output circuit 40 is similar to FIG. 6 because same will be described with the first circuit output terminal OUT-Y ₁ as an example. The signals supplied to the blanking signal input terminal LBLK and the data input terminal DIN-1 are the same as the conventional signals shown in FIG.
Therefore, the operation of the P-type output transistor P _O in FIG. 6 is the same as, for example, P _O (1) indicating the state of the P-type output transistor at the _first output terminal OUT-Y1. The operation of the first N-type output transistor N _O1 is similar to, for example, N _O (1) indicating the state of the N-type output transistor at the _first output terminal OUT-Y ₁ in FIG. , N _O1 (1), and the description is omitted.

Next, the operation of the second N-type output transistor N _O2 will be described. (1) While both the blanking signal and the data signal are high, the voltage at the output terminal of the first NAND circuit 21 is low. Then, the output terminal of the second NAND circuit 41 becomes high. Then, the signal is inverted and supplied to the gate by the fourth NOT circuit 42, so that the second N-type output transistor N _O2 is turned off. (2) While the blanking signal is high and the data signal is low, the voltage at the output terminal of the first NAND circuit 21 is high. Then, the output terminal of the second NAND circuit 41 becomes low. Then, the signal is inverted and supplied to the gate by the fourth NOT circuit 42, so that the second N-type output transistor N _O2 is on. (3) During the period when the blanking signal is low and the data signal is high, the voltage at the output terminal of the first NAND circuit 21 is high. Then, the output terminal of the second NAND circuit 41 becomes high. Then, the signal is inverted and supplied to the gate by the fourth NOT circuit 42, so that the second N-type output transistor N _O2 is turned off. That is, the second N-type output transistor N _O2 is the have to On only during the period (2), an operating state indicated as N0 ₂ (1) in FIG. 2 in the case of the example, the first output terminal.

[0028] Therefore, the output terminal OUT-Y ₁ is output driving signal waveform with a drive pulse of the row corresponding to the low pulse both the low-pulse and a data input terminal DIN-1 as in the prior art blanking signal. However,
At the time of a low pulse based on a blanking signal, the second N-type output transistor N _O2 remains off, so that the falling waveform becomes gentler than the conventional one, but it is not explicitly shown in FIG. In the case of a low pulse based on the data signal, the second N
Since the type output transistor N _{O2 is} also turned on, the falling speed is fast as in the conventional circuit.

[0029] Then, the pulse signal of the other output terminal OUT-Y _i in the data write period also is are offset timing is output as well.

According to the above embodiment, since the current flowing into the low-potential power supply line V _SS when simultaneously with brazing of all the scanning electrodes can be as small as possible, the noise is reduced resulting in low-potential power supply line, The risk of malfunction is reduced.

[0031]

As described above, according to the scan electrode driving IC of the plasma display of the present invention, the lower output transistor of the upper and lower output transistors for driving the scan electrode high and low is divided into two. In the case of a low pulse peculiar to the scanning electrode, both are turned on to secure a fast fall, and in the case of a low pulse applied to all the scanning electrodes simultaneously, only one of them is turned on to increase the On resistance and reduce the current. Therefore, the risk of malfunction can be reduced.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram of a scan electrode driving IC of a plasma display according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of the output circuit unit in FIG.

FIG. 3 is a driving circuit diagram of a plasma display.

FIG. 4 is a timing chart illustrating the operation of the circuit in FIG. 3;

FIG. 5 is a main part circuit diagram of a scan electrode driving IC of a conventional plasma display.

FIG. 6 is a timing chart illustrating the operation of the output circuit unit in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Plasma display 21 1st NAND circuit (1st logic circuit) 40 Output circuit part 41 2nd NAND circuit 42 4th NOT circuit 50 Scan electrode drive IC DIN-1, DIN-2 ... DIN- of plasma display M Data signal input terminal LBLK Blanking signal input terminal N _O1 First N-type output transistor (first lower output transistor) N _O2 Second N-type output transistor (second lower output transistor) OUT-Y _{1, OUT-Y 2 ... OUT} -Y M output terminal P _O P-type output transistor (upper output transistor) _{V DD} high voltage high side line V _SS common low-potential power supply line Y ₁ of the power source, Y ₂ ... Y _i ... Y _M scanning electrode

Claims (3)

[Claims] A high-voltage power supply, a high-voltage power supply, a low-voltage power supply, and a common low-voltage power supply. And a logic unit functioning with the low-voltage power supply, and an upper output transistor provided for each output terminal corresponding to each of the scan electrodes and connecting a high-order line of the high-voltage power supply and the output terminal. A lower output transistor that is provided for each output terminal corresponding to each of the scan electrodes and that connects the lower power supply line and the output terminal. The upper and lower output transistors are complementarily On-Off.
In a scan electrode driving IC of a plasma display which drives to output a low pulse peculiar to the scan electrode and a low pulse for all scan electrodes at the same time, the lower output transistor is composed of two pieces, and the first lower output transistor is an output. It is assumed that both the period of the low pulse peculiar to the scan electrode in the waveform and the period of the low pulse for all the scan electrodes are on, and the second lower output transistor is on only for the period of the low pulse for all the scan electrodes. Scan electrode drive IC for plasma display. 2. A method for driving a scan electrode of a plasma display having a plurality of scan electrodes, comprising: a high-side line of a high-voltage power supply; a high-side line of a low-voltage power supply; a common low-side power supply line; A logic unit functioning with the low-voltage power supply, and an output circuit unit provided for each output terminal corresponding to each scan electrode, wherein the output circuit unit includes a part of the logic unit, An upper output transistor that connects between a higher-order line of a high-voltage power supply and the output terminal; first and second lower output transistors that connect between the lower-order power supply line and the output terminal; A data signal input terminal for receiving a data signal as a basis of a specific drive pulse, a blanking signal input terminal for receiving a blanking signal as a basis for a drive pulse common to all scan electrodes, Complementarily On-Of the logical operation result in the upper output transistor and said first low side output transistor between the signal and the blanking signal
a first logic circuit that controls the output terminal to output a predetermined drive signal to the output terminal; and the drive signal drives the second lower output transistor based on a logical operation result of the data signal and the blanking signal. A second logic circuit for controlling the row based on the data signal to be ON only during a row period and OFF during the other period. 3. The high-side output transistor is of a P-channel MOS type, and the first and second low-side output transistors are each of an N-channel MOS type.
A scan electrode driving IC for a plasma display according to claim 2.