JP2008158439A - Active matrix type display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce current consumption in an active matrix type display panel. <P>SOLUTION: A static memory is formed of a first drive transistor 2 and a second drive transistor 4. The data voltage from a data line 7 is input via a transistor 5 and is stored in the static memory. First and second organic EL elements 1, 3 are connected to the first and second drive transistors 2, 4 and by making either non-light emittable and the other light emittable, the light emission complying with the data voltage is performed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an active matrix display panel having a transistor for controlling data intake for each pixel.

  An active matrix display panel is widely used as a display because of its high resolution. Here, an active matrix display requires an active element for determining a display state for each pixel. In particular, in the case of a current drive type such as an organic EL display, a drive transistor capable of continuing to supply current to the organic EL element is provided. A thin film transistor (Thin Film Transistor: TFT) formed of a thin film such as amorphous silicon or polysilicon is used as the driving transistor, but it is difficult to make the characteristics of the TFT uniform.

  Several methods for correcting TFT characteristics using circuit technology have been proposed, and one of them is digital driving (Patent Document 1).

JP-A-2005-331891

  However, in digital driving, it is necessary to divide one frame period into a plurality of subframe periods, and write data for controlling whether or not to light each subframe period given a certain light emission period to a pixel. For this reason, the power consumption for transferring data increases. For example, if one frame period is divided into eight subframes, it is necessary to access the pixel eight times in one frame period compared to the case where the analog voltage is written in one normal scan. Or more than that. Therefore, it is more demanded to reduce power consumption in a digital drive display panel.

  The present invention is an active matrix display panel in which each pixel has a selection transistor for controlling input of digital data from a data line and a pair of transistors, and is arranged between a positive power source and a negative power source, and is selected. A static memory that stores digital data that is input when one transistor is turned on and the other transistor is turned off according to the digital data that is input when the transistor is turned on, and a pair of transistors of this static memory A light emitting element that emits light by current flowing through one of the transistors, and the light emission of the light emitting element is controlled in accordance with the input data.

The static memory is
A first transistor having one end connected to a power supply, a gate connected to an output side of the selection transistor, and being turned on / off by the digital data;
A second transistor having one end connected to a power source, a gate connected to the other end of the first transistor, and being turned on / off according to an on / off state of the first transistor;
Have
The other end of the second transistor is connected to the gate of the first transistor and the output side of the selection transistor;
It is preferable that the first transistor and the second transistor are complementarily turned on in accordance with input digital data.

  Preferably, a light emitting element is connected to each of the other ends of the first transistor and the second transistor, and one of the two light emitting elements emits light and the other is shielded.

  In addition, a gate is disposed between the light-shielding light-emitting element and one of the first or second transistor connected to the light-shielded light-emitting element and the other of the first or second transistor. It is preferable to provide a switching transistor connected to the end and having the opposite polarity to the other of the first or second transistor, and to cut off the current supply to the light-shielded light-emitting element by this switching transistor.

  In addition, a light emitting element is connected to one other end of the first transistor and the second transistor, and a gate is connected to the other end of the other one of the first or second transistor. And a switching transistor having a polarity opposite to that of the first or second transistor is provided, and the switching transistor cuts off a current flowing when the other of the first or second transistor is turned on. Is preferred.

  Further, it is preferable that a frame memory for storing at least one frame of digital data is provided, and the digital data is supplied from the frame memory to the data line.

  Further, a gate line is arranged for each row of pixels, and the gate line is driven by a gate driver to control the selection transistor, and the gate driver can sequentially select only a predetermined range of rows, Thus, it is preferable that the data of only the pixels within the selected range can be updated.

  In addition, the frame memory can store both 1-bit digital data and multi-bit digital data corresponding to each pixel. In the monochrome pixel memory display mode, 1-bit digital data per frame is stored. In the case of multi-gradation mode, it is preferable that digital data of a plurality of bits is supplied to the data line in a plurality of subframes.

  In addition, it is preferable that one bit digital data or a plurality of bits digital data from the frame memory can be selected for the data line of each column, and the display mode can be partially changed. .

  The light emitting element is preferably an organic EL element.

  As described above, according to the present invention, since each pixel has a static memory, the data once written is maintained until the power is turned off. Therefore, refreshing is unnecessary, and the display is not particularly changed. In some cases, power saving can be achieved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
1A and 1B show the configuration of the pixel circuit of the present invention. FIG. 1A is a pixel equivalent circuit, and FIG. 1B is a pixel circuit arrangement wiring diagram (layout) as viewed from the opposite side of the light emitting surface.

  The pixel circuit includes a first organic EL element (light emitting element) 1 that contributes to light emission, a first drive transistor (first transistor) 2 that drives the first organic EL element (light emitting element) 2, a second organic EL element (light emitting element) 3 that does not contribute to light emission, The supply of the data voltage supplied to the data line 7 is controlled to the gate terminal of the first drive transistor 2 by the second drive transistor (second transistor) 4 for driving it and the gate line 6 to which the selection signal is supplied. The gate transistor (selection transistor) 5 is configured. Thus, this pixel circuit does not require a holding capacitor for holding a data voltage that has been required in the past. In this example, the first drive transistor 2, the second drive transistor 4, and the gate transistor 5 are all composed of P-type TFTs.

  The anode of the first organic EL element 1 is connected to the drain terminal of the first drive transistor 2 and the gate terminal of the second drive transistor 4. The gate terminal of the first drive transistor 2 is connected to the anode of the second organic EL element 3, the drain terminal of the second drive transistor 4, and the source terminal of the gate transistor 5. The gate terminal of the gate transistor 5 is connected to the gate line 6, and the drain terminal is connected to the data line 7. The source terminals of the first drive transistor 2 and the second drive transistor 4 are connected to the power supply line 8, and the cathodes of the first organic EL element 1 and the second organic EL element 3 are connected to the cathode electrode 9.

  When the gate line 6 is selected (Low), the gate transistor 5 is turned on, and the data voltage supplied to the data line 7 is taken into the pixel circuit via the gate transistor 5.

  When the data voltage is low, the first drive transistor 2 is turned on. When the first drive transistor 2 is turned on, the anode of the first organic EL element 1 is connected to the power supply line 8 to which the power supply voltage VDD is supplied, and a current flows through the first organic EL element 1 to emit light. At the same time, the gate terminal of the second drive transistor 4 becomes VDD, and the second drive transistor 4 is turned off, whereby the anode of the second organic EL element 3 is lowered to the cathode potential VSS. Since this cathode potential VSS is supplied to the gate terminal of the first drive transistor 2, even after the gate line 5 is set to High and the gate transistor 5 is turned off, the state set by the written data voltage Low remains VDD and VSS. Maintained while being given.

  When the data voltage is high, the first drive transistor 2 is turned off and the anode of the first organic EL element 1 is lowered to the cathode potential VSS. Since the cathode potential VSS is supplied to the gate terminal of the second drive transistor 2, the second drive transistor 4 is turned on, and the anode of the second organic EL element 3 is connected to the power supply line 8 to which the power supply voltage VDD is supplied. Then, a current flows through the second organic EL element 3. Since the anode potential of the second organic EL element 3 is reflected on the gate terminal of the first drive transistor 2 and becomes the power supply voltage VDD, the written data voltage even after the gate line 5 is set high and the gate transistor 5 is turned off. The state set by High is maintained while VDD and VSS are applied.

  Since the second organic EL element 3 does not contribute to light emission, the light emission state of the first organic EL element 1 determines the light emission state of the pixel.

  As a configuration method of the second organic EL element 3 that does not contribute to light emission, there is a method of forming an element that does not emit light different from the first organic EL element 1 (any element that exhibits resistance) may be used. Since it is necessary to form two elements of the organic EL element 1 and the organic EL element 3 that does not emit light, the manufacturing process becomes complicated. Therefore, it is preferable to form both of them with the same element, and to shield the second organic EL element 3 from light emitted from the light emitting surface by shielding light with a wiring for forming a pixel circuit.

  In the case of a top emission structure in which light is extracted to the side opposite to the pixel circuit side, the pixel circuit is formed by using a glass substrate coated with a light shielding film such as a black matrix to shield the second organic EL element 3 as a counter substrate. It may be shielded from light by sticking to the formed substrate.

  In any case, since the second organic EL element 3 does not contribute to light emission, the arrangement and wiring are performed so that the light emission area can be reduced and the light emission area of the first organic EL element 1 that emits light can be ensured as shown in FIG. 1B. It is preferable to do.

  FIG. 2 includes a pixel memory array 10 in which the pixels 13 shown in FIGS. 1A and 1B are arranged in a matrix, a gate driver 11 that drives the gate line 6, and a data driver 12 that drives the data line 7. The overall structure of the organic EL display is shown. The power supply line 8 and the cathode electrode 9 are shared by all pixels, and VDD and VSS are supplied from the outside, respectively.

  When a high-performance transistor manufactured by a process such as low-temperature polysilicon is used, the gate driver 11 and the data driver 12 can be formed on the same glass substrate as the pixel 13, but in digital driving, a frame image is divided into a plurality of subframes. A frame memory is required to divide. For this reason, it is more realistic to configure the data driver 12 as a driver IC and form the gate driver 11 on the same glass substrate as that of the pixels 13, so that the following description is based on this configuration.

  FIG. 3 shows the internal configuration of the data driver 12. Input data input from the external input to the input processing unit 14 is in units of 1 to several pixels obtained by adding red (R), green (G), blue (B), or white (W) to a full color display. The video data to be transferred and the clock signal and timing signal to transfer them. The video data in the input data is accumulated as one line of video data by the input processing unit 14 and transferred to the frame memory 15 and stored in units of lines. The video data for one screen stored in the frame memory 15 is read in line units, and is output to the organic EL panel 17 by the output processing unit 16 in line units. The organic EL panel 17 reflects the supplied video data on the display. However, description of timing signals stored in the frame memory 15 and timing signals for reading and outputting to the organic EL panel 17 is omitted here.

  As described above, in the configuration in which the frame memory 15 is introduced between the input processing unit 14 and the output processing unit 16, once the video data is stored in the frame memory 15, the organic EL does not have to be input from the outside. Video data can be supplied to the panel 17 from the frame memory 15. For this reason, it is not necessary to continue inputting video data from the outside in order to continue the display. As a result, the power consumption required for data transfer from the outside can be reduced, so that it is often used in LCDs (Liquid Crystal Display) mounted on portable terminals that require low power consumption.

  In the case of digital driving, since each subframe data is updated in units of one screen in each subframe period, power consumption due to scanning increases. However, in the present embodiment, as shown in FIGS. 1A and 1B, a static memory that does not need to be refreshed is introduced into the pixel and driven by the method described below. As a result, power consumption can be reduced even in digital driving.

  In general, there are many opportunities to display images and videos on portable terminals such as portable notebook computers, cellular phones, and portable music players, but functional displays that facilitate simple operations such as e-mail and menu screens. There are many cases where Since the conventional pixel circuit does not have a built-in static memory, there is almost no change in the image, and even in the case of a simple image for providing a function, it is necessary to always refresh at a certain cycle. It was. Therefore, even when the display does not change, the power for refreshing is always consumed. For this reason, extra power is consumed in the conventional analog-driven pixel circuit. However, since the power consumption is higher in digital driving, the refresh operation should be avoided as much as possible.

  If a static memory is introduced inside the pixel circuit, the data storage capacity is small as 1 bit, but once it is written, it is retained unless the power is turned off. Therefore, the refresh operation can be avoided by actively using this function.

  Most e-mails, menu screens, etc. are often composed of black characters on a white background, and are characterized in that only the characters typed or selected by the user are updated. In consideration of this feature, the power consumption can be further reduced by combining the pixel circuit of FIG. 1 in which a static memory is introduced in the pixel circuit and the partial update process for partially rewriting the video. This point will be described in more detail with reference to FIG.

  FIG. 4 shows a video stored in a frame memory 15 built in the data driver 12 capable of storing 7-bit data per pixel and a pixel memory array 10 capable of storing 1-bit data per pixel. An example of partially updating is shown.

  Of the 7-bit data stored in the frame memory 15, the E0 bit is used for 1-bit pixel memory display, and the remaining D0 to D5 are used for 6-bit multi-gradation display. Thus, the frame memory 15 is configured to store two types of data simultaneously.

  Consider a case where both the area A and the area B are displayed in the 1-bit pixel memory display mode and only the area A is updated. When an external signal is input to update the E0 bit in the area A in the frame memory 15 and reflect it in the display, the 7-bit data from the uppermost line M in the area A is sequentially sent from the frame memory 15 to the bottom. Read up to line N.

  When E0 is selected by setting the data selection signal for specifying whether E0 or D0 to D5 is selected from 7-bit data to High from lines M to N, the data of E0 is output from the output processing unit 16 to the pixel memory array 10. The data in the M to N areas of the line of the pixel memory array 10 is updated with the data of E0 in the frame memory 15. Note that the data is actually updated only in the area A, and the same data is rewritten in the area B.

  When the region A is in the multi-gradation display mode and the region B is in the 1-bit pixel memory display mode, the region A is updated in the multi-gradation display mode from the lines M to N. In this case, the data selection signal becomes Low in the area A, and D0 to D5 are selected at that time. The portion of region A is updated with the respective subframe data in each subframe, but the portion of region B is rewritten with the same data.

  When the region B is in the multi-tone display mode, the multi-tone display mode is set on the entire screen. In this case, the data selection signal is Low on all lines.

  As described above, when a specific part is updated in the 1-bit single-color pixel memory display mode or when a specific area is displayed in multiple gradations, the area to be updated is limited, so that the refresh operation is minimized. Power consumption can be further reduced.

  The gate driver 11 plays an important role in such partial update processing. If the gate driver 11 has a configuration with a built-in decoder, any line can be directly accessed, so that flexibility is high and partial updating is easy. For example, when accessing up to 256 lines, if 8 bit data (selection data) for a line to be selected is input to the 8 bit control line, the line to be directly selected can be designated one by one. As described above, the decoder is effective when random addressing is frequently used, such as a memory. However, in a display in which sequential addressing that normally accesses in order from the top line to the bottom line is used, control is somewhat complicated and overhead is large.

  In sequential addressing, a shift register is used, and the address can be updated (+1) by inputting one clock. However, in random addressing, the counted up address must always be designated.

  Further, when the number of lines increases, the address increases, so that the decoding circuit becomes large and the operation speed also becomes slow. Therefore, when applied to a high-resolution display, it is desirable to use a higher-performance transistor.

  As shown in FIG. 2, it is more effective if the gate driver 11 is not formed on the same glass substrate as the pixel 13 and is configured as a driver IC or incorporated in the data driver 12.

  Further, partial update processing can be performed more effectively by dividing the gate driver 11 as shown in FIG. 5 by sequential addressing using a shift register.

  In FIG. 5, the pixel memory array 10 is divided into three blocks of an upper part (a), a middle part (b), and a lower part (c), and the gate driver 11 drives the gate line of the upper part a of the pixel memory array 10. The structure is divided into an upper gate driver 11a, a middle gate driver 11b for driving the middle part, and a lower gate driver 11c for driving the lower part. However, in FIG. 5, the clocks input to the shift register and the enable control lines enb1 to enb3 that reflect the output of the shift register on the gate line are shared by the three divided gate drivers 11a, 11b, and 11c. Instead, they may be introduced independently and driven independently.

  A selection pulse is supplied from the input ain to the upper gate driver 11a, from the input bin to the middle gate driver 11b, and from the input cin to the lower gate driver 11c. This selection pulse is a clock (horizontal synchronization signal or Are transferred in the shift register in accordance with the synchronizing signal), and the selected lines are sequentially changed. Further, the lines to be selected can be determined by the enable signals enb1 to enb1.

  In a mode in which data is supplied to the entire organic EL panel and displayed, a selection pulse is input from the input ain, and two connection signals con_ab and con_bc described later are set to High. As a result, the gate driver 11 operates as a whole, the selection pulses are sequentially transferred to the shift register, and the gate lines are sequentially selected. On the other hand, when it is desired to update only the upper part (a), the connection signals con_ab and con_bc are set to Low and a selection pulse is supplied from ain. An example in which only the middle part (b) or the middle part (b) and the lower part (c) are updated will be described.

  Two connection signals con_ab and con_bc are signals for controlling the connection between the divided gate drivers 11a and 11b and the connection between 11b and 11c, respectively, and both are connected when High and are divided when Low. When divided, the selection pulses input to the shift registers of the divided gate drivers 11b and 11c can be input from bin and cin from the outside.

  As an example, consider a case where the area A displayed in the pixel memory display mode is updated. Since the area A is entirely included in the block b, only the divided gate driver 11b has to be operated. At this time, the non-selection pulse is continuously input to the inputs ain and cin of the other divided gate drivers 11a and 11c, and control is performed so that the pixels of the blocks a and c are not updated.

  The selection pulse is input to the input bin of the divided gate driver 11b, and the clock is input until the selection pulse is stored in the shift register of the line L, thereby selecting the line L and updating the data of the line L. When this is repeated up to the line M, the data in the area A of the pixel memory array is updated by the method shown in FIG.

  As described above, in the update of only the 1-bit data, only the portion of the area A can be updated, or the entire block b can be simply updated.

  In this case, all of enb1 to enb3 may be always set to High so that selection data of the shift register (data for selecting the gate line of each line (for example, Low)) is reflected as it is in the output. Any one of enb1 to 3 that enables each line may be selected to reflect the selection data of the shift register in the output. By selecting one of the enable signals enb1 to enb3, every third gate line is selected, and by sequentially changing the selectable enable signals enb1 to enb3, the lines to be selected every third are sequentially changed. Can do.

  When the area A is multi-gradation display, all the blocks b are to be updated, and are controlled by digital drive by the divided gate driver 11b. Since the control method of the gate driver 11b at the time of digital driving is described in detail in Patent Document 1, description thereof is omitted.

  In the case where a partial update process is performed on an area extending over two blocks as in the area B in the figure, first, the connection signal con_bc is set to High, the divided gate drivers 11b and 11c are connected, and the block b and the block c are combined into one block. To perform partial update processing.

  In this case, if the area B is the 1-bit pixel memory display mode, only the area B can be updated. However, in the multi-gradation display mode, all the blocks b and c are to be updated.

  In the above example, the number of divisions is three. However, the number of divisions may be divided into upper and lower two, or may be divided into four or more. It is also possible to arrange some of the divided gate drivers on the left side and the rest on the right side.

  When a divided gate driver is used in this way, partial update processing is possible even in sequential addressing by a shift register, but the frequency of partial update processing is not so high because the degree of freedom of the update area is narrow compared to random addressing by a decoder. Not suitable for many cases. Conversely, when there are many multi-gradation displays, sequential addressing is more suitable than random addressing, so it is desirable to select the configuration according to the usage environment of the display.

  In any case, by actively introducing such a partial update process, in the case of the pixel memory display mode, refresh is not required in the case of the same display. For this reason, since refresh frequency can be reduced, the organic EL display driven by digital drive can be made low in power consumption.

(Embodiment 2)
6A and 6B show a pixel circuit that can further reduce power consumption by introducing an N-type switching transistor 18 between the second organic EL element 3 and the second drive transistor 4.

  In the pixel circuit shown in FIG. 6A, the source terminal of the N-type switching transistor 18 is connected to the anode of the second organic EL element 3, the gate terminal thereof is the drain terminal of the first driving transistor 2, and the anode of the first organic EL element 1. The drain terminal of the second driving transistor 4 is connected to the drain terminal of the second driving transistor 4, the gate terminal of the first driving transistor 2, and the source terminal of the gate transistor 5.

  Since the N-type switching transistor 18 is disposed between the second drive transistor 4 and the second organic EL element 3, the first organic EL element 1 is turned off, that is, when the second drive transistor 4 is turned on. Since the switching transistor 18 cuts the current flowing through the second organic EL element 3, no extra current flows.

  In FIG. 6B, the second organic EL element 3 is omitted from the pixel circuit of FIG. 6A, and the source terminal of the switching transistor 18 is directly connected to the cathode.

  By introducing the switching transistor 18 in this way, it is possible to prevent unnecessary current consumption when the first organic EL element 1 is turned off, so that the power consumption can be further reduced.

  In the above description, the first drive transistor, the second drive transistor, and the gate transistor are P-type. However, these transistors can be N-type. When each driving transistor is an N-type, it is preferable to arrange the organic EL element between the positive power source and not between the driving transistor and the negative power source. At this time, it is also preferable to take measures for maintaining the voltage applied to the organic EL element at a predetermined value. If the gate transistor 5 is an N type, the polarity of the gate line 6 may be reversed.

FIG. 2 is a pixel equivalent circuit diagram of the first embodiment. FIG. 2 is a pixel equivalent circuit diagram and a layout wiring diagram of the first embodiment. It is a whole block diagram of an organic EL display. It is an internal block diagram of a data driver. It is partial update process explanatory drawing. It is a gate driver internal block diagram. 6 is a pixel equivalent circuit diagram of Embodiment 2. FIG. 6 is a pixel equivalent circuit diagram of another example of Embodiment 2. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 1st organic EL element, 2 1st drive transistor, 3nd 2nd organic EL element, 4 2nd drive transistor, 5 gate transistor, 6 gate line, 7 data line, 8 power supply line, 9 cathode electrode, 10 pixel memory array 11 gate driver, 12 data driver, 13 pixels, 14 input processing unit, 15 frame memory, 16 output processing unit, 17 organic EL panel, 18 switch transistor.

Claims (10)

An active matrix display panel,
Each pixel is
A select transistor for controlling the input of digital data from the data line;
It has a pair of transistors and is arranged between the positive power supply and the negative power supply. When the selection transistor is turned on, one transistor is turned on and the other transistor is turned off. Static memory to store incoming digital data,
A light emitting element that emits light by a current flowing through one of the pair of transistors of the static memory; and
Have
An active matrix display panel, wherein light emission of the light emitting element is controlled according to the input data. The active matrix display panel according to claim 1,
The static memory is
A first transistor having one end connected to a power supply, a gate connected to an output side of the selection transistor, and being turned on / off by the digital data;
A second transistor having one end connected to a power source, a gate connected to the other end of the first transistor, and being turned on / off according to an on / off state of the first transistor;
Have
The other end of the second transistor is connected to the gate of the first transistor and the output side of the selection transistor;
An active matrix display panel, wherein the first transistor and the second transistor are complementarily turned on in accordance with input digital data. The active matrix display panel according to claim 2,
An active matrix display panel, wherein a light emitting element is connected to each of the other ends of the first transistor and the second transistor, and one of the two light emitting elements emits light and the other is shielded. In claim 3,
Between the light-shielding light-emitting element and one of the first or second transistor connected to the light-shielded light-emitting element, a gate is connected to the other end of the first or second transistor. An active matrix display characterized in that a switching transistor having a polarity opposite to that of the other one of the first or second transistors is provided, and the current supply to the light-emitting element that is shielded from light is cut off by the switching transistor. panel. The active matrix display panel according to claim 2,
A light emitting element is connected to the other end of the first transistor and the second transistor;
The other of the first and second transistors is provided with a switching transistor whose gate is connected to the other end of the first or second transistor and whose polarity is opposite to that of the first or second transistor. An active matrix display panel characterized in that when the other of the first or second transistor is turned on, the current flowing therethrough is cut off by the switching transistor. In the active matrix type display panel according to any one of claims 1 to 5,
An active matrix display panel comprising a frame memory for storing at least one frame of digital data, wherein the digital data is supplied from the frame memory to a data line. The active matrix display panel according to claim 6,
A gate line is arranged for each row of pixels, and the gate line is driven by a gate driver to control the selection transistor,
The active matrix display panel, wherein the gate driver can sequentially select only a predetermined range of rows, and can update data of only pixels within the selected range. The active matrix display panel according to claim 6 or 7,
The frame memory can store both 1-bit digital data and multi-bit digital data corresponding to each pixel. In the monochrome pixel memory display mode, 1-bit digital data is stored in one frame. In the multi-grayscale mode, an active matrix display panel, wherein digital data of a plurality of bits is supplied to the data lines in a plurality of subframes. The active matrix display panel according to claim 8, wherein
An active matrix characterized in that either one-bit digital data or a plurality of bits of digital data from the frame memory can be selected for a data line of each column, and a display mode can be partially changed. Type display panel. In the active matrix type display panel according to any one of claims 1 to 9,
The active matrix display panel, wherein the light emitting element is an organic EL element.

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