JP5281760B2 - Active matrix display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a power source line conform to a memory pixel. <P>SOLUTION: Unit pixels 11 are arranged in a matrix form and their display is controlled. The unit pixels 11 are provided with a plurality of memory pixels 10 each having a one-bit memory, which are arranged in two or more lines. A power source line 8 is wired corresponding to each of the lines of the memory pixels 10. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to an active matrix display device in which unit pixels are arranged in a matrix and the display is controlled.

  In any form of display device that receives digital input, it is necessary to generate emission intensity, which is an analog output, in accordance with input digital data, and is provided with digital-analog conversion (DA conversion) means.

  Patent Documents 1 and 2 disclose active matrix organic EL panels that are digitally driven. In Patent Document 1, DA conversion is performed by changing the pulse width of the light emission period. In Patent Document 2, DA conversion is realized by using divided pixels having different light emission intensities.

  Here, the pixels disclosed in Patent Documents 1 and 2 have a storage capacitor, but written data can be stored only for a certain period. For this reason, in order to always maintain the light emission intensity corresponding to the data, an externally readable / writable memory is provided, and the pixel is always refreshed (operation for writing data to the pixel at a constant cycle) by the memory data. There is a need. In particular, when performing DA conversion in the light emission period, it is desirable to refresh at a frequency of 60 Hz or more in order to suppress flicker.

  On the other hand, once static memory is introduced into a pixel, data once written is held. Therefore, a part of the refresh operation can be omitted, and an external frame memory provided for refresh is not required, and the cost can be reduced.

  As in the above-mentioned Patent Document 1, when DA conversion is performed in a light emission period of a subframe, the number of memory bits per pixel is small, so that a small size and high definition can be achieved. In addition, because of its small size, the wiring capacity is small even when the light emission period is changed at a high frequency, so that it has little influence on power consumption and is suitable for small mobile applications such as cellular phones.

  In addition, as in Patent Document 2, in the case of DA conversion by hardware using multi-bit divided pixels, it is necessary to introduce a multi-bit memory per pixel. For this reason, although it is difficult to achieve high definition, it becomes easy to introduce a multi-bit memory as the pixel pitch increases as the size increases. Furthermore, because of the large size, the wiring capacity increases and the power consumption increases. However, if the frequency of accessing the pixels can be reduced, a large-sized television or monitor with lower power consumption and lower cost can be realized.

  Further, when a static memory is introduced into a pixel, read / write access is possible, so that a function such as reading and rewriting data in a necessary area can be provided, and the range of control is widened. There is a display method in which a moving image such as a TV is displayed on a display, whether it is small or large, and there is a display method in which only a target area of a user's action is updated like a display screen of a personal computer. If the above functions are effectively used in consideration of display characteristics, the performance as a display such as low power consumption and multi-gradation can be improved.

JP 2005-331891 A Japanese Patent Laid-Open No. 11-73158

  Here, in Patent Document 2, one pixel is composed of a plurality of divided pixels, and these divided pixels all share the same power supply line. Divided pixels with different emission intensity due to the difference in emission area are supplied with power from the same power line. Therefore, by changing the specifications of the power line according to the divided pixels, different emission intensity can be generated, The wiring width could not be changed according to the situation.

The present invention is an active matrix display device in which unit pixels are arranged in a matrix and control the display thereof. The unit pixel includes a plurality of memory pixels having a 1-bit memory, and the plurality of memories. The pixels are arranged in two or more columns, and a power supply line is wired corresponding to each column of the memory pixels, and a power supply line connected to pixels adjacent in the row direction or the column direction arranged in the unit pixel is The memory pixels having different wiring widths or supply voltages and connected to adjacent power supply lines are arranged so that the light emission areas have a predetermined ratio, and generate a desired light emission intensity ratio. To do.

  Thus, according to the present invention, a unit pixel is composed of a plurality of memory pixels, and two or more power supply lines for supplying power to the memory pixels in the unit pixel are provided. Therefore, the voltage, width, etc. of the power supply line can be set appropriately according to the memory pixel to be connected.

  FIG. 1A shows an equivalent circuit diagram of a memory pixel including a static memory using only a P-type transistor, and FIG. 1B shows a layout diagram viewed from the surface on which the transistor is formed.

  One memory pixel includes a first organic EL element 1 that contributes to light emission, a first drive transistor 2 that drives it, a second organic EL element 3 that does not contribute to light emission, a second drive transistor 4 that drives it, and The gate transistor 5 is turned on / off in accordance with a selection signal supplied to the gate line 6 and is turned on to supply the data voltage supplied to the data line 7 to the gate terminal of the first drive transistor 2.

  The anode of the first organic EL element 1 is connected to the drain terminal of the first driving transistor 2 and the gate terminal of the second driving transistor 4, and the gate terminal of the first driving transistor 2 is the anode of the second organic EL element 3. Are connected to the drain terminal of the second drive transistor 4 and the source terminal of the gate transistor 5, the gate terminal of the gate transistor 5 is connected to the gate line 6, and the drain terminal is connected to the data line 7. The source terminals of the first driving transistor 2 and the second driving transistor 4 are connected to the power supply line 8, and the cathodes of the first organic EL element 1 and the second organic EL element 3 are connected to the cathode electrode 9 to form the memory pixel 10. Has been.

  The second organic EL element 3 is shielded from light by a wiring metal, a black matrix, or the like, or formed as an organic EL element that does not emit light, so that light emission is not emitted to the outside. Therefore, the light emission state of the first organic EL element 1 determines the lighting state of the memory pixel 10.

  When writing data to the memory pixel 10, a write selection signal (lower Low level) is supplied to the gate line 6, and when the gate transistor 5 is turned on with a lower on-resistance, the data signal supplied to the data line 7 The state of one driving transistor is determined, and light emission / non-light emission of the first organic EL element 1 is controlled.

  When the gate potential of the first drive transistor 2 is High, that is, when the first drive transistor 2 is off, the second drive transistor 4 is on, and Low data is supplied to the data line 7, the first drive transistor 2 Since the gate transistor 5 has a lower on-resistance than the second drive transistor 4, even when the second drive transistor 4 is on, the gate potential is guided to the Low side, which is the potential of the data line 7, The drive transistor 2 is turned on, and a current flows through the first organic EL element 1 to emit light. At the same time, the second drive transistor 4 is turned off when the first drive transistor 2 is turned on, and the gate potential of the first drive transistor 2 is lowered to near the cathode potential at which no current flows through the second organic EL element 3. This potential is continuously applied to the gate potential of the first drive transistor 2 even when the gate transistor 5 is turned off, so that the lighting state of the first organic EL element 1 is maintained even if the refresh operation is not performed periodically. Is done.

  When the gate potential of the first drive transistor 2 is low, that is, when the first drive transistor 2 is on, the second drive transistor 4 is off, and high data is supplied to the data line 7, the gate transistor 5 is lower. When the current is quickly supplied to the second organic EL element 3 due to the ON resistance and the gate potential of the first driving transistor 2 is set to High, the first driving transistor 2 is turned off and the first organic EL element 1 is turned off. . Since the anode potential of the first organic EL element 1 drops to near the cathode potential and is supplied to the gate terminal of the second drive transistor 4, the second drive transistor 4 is turned on, and a current flows through the second organic EL element 3. However, the gate potential of the first drive transistor 2 is kept high. That is, even after the gate transistor 5 is turned off, the non-lighting state of the first organic EL element 1 is continuously maintained. Although the second organic EL element 3 does not contribute to light emission and plays a role of maintaining the gate potential of the first drive transistor 2, the current flowing through the second organic EL element consumes power, and thus is shown in FIG. 1B. As described above, it is desirable that the light emitting area of the second organic EL element 3 is formed to be sufficiently smaller than that of the first organic EL element 1.

  In the case of reading, the data line 7 is precharged to a low level, and a read selection signal (higher low level) is supplied to the gate line 6. When the gate potential of the first drive transistor 2 is high, that is, when the first drive transistor 2 is off and the second drive transistor 4 is on, the gate transistor 5 has higher on-resistance than the second drive transistor 2. The data line 7 precharged with low data is charged high while the gate potential of the first driving transistor 2 is maintained high by resistance voltage division.

  When the gate potential of the first driving transistor 2 is Low, the data line 7 precharged with Low does not change for a long time. Therefore, if the data line 7 is High after a certain time has elapsed, the memory In this case, it can be determined that Low data is written if the High data remains Low.

  In this manner, by applying different selection voltages for writing and reading to the gate line 6, data can be read and written using the memory pixels of FIGS. 1A and 1B.

  2A and 2B show layout diagrams of a pixel 11 having a 6-bit DA conversion function using six memory pixels 10 of FIGS. 1A and 1B. In the case of full color, at least three colors are provided for one pixel, such as R (red), G (green), and B (blue).

  As shown in FIG. 2A and FIG. 2B, when a plurality of memory pixels 10 having different light emitting areas are provided in one pixel 11 to realize area gradation, the logical operation of reading / writing as described above for each memory pixel 10 is as follows. Even if they are the same, the light emission intensity to be output differs depending on the light emission area of each memory pixel. Therefore, it is an important point that the light emitting area is effectively formed in a desired ratio in each memory pixel.

  In FIG. 2A, the light emission areas of the first organic EL elements 1-0 to 1-5, which are constituent elements of the memory pixels 10-0 to 10-5 included in the pixel 11, are 1: 2: 4: 8: 16, respectively. : 32 is an example that is effectively formed so that the same potential is supplied to the power supply lines 8-0 and 8-1, and each of the memory pixels 10-0 to 10-5 has the same relationship. The emission intensity has a ratio similar to the area.

  When the area gradation is applied, it is necessary to sufficiently consider the case where the light emitting region of the first organic EL element 1-0 of the LSB (Least Significant Bit) memory pixel is extremely smaller than the transistor formation region. In this example, the ratio of MSB (Most Significant Bit) and LSB is 32: 1, and the light emitting region of the memory pixel of LSB is considerably smaller than the transistor formation region.

  Since the formation area of the transistor circuit should occupy the same area in all the memory pixels, in order to distribute the light emitting area of the organic EL element so as to have a desired ratio, for example, as shown in FIG. It is effective to form a sub-matrix and redistribute the light emitting area in each memory pixel. The reason for thinking in this way is as follows.

  For example, the organic EL elements 1-5 and 1-2 need to be formed with a light emission area ratio of 32: 4 (8: 1), but the two memory pixels should be adjacent to each other. This is because the organic EL element 1-5 can sufficiently expand the light emitting area by using an unnecessary organic EL formable region of the organic EL element 1-2. The same applies to the organic EL elements 1-4 and 1-1, 1-3 and 1-0. The paired memory pixels are arranged in the vertical direction, and the vertical lengths are adjusted so that the light emitting areas of the organic EL elements 1-5, 1-4, and 1-3 are 4: 2: 1. Thus, even in the memory pixel having the same transistor region, the light emitting area can be effectively formed in a desired ratio.

  Regarding the first organic EL elements 1-5, 1-4, and 1-3 in FIG. 2A, in the case of a bottom emission type organic EL element that extracts light emitted to the opposite side of the transistor formation surface, a part of the light emitting region is a power line 8. -1 and 8-0 and data lines 7-1 and 7-0, the light emission area is substantially reduced. Therefore, it is necessary to adjust the light emission area in consideration of the wiring region. In the case of a top emission type organic EL element to be taken out, the consideration is not so necessary.

  Alternatively, as shown in FIG. 2B, the light emission area of the first organic EL element is made the same between 1-3 and 1-0, 1-4 and 1-1, 1-5 and 1-2, and the power line 8-0, A desired light emission intensity ratio may be generated by changing the light emitting area and the power supply voltage applied to the organic EL element, such as applying different potentials to 8-1. For example, when the potential V1 higher than the potential V0 of the power supply line 8-0 is applied to the power supply line 8-1, the first organic EL element 1-5 has a light emission intensity higher than that of 1-2, which is 8: 1. Thus, if the power supply potentials V1 and V0 of the power supply lines 8-1 and 8-0 are determined, a 6-bit gradation can be generated without contradiction as in FIG. 2A. However, the first organic EL elements 1-5, 1-4, 1-3 that emit light when given a higher potential V1, and 1-2, 1-1, 1-0 that emit light when given a lower potential V0. Since the current density at the time of light emission is different, the former is more rapidly deteriorated when light is emitted simultaneously. Thus, the deterioration of the organic EL element can be made uniform by alternately switching the potentials V1 and V0 supplied to the power supply lines 8-1 and 8-0. At this time, since the light emission intensity changes when the potential is switched, control is performed so that bit data corresponding to the memory pixel that generates each light emission intensity is written. That is, when V1 is applied to the power supply line 8-1 and V0 is applied to 8-0, the fifth bit data is reflected in the memory pixel 10-5, while the second bit data is reflected in the memory pixel 10-5. When V0 is applied to 8-1 and V1 is applied to 8-0, the second bit data is written to the memory pixel 10-5, and the bit data is written to each memory pixel so that the fifth bit data is reflected to 10-2. It is.

  When bit data is determined for each memory pixel in hardware as shown in FIG. 2A, a power supply line 8- supplying current to the first organic EL elements 1-5, 1-4, 1-3 of the upper 3 bits. 1 is made wider than the width of the power supply line 8-0 that supplies current to the first organic EL elements 1-2, 1-1, 1-0 of the lower 3 bits, and the voltage resulting from the flow of 8 times the current flows. You may suppress a fall.

  In this way, organic EL elements having different light emitting areas can be easily formed by arranging memory pixels in a sub-matrix of 3 rows and 2 columns in one pixel and leaving room for extending the light emitting area vertically and horizontally. It becomes possible to do.

  When arranged in a sub-matrix of 3 rows and 2 columns, the number of gate lines 6 for accessing each memory pixel may be three (6-2, 6-1, 6-0). If the memory pixels are arranged in 6 rows and 1 column, six gate lines 6 are required for each pixel, and the circuit scale of a gate selection decoder, which will be described later, for selecting and controlling the gate lines 6 also increases. Thus, the sub-matrix configuration is advantageous also from the viewpoint of the scale of the gate selection decoder. FIG. 2 shows only an example of a submatrix configuration including 6-bit memory pixels, but in the case of 4 bits, four memory pixels, for example, 10-1, 10-2, 10-4, 10-5. Needless to say, the same concept applies to the case of 2-bit pixels having only the memory pixels 10-5 and 10-2, for example.

  3 includes a pixel array 12 in which the pixels 11 of FIG. 2 are arranged in a matrix, a gate selection decoder 13 that controls selection / non-selection of the gate line 6, and bit data is output to and input from the pixel array 12. An overall configuration of an organic EL display including a possible data driver 14 and a bit selector 15 for switching bit data supplied to the data line 7 is shown.

  Often, the pixel array 12, the gate selection decoder 13, and the bit selector 15 are formed on the same substrate. However, if the data driver 14 is also formed on the same substrate, the cost can be further reduced. Alternatively, the data driver 14 may be composed of an IC.

  When displaying an image input from the outside, the data driver 14 converts the data transferred in dot units into line data, and outputs the data to the data lines 7-0 and 7-1 in line units. The data output to the data lines 7-0 and 7-1 is written to the pixels 11 of the line selected by the gate selection decoder 13, and this data writing is performed in bit units. That is, the bit selector 15 connects the output of the data driver 14 to the data line 7-1 when writing any of the upper 3 bits, and the bit selector 15 when writing any of the lower 3 bits. Connects the output of the data driver 14 to the data line 7-0. At the same time, if the bit data is the fifth or second bit, the gate line 6-2 is used, if the bit data is the fourth or first bit, the gate line 6-1 is used, and if the bit data is the third or 0th bit, the gate line 6-0 is used. Is selected by the decoder 13, and bit data corresponding to each memory pixel is written at a timing described later.

  Since the bit data once written is maintained in the memory pixel, it is not necessary to always operate the gate selection decoder 13 and write the data to the pixel at a constant cycle. The corresponding pixel 11 may be updated only when there is a video change. Therefore, it is not necessary to introduce a refresh frame memory inside or outside the data driver 14, and the display cost can be reduced.

  FIG. 4 shows the configuration of the gate selection decoder 13. Here, for the sake of simplicity of explanation, an example in which the pixel array shown in FIG. 2 drives a pixel array having two lines is shown. The gate selection decoder 13 includes a selection circuit 16 and a non-selection circuit 17, and drives a corresponding line Low from 3-bit address data {A0, B1, B0} and its complement data {A0b, B1b, B0b}. Then, all the lines that do not correspond are driven high to be unselected. The selection circuit 16 includes a selection decoding unit in which three P-type transistors are connected in series, and a selection voltage control unit that switches a selection voltage level by a write enable signal WE and a read enable signal RE, and the non-selection circuit 17 includes a P-type transistor. It consists of three non-select decoding units connected in parallel.

  The selection decoding unit is turned on when all three inputs are Low, and the non-selection decoding unit forms a logic that is turned off when all three inputs are High, both of which are address data {A0, B1, B0}. And their complement data {A0b, B1b, B0b} are in a complementary relationship. That is, among the 6 inputs {A0, A0b, B1, B1b, B0, B0b}, if the 3 inputs of the selected decoder 16 are connected to {C, D, E}, then 3 inputs of the unselected decoder Are connected to {c, d, e}. However, c = C's complement, d = D's complement, and e = E's complement. If the connection is made in this way, the non-selection circuit 17 is always turned off when the gate line is selected by the selection circuit 16, and the selection circuit 17 is always turned off when the selection is released by the selection circuit 16. Will be on. For example, when the first gate line 6-1 is selected, the selection decoding unit of the first gate line 6-1 is selected when the three inputs are address data {0, 0, 1}. May be {A0, B1, B0b}. At the same time, the non-selection circuit 17 uses the address data {0, 0, 1} to disconnect the first gate line 6-1 from the non-selection voltage VDD, so that the connection destination of the three inputs is {A0b, B1b, B0}. . As a result, Low is input to all inputs of the decoding unit 3 of the selection circuit 16, and High is input to all three inputs of the non-selection circuit 17, so that the first gate line 6-1 has address data {0, 0, 1} is selected without contradiction.

  The selection voltage control unit of the selection circuit 16 selects and reads a sufficiently low level (VSS1) necessary for writing by setting the write enable signal WE to Low and the read enable signal RE to High when writing is selected. At the time of selection, the low level (VSS2) suitable for reading is selected by setting the read enable signal RE to Low and the write enable signal WE to High. On the other hand, the non-selection circuit 17 is supplied with a high level (VDD) potential sufficient to deselect the gate line.

  The line address A0 determines which of the two lines is selected, and the bit address {B1, B0} specifies which bit of the memory pixel is to be written. For example, when writing the 0th bit data to the 0th bit memory pixel of the first gate line 6-0, {A0, B1, B0} is set to {0, 0, 0}, the write enable signal WE is Low, and the read enable By setting the signal RE to High, the selection circuit 16 of the first gate line 6-0 drives the first gate line 6-0 to Low enough for writing. At the same time, since {A0b, B1b, B0b} becomes {1, 1, 1}, the non-selection circuit 17 of the first gate line 6-0 is turned off and the first gate line 6-0 is driven as it is, and the data The 0th bit data supplied to the line 7-0 is written into the memory pixel. When the first bit data is written to the first bit memory pixel of the first gate line 6-1, if A 0 and B 1 are left as they are and B 0 is set to “1”, B 0 b becomes “0”, and the first gate line 6 At the same time, -1 is set to Low by the selection circuit 16, the non-selection circuit 17 is turned off, and the first gate line 6-1 is driven to Low. On the other hand, the selection of the first gate line 6-0 that has been selected is canceled by the selection circuit 16 when B0 becomes "1", and at the same time, B0b becomes "0". High is supplied and is not selected. Other lines other than the designated address are also deselected by the selection circuit 16 and driven to High by the non-selection circuit 17 to be unselected.

  When reading bit data from a memory pixel, after precharging the data line 7 to Low, the gate line is read and selected by setting the read enable signal RE to Low and the write enable signal WE to High, and the data at the same address is selected. It can be read out on the data line 7.

  As described above, the selection circuit 16 having the selection decoding unit in which the same type transistors are connected in series by the same number of bits as the address, and the non-selection circuit 17 having the non-selection decoding unit in which the same type transistors are connected in parallel. If a decoder formed using is used, all gate lines can be accessed for reading and writing at random.

  FIG. 4 shows an example of an address decoder having a 1-bit (2-line) line address. Even if the number of lines increases and an 8-bit (256-line) address decoder is required, the selection circuit 16 performs the decoding. The number of transistors connected in series in the unit may be 10 (line address 8 + bit address 2), and the number of transistors connected in parallel in the non-selection circuit 17 may be 10 to form a gate selection decoder.

  FIG. 5 shows a timing chart of bit data supplied from the data driver 14, control signals of the bit selector 15 (upper bit data selection signal, lower bit data selection signal), and gate line selection control by the decoder 13.

  Since the pixel of FIG. 2 can write 2-bit data supplied to the data lines 7-0 and 7-1 by selecting one gate line, the data driver 14 can write in the order of bit data that can be written by one selection. Output data. For example, when the fifth bit data D5 is output and Low is input to the bit selector 15 as the upper bit data selection signal, the output of the data driver 14 is connected to the data line 7-1 and the data D5 is supplied to the data line 7-1. Is done. Next, when the upper bit data selection signal is canceled (High) and the data D5 is held in the data line 7-1, the second bit data D2 is output from the data driver 14, and Low is input as the lower bit data selection signal. Since the output of the data driver 14 is connected to the data line 7-0, the data D2 is supplied to the data line 7-0. If the nth gate line 6-2 is selected while the data D5 and D2 are held in the data lines 7-0 and 7-1, the data D5 and D2 share the same gate line. 5. The data written in the memory pixel of the second bit and written in the memory pixel is determined by selecting a line other than the nth gate line 6-2.

  Thereafter, the fourth bit data, the first bit data, the third bit data, and the zeroth bit data are sequentially output from the data driver 14, but each bit data corresponds by controlling the bit selector 14 in the same manner. The data is supplied to the data line leading to the memory pixel, and the corresponding gate line is selected by the bit address selection, and the bit data writing of the nth line is completed. By repeating this, all the bit data of all the lines can be written into the memory pixels, and the data writing of the entire screen is completed.

  However, when it is small and high-definition is required, such as a mobile terminal, it is difficult to introduce a 6-bit memory pixel for each pixel. Therefore, only 3 bits are introduced to one pixel as shown in FIG. Therefore, it is better to omit part of the external memory. However, when generating a 6-bit gradation, it is necessary to provide a memory of 3 bits or more inside or outside the data driver 14.

  In the pixel of FIG. 6, the light emitting areas of the first organic EL elements 1-2, 1-1, 1-0 are set to approximately 2: 1: 1. Unlike FIG. 2, memory pixels are configured in 3 rows and 1 column. Has been. More precisely, in order to generate a 6-bit gradation, the ratio of the first organic EL elements 1-1 and 1-0 of the memory pixels 10-1 and 10-0 in FIG. 6 is 16:15. Although it is desirable, at least the first organic EL element 1-0 should be equal to or larger than 1-1. As will be described later, the brightness of the memory pixel 10-0 can be adjusted by changing the light emission period according to the subframe. Even with the pixel configuration as shown in FIG. 6, read / write control can be effectively performed by using the gate selection decoder 13.

  FIG. 7 shows a timing chart of digital driving for generating a 6-bit gradation using a 3-bit memory pixel and a 3-bit external memory included in the pixel of FIG. In the example of FIG. 7, 10-2 and 10-1 are allocated exclusively for the most significant 2 bits among the 3-bit memory pixels, and 10-0 is shared by the remaining 4 bits.

First, in the memory writing period of FIG. 7, upper 3 bit data is written into a 3 bit memory pixel, and the remaining lower 3 bit data is written to the outside, for example, a memory introduced in the data driver 14. The procedure for writing to the memory pixel is the same as in FIG. 5, except that one pixel has only a 3-bit memory pixel, so that the bit selector 15 is not necessary.
When the memory writing period ends, the upper 2 bits of bit data are continuously held by the dedicated memory pixels 10-2 and 10-1 unless the external video data is input and need to be updated. . For the remaining lower 4 bits, a 4-bit gradation is reproduced using the memory pixel 10-0 and the subframes SF0 to SF3.

  Since it is not necessary to access the memory pixels 10-2 and 10-1 in the display period by the subframe, the bit address {B1, B0} shown in FIG. 4 is always fixed to {0, 0} and the access is performed. It may be limited to the memory pixel 10-0. Thereby, access to the memory pixels 10-2 and 10-1 is avoided.

  Immediately after writing to the memory, the third bit data D3 is written in the memory pixel 10-0, and the second bit data D2 is read from the external memory at the timing when the first second-bit subframe SF2 starts. If this is written in the memory pixel 10-0 as it is, the third bit data D3 is overwritten, and the third bit data is lost. This is because the third bit data is not stored anywhere other than the memory pixel 10-0. Therefore, the second bit data D2 of the nth line once read from the external memory is saved in a line memory or the like, and the memory pixel 10 of the nth line is stored at the address where the second bit data D2 is stored. If the third bit data D3 read from −0 is stored, the third bit data D3 is not lost. The validity can be understood from the fact that the total capacity of the memory pixel and the external memory is the same 6 bits.

  Similarly, when the first bit sub-frame SF1 is started, the first bit data D1 is read from the external memory and saved, and the second bit data read from the memory pixel 10-0 is stored in the read external memory address. Store. By repeating the same process in other subframe periods, a 4-bit gradation can be reproduced using the memory pixel 10-0 without losing any bit data.

  If a 4-bit memory is introduced externally, it is not necessary to read out bit data from the memory pixel as described above and to drive while exchanging the bit data with the external memory. That is, the third bit data D3 is written in both the memory pixel and the external memory or only in the external memory in the memory writing period, and the third to 0th bits read from the external memory having 4 bits in each subframe period. The 4-bit data up to the data may be overwritten and written in the memory pixel 10-0 in the subframe order.

  In this case, since only the write control is required for the memory pixel, the selection voltage need not be switched by the write enable signal WE and the read enable signal RE, and the selection voltage control unit of the selection circuit 16 can be omitted.

  Use of the memory pixel and the decoder 13 in FIG. 6 has an advantage that the area for digital driving by the subframe can be limited only to the display area where multi-gradation display is necessary. For example, consider the case where the upper half of the display area is used as a natural image display area such as a photograph and the lower half is used as a text area such as an e-mail, as often appears on a mobile terminal. Since the lower half text area does not need to be displayed in multiple gradations, the decoder 13 may be operated so that only the changed portion is updated using only two bits of the memory pixels 10-2 and 10-1. Since there is a possibility that a portion with a change may occur at random, the decoder can be directly accessed as compared with a selection means that sequentially selects such as a shift register, which is efficient.

  The upper half needs to be periodically updated with bit data corresponding to each subframe by digital drive, but it is not necessary to update the entire screen, so there is no need to operate the decoder 13 from top to bottom, and data writing Power consumption can be reduced.

  Further, by applying the decoding circuit of FIG. 4, the data driver 14 may be formed on the same substrate as the memory pixel by forming a data selection decoder using P-type transistors as shown in FIG.

In FIG. 8, one selection circuit 18 and one non-selection circuit 19 operated by the address data {A1, A0} and its complement data {A1b, A0b} are provided for each of four columns of data lines. An example is shown in which the switch 20 is controlled by a non-selection circuit so that four columns of data lines can be simultaneously accessed via the data buses X0 to X3. The operation principle is the same as in FIG. In the example of FIG. 8, since the address is 2 bits, it is possible to freely access four addresses. For example, when the address data {A1, A0} is {0, 0}, the complement data {A1b, A0b} is {1, 1}, and Low (VSS) is applied to the input of the switch 20 at address 0, and the address The 0 data line group is simultaneously connected to the data buses X0 to X3 via the switch 20. During this time, if bit data for four columns is supplied to the data buses X0 to X3, data is supplied to the four data lines 7 at a time. Subsequently, when the address data {A1, A0} is changed to {0, 1}, the complement data {A1b, A0b} is also updated to {1, 0}, and the selection of the address 0 is canceled by the selection circuit 18 and is not selected. The circuit 19 supplies High (VDD) to the input of the switch 20, and the data line group at the address 0 is disconnected from the data buses X0 to X3. At the same time, the switch 20 is turned on by the selection circuit 18 of the address 1, the data line group of the address 1 is connected to the data buses X0 to X3, and the bit data on the data bus is supplied to the respective data lines 7.
When data is read from the memory pixels onto the data buses X0 to X3, the corresponding gate line is read and selected, and the data of the memory pixel is read onto the data line, but the address specified by the address data {A1, A0}. Only the data lines are connected to the data buses X0 to X3, read onto the data bus, and accessed from the outside.

  By incorporating a data selection decoder as shown in FIG. 8 into the data driver 14, the data change area can be easily limited. For example, in order to update only the data of the column width w of the nth line, it is preferable to do the following. The data line 7 is precharged, the nth line is selected by the decoder 13, and the bit data of the nth line is read from the memory pixel to the data line 7. When the address to be written is specified and the corresponding bit data is supplied on the data bus, the switch 20 of the specified address is connected to the data bus, and the data on the data line of the corresponding column read first is on the data bus. Overwritten with data. Since the switch 20 is off for the data line in the column not designated by the address, the data read from the memory pixel is maintained as it is. Since the data on the data line is determined as the data of the memory pixel by deselecting the nth line of the gate selection decoder 13, the memory pixel of the column width w is updated, and the same data read out to the other memory pixels Is rewritten. If the same control is repeated for only l lines, only the area of width w and length l can be updated.

  If necessary, only the data selection decoder of FIG. 8 is formed on the same substrate as the pixel array, and a gate driver composed of a shift register or the like instead of the gate selection decoder 13 and a gate driver IC for providing these functions by an IC. It is good also as a structure using.

  In any case, if a data selection decoder can be configured with the same type of transistors as a part of the data driver 14 as shown in FIG. 8, a multifunctional organic EL display can be realized at low cost.

  In addition, since the gate selection decoder, the data selection decoder, and the memory pixel can be formed of a single type transistor, the gate selection decoder, the data selection decoder, and the memory pixel are not limited to low-temperature polysilicon and amorphous silicon, and may be formed using an organic semiconductor or an oxide semiconductor. If it is formed on a plastic substrate in addition to the glass substrate, a flexible display can be configured.

  The decoders of FIGS. 4 and 8 can be applied to a system that employs pixels in which no static memory is introduced, and needless to say, the decoders also work effectively in display elements such as liquid crystals.

It is an equivalent circuit diagram of a memory pixel. It is a layout diagram of a memory pixel. It is a 6-bit area gradation generation type pixel layout diagram. It is a 6-bit area gradation and voltage gradation generation type pixel layout diagram. It is the whole structure of an organic EL display. It is a block diagram of a P-type gate selection decoder. It is a bit data write timing chart. It is a 3-bit area gradation generation type pixel layout diagram. It is a digital drive timing chart by a sub-frame. It is a block diagram of a P-type data selection decoder.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 1st organic EL element, 2 1st drive transistor, 2nd organic EL element, 4 2nd drive transistor, 5 gate transistor, 6 gate line, 7 data line, 8 power supply line, 9 cathode electrode, 10 memory pixel, 11 pixels, 12 pixel array, 13 gate selection decoder, 14 data driver, 15 bit selector, 16, 18 selection circuit, 17, 19 non-selection circuit, 20 switch.

Claims (5)

An active matrix display device in which unit pixels are arranged in a matrix and the display is controlled,
The unit pixel includes a plurality of memory pixels each having a 1-bit memory. The plurality of memory pixels are arranged in two or more columns, and a power supply line is wired corresponding to each column of the memory pixels .
The power supply lines connected to adjacent pixels in the row direction or column direction arranged in the unit pixel have different wiring widths or supply voltages,
An active matrix display device characterized in that each memory pixel connected to an adjacent power supply line is arranged so that a light emission area has a predetermined ratio, and generates a desired light emission intensity ratio . The active matrix display device according to claim 1,
The same potential is supplied to adjacent power supply lines with different wiring widths.
An active matrix display device characterized by the above . The active matrix display device according to claim 1,
Different potentials are supplied to adjacent power supply lines with the same wiring width
An active matrix display device characterized by the above . The active matrix display device according to claim 3,
The potential supplied to the adjacent power supply line is switched alternately.
An active matrix display device characterized by the above. The active matrix type display device according to any one of claims 1 to 4 ,
An active matrix display device, wherein the memory of the memory pixel is a static memory.

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