JP2006119628A - Display device and electronic device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device in which a compact and inexpensive memory with low power consumption and low access speed, can be used for a panel controller and a deterioration compensation circuit of the display device. <P>SOLUTION: In the display device 31 of a digital gray scale method, a plurality of pixels of a display panel 32 are divided into first to n-th pixel regions (n is 2 or more) and a format converting section 34 of a panel controller 33 converts the format of only video data corresponding to one of first to n-th pixel regions and writes the data to one of first and second video memories 35 and 36 in each frame period. A display control section 37 reads out video data that are converted in format and corresponds to one of first to n-th pixel regions in which video data are written to the other of the first and second video memories in the preceding frame period, and transmits the data to the display panel. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital gradation display device and an electronic apparatus using the same. In particular, the present invention relates to a time gray scale display device using a self-luminous material such as organic electroluminescence (EL) and an electronic apparatus using the display device.

  In recent years, as a flat panel display (FPD), an active matrix semiconductor display device has become popular. In particular, as a flat panel display replacing a liquid crystal display device (LCD), a self-luminous active matrix display device using a self-luminous material such as an organic EL is attracting attention, and active research and development is being performed. .

  In an active matrix display device, there are known an analog gradation that continuously changes the brightness of each pixel and a digital gradation that discretely changes the brightness of each pixel. The analog gradation is realized, for example, by continuously changing the voltage applied to a light emitting element such as an EL element assigned to each pixel and continuously changing the brightness of the light emitting element. For digital gradation, a plurality of light emitting elements (or sub-pixels) having different areas are assigned to each pixel, and an area gradation that changes the brightness of each pixel by changing the combination of light emitting elements to emit light, or assigned to each pixel. Although there is one light emitting element, there is a time gradation in which the brightness of each pixel is changed by discretely changing the lighting time of the light emitting element in one frame period (period in which one image is displayed). In addition, color display is widely performed by using a red (R), green (G), or blue (B) filter for each pixel.

In the area gradation, a plurality of subpixels are assigned to each pixel. For example, k sub-pixels E ₁ , E ₂ ,. . . When assigning E _k to one pixel (referred to as the display bit number k), each sub-pixel E ₁ , E ₂ ,. . . When the area of E _k is the minimum sub-pixel area E ₀ , E ₁ = 1 × E ₀ , E ₂ = 2 × E _0,. . . , E _k = 2 ^k−1 × E ₀ , by changing these combinations, the brightness of each pixel can be changed in 2 ^k gradation with the brightness corresponding to E ₀ as the minimum unit. it can.

In the time gradation, one frame period includes a plurality of (for example, k) subframe periods S ₁ , S ₂ ,. . . , It is divided into _{S k.} Each subframe period S ₁ , S ₂ ,. . . , S _k , lighting periods T ₁ , T ₂ ,. . . , T _k , for example, where T ₀ is the minimum lighting period, T ₁ = 1 × T ₀ , T2 = 2 × T ₀ ,. . . , T _k = 2 ^k−1 × T ₀ (the sum of T _{1 to} T _n is smaller than one frame period), the combination thereof is changed (that is, the lighting / non-lighting of each pixel in each lighting period) brightness corresponding to T ₀ in the lighting selecting) that can change the brightness of each pixel in the 2 ^k gray-scale as the minimum unit.

  In such a time gray scale display device, the input video data (or digital video signal) is subjected to format conversion for time gray scale, and the control for supplying the format converted video data to the display panel at an appropriate timing. A circuit (panel controller) is required (see Patent Document 1). An example of a time gray scale display device provided with such a panel controller is shown in FIG.

  The display device 1 in FIG. 1 includes a display panel 2 and a panel controller 3, and a video signal is input to the panel controller 3. The panel controller 3 includes a format conversion unit 4 that converts the format of the input video data for time gradation, and a first video memory 5 and a second video memory that store the video data format-converted by the format conversion unit 4. 6 and a display control unit 7 that reads out video data stored in the first video memory 5 and the second video memory 6 and transmits them to the display panel 2. The format converter 4 is connected to the first video memory 5 and the second video memory 6 via the tristate buffer 8 and the tristate buffer 9, and the display controller 7 is connected to the first video memory 5 via the selector 10. And connected to the second video memory 6. The format conversion unit 4 and the display control unit 7 are connected to each other so that they can operate in synchronization.

  The panel controller 3 writes the video data converted by the format converter 4 in the first video memory 5 in a certain frame period, and displays the format-converted video data stored in the second video memory 6 in the display controller 7. And the video data is written to the second video memory 6 in the next frame period, and the video data is read from the first video memory 5 and transmitted to the display panel 2. These operations are repeated alternately. That is, the first video memory 5 and the second video memory 6 are used by alternately switching roles for each frame. As the first video memory 5 and the second video memory 6, an SRAM can be preferably used.

  However, in recent years, the amount of information of video data tends to increase with an increase in the size of a display panel, and video data for one frame may not fit in one SRAM. In order to cope with this, it is necessary to use a plurality of SRAMs for each of the first video memory 5 and the second video memory 6, but this is not preferable for downsizing of the product and cost reduction.

  On the other hand, light emitting elements such as EL elements are deteriorated by lighting for a long time. Therefore, when a display device using an EL element is used for a long time, the luminance characteristics of the EL element may vary depending on the degree of deterioration of each EL element. That is, even when the same voltage is applied between the deteriorated EL element and the non-deteriorated EL element, a difference in luminance occurs.

  In order to prevent such luminance unevenness, the lighting time of the EL element of each pixel is detected by periodically sampling the video data signal, and the accumulation of the detected values and the EL elements stored in advance are detected. There is a technique that uses a deterioration compensation circuit that corrects a video data signal for driving a pixel having deteriorated EL elements so as to compensate for the deterioration of the EL elements by referring to the data of the luminance characteristics with time (patent) Reference 2).

  An example of such a deterioration compensation circuit is shown in the block diagram of FIG. The degradation compensation circuit 20 in FIG. 2 includes a counter unit 21, a storage circuit unit 22, and a signal correction unit 23. The counter unit 21 includes the counter 12, the storage circuit unit 22 includes the volatile memory 13 and the nonvolatile memory 14, and the signal correction unit 23 includes the correction circuit 15 and the correction data storage unit 16. In this deterioration compensation circuit 20, the video data for driving the deteriorated pixel of the EL element in the first video signal 11A, which is the video data before correction, is corrected by the signal correction unit 23 and is the corrected video data. The second video signal 11B is supplied to the display device 17.

  More specifically, in the deterioration compensation circuit 20, the first video signal 11A is sampled periodically (for example, every second), and the counter 12 counts lighting or non-lighting in each pixel based on the signal. The number of times of lighting in each pixel, that is, the cumulative lighting time, is sequentially stored in the storage circuit unit 22 (hereinafter referred to as cumulative time data). Since the number of times of lighting is accumulated, it is desirable that the memory circuit unit is configured using a nonvolatile memory. However, since the nonvolatile memory generally has a limited number of times of writing, the device shown in FIG. Then, during operation of the display device 17, data is stored using the volatile memory 13, and written into the nonvolatile memory 14 at regular intervals (for example, every hour or when the power supply is shut down). The contents of the volatile memory 13 are lost when the power is shut down. However, when the power is turned on again, the accumulated time data is read from the nonvolatile memory 14 to the volatile memory 13, and the lighting time of the EL element is continued. Is cumulatively counted.

  The correction data storage unit 16 of the signal correction unit 23 preliminarily stores the change data of the luminance characteristics of the EL elements as a video signal correction map. The correction circuit 15 refers to the video signal correction map and the cumulative lighting time of each pixel read from the volatile memory 13, and adjusts each pixel according to the degree of deterioration of each pixel estimated from the cumulative lighting time. The input first video signal 11A is corrected by increasing / decreasing the digital video signal (pixel data).

In such a degradation compensation circuit 20, when the amount of information of video data increases, the amount of data transfer among the counter 12, the volatile memory 13, the nonvolatile memory 14, the correction circuit 15 and the like increases, and access to these devices is increased. It will be done more often. Therefore, these devices (particularly memories) that can operate at high speed are required, leading to an increase in cost.
JP 2004-163919 A JP 2002-175041 A

  The present invention has been made to solve the above-described problems of the prior art, and a first object of the present invention is to provide a digital gray scale display device having a panel controller for video data format conversion. Even if the amount of input video data increases due to an increase in the size of the display panel, etc., it prevents the increase in the capacity of the video memory used by the panel controller, and is a small, low-speed and low-power-consumption memory It is possible to use.

  A second object of the present invention is to use a display device having a deterioration compensation circuit that compensates for deterioration of a light emitting element, even if the amount of input video data increases due to an increase in the size of the display panel, etc. It is possible to use a low-cost and low-power-consumption memory that is small and has a low access speed as the memory to be used.

  In order to solve the above-described problems, according to the present invention, a display panel having a plurality of pixels, and a panel that converts the format of input video data into data for display in a predetermined digital gradation and supplies the data to the display panel The panel controller includes first and second video memories, format conversion of input video data in units of frames, and format-converted video data in the first video memory or the second video memory. A format conversion section for alternately writing to the display panel, and a display control section for reading out the format-converted video data stored in the first video memory or the second video memory and transmitting it to the display panel. The plurality of pixels are divided into first to nth pixel regions (n ≧ 2), and in each frame period, The format conversion unit converts the format of the video data for the selected one of the first to n-th pixel regions and writes the video data to one of the first and second video memories. There is provided a display device that reads out the format-converted video data for one of the first to n-th pixel regions written in the other of the second video memories and transmits it to the display panel.

  Preferably, the pixel regions in which the format conversion of the video data is performed by the format conversion unit in each frame period are the first, second,. . . The nth pixel region may be selected in order, and the next to the nth pixel region may return to the first pixel region (that is, cyclically selected from the first to nth pixel regions). The n can be set to 2, for example.

  In each frame period, the display control unit can fix the video data of each pixel belonging to the pixel region where the video data is not read from the first or second video memory to a predetermined value. Alternatively, in each frame period, the display control unit outputs the video data of each pixel belonging to the pixel area from which the video data is not read from the first or second video memory to the first or second around the pixel. It can also be determined from the result of statistical processing of video data of pixels belonging to the pixel area from which video data has been read from the video memory.

  According to another aspect of the present invention, a display panel having a plurality of pixels, a deterioration compensation circuit for correcting video data input to compensate for deterioration of a light emitting element of each pixel, and video data from the deterioration compensation circuit A panel controller that converts the data into data for display at a predetermined digital gradation and supplies the data to the display panel. The panel controller includes video data from the first and second video memories and the deterioration compensation circuit. Is converted into a frame unit and the format-converted video data is alternately written in the first video memory or the second video memory, and stored in the first video memory or the second video memory. A display control unit for reading out the video data converted in format and transmitting it to the display panel. The plurality of pixels of the panel are divided into first to nth pixel regions (n ≧ 2), and the deterioration compensation circuit is configured to output the first to nth pixel regions of the video data for one frame in each frame period. The video data corresponding to the selected one is corrected to generate corrected video data, and the format converter of the panel controller converts the format of the corrected video data generated by the deterioration compensation circuit to the first video memory or the first video memory. A display device is provided that writes to a video memory.

  Preferably, the pixel regions in which the video data is corrected by the deterioration compensation circuit in each frame period are the first, second,. . . The nth pixel region may be selected in order, and the next to the nth pixel region may return to the first pixel region (that is, cyclically selected from the first to nth pixel regions). The n can be set to 2, for example.

  The deterioration compensation circuit includes a counter unit that detects the cumulative lighting time of each pixel, a storage circuit unit that stores the cumulative lighting time, and a signal correction unit that corrects video data in accordance with the cumulative lighting time stored in the storage circuit unit. The signal correction unit includes a correction data storage unit that stores correction data based on a change in luminance characteristics of the light emitting element over time, and a predetermined calculation for video data using the correction data stored in the correction data storage unit. And an arithmetic circuit for generating corrected video data, and an address for reading out the cumulative lighting time of pixels belonging to the pixel area where the video data is corrected in each frame period from the storage circuit unit and accessing the correction data storage unit The correction data storage unit outputs correction data corresponding to the address to the arithmetic circuit.

  Preferably, in each frame period, the deterioration compensation circuit outputs corrected video data for a selected one of the first to nth pixel regions to the panel controller. In that case, the signal correction unit further includes a latch connected to the input of the arithmetic circuit, and the video data is input to the arithmetic circuit via the latch, and the latch is corrected in each frame period. The video data for a selected one of the n pixel regions can be sampled and input to the arithmetic circuit. The counter unit includes an adder and a latch connected to the input terminal of the adder. In each frame period, the corrected video data for the selected one of the first to nth pixel regions is output from the arithmetic circuit. Sent to the latch of the counter unit, which periodically samples the corrected video data and sends it to the adder, the adder is a pixel belonging to the pixel area where the corrected video data is sent to the adder The accumulated lighting time is read from the storage circuit unit, and the corrected lighting data is added to the read accumulated lighting time to update the accumulated lighting time.

  Alternatively, in each frame period, the deterioration compensation circuit outputs the corrected video data for the selected one of the first to nth pixel areas and the uncorrected video data for the other pixel areas to the panel controller. It can also be. In that case, the signal correction unit further includes a selector provided between the arithmetic circuit and the correction data storage unit, the selector has two input ends and one output end, and the output end of the correction circuit. Connected to the input terminal, one of the two input terminals is connected to the output terminal of the correction data storage unit, a predetermined value is input to the other of the two input terminals, and the selector has a first value in each frame period. When the video data for the selected one of the nth pixel regions is input to the arithmetic circuit, the correction data stored in the correction data storage unit is input to the arithmetic circuit, and the other pixel regions When video data is input to the arithmetic circuit, a predetermined value is input to the arithmetic circuit, and the predetermined value is used even when the arithmetic circuit performs an operation on the video data using the predetermined value. With a value that does not change the video data It can be a shall.

  Preferably, the counter unit includes an adder and a latch connected to the input terminal of the adder, and the corrected video data for the selected one of the first to nth pixel regions in each frame period. And non-corrected video data for the other pixel regions are sent from the arithmetic circuit to the latch of the counter unit, and the counter unit latch periodically samples the corrected video data for the selected one of the first to nth pixel regions. To the adder, and the adder reads the accumulated lighting time of the pixels belonging to the pixel area to which the corrected video data is sent to the adder from the storage circuit unit, and adds the corrected video data to the read accumulated lighting time. Thus, the cumulative lighting time can be updated.

  Preferably, the display device is a time gray scale display device.

  According to still another aspect of the present invention, an electronic apparatus having the display device as described above is provided.

  In the display device according to the present invention, the pixels of the display panel are divided into the first to nth pixel regions, and the format conversion unit converts the format of the video data for the selected one of the first to nth pixel regions in each frame period. By sending the data to the first or second video memory, the amount of video data stored in the first and second video memories can be reduced to approximately 1 / n. Therefore, it is possible to use a small and inexpensive video memory with a small capacity even if the amount of information of the input video data is large.

  The pixel regions where the format conversion of the video data is performed by the format conversion unit in each frame period are the first, second,. . . If the n pixel regions are selected in this order and the next pixel region returns to the first pixel region, these pixel regions can be used without bias. When n is 2, the video data for the first pixel region and the video data for the second pixel region are alternately converted in format for each frame and written to the first or second video memory. The amount of video data stored in the memory can be approximately halved.

  In each frame period, the display control unit can fix the video data of each pixel belonging to the pixel area where the video data is not read from the first or second video memory to a predetermined value, thereby Although the load on the display control unit can be reduced, image flicker may occur. In each frame period, the display control unit outputs the video data of each pixel belonging to the pixel area where the video data is not read from the first or second video memory to the first or second video located around the pixel. By determining the video data of the pixels belonging to the pixel area from which the video data has been read from the memory based on the result of statistical processing, it is possible to reduce image flickering that may occur when the video data is fixed to a predetermined value. .

  In addition, according to the self-luminous display device according to another embodiment of the present invention, the deterioration compensation circuit for correcting the video data input to compensate for the deterioration of the light emitting element includes video data for one frame in each frame period. The corrected video data is generated by correcting the video data for the selected one of the first to nth pixel areas, and the format conversion unit of the panel controller converts the corrected video data generated by the deterioration compensation circuit. Since the data is written in the first video memory or the second video memory, the amount of video data written in the video memory of the panel controller can be reduced to 1 / n. These video memories are small in capacity, small in size and low in cost. Can be.

  Pixel regions in which video data is corrected by the deterioration compensation circuit in each frame period are first, second,. . . If the n pixel regions are selected in this order and the next pixel region returns to the first pixel region, these pixel regions can be used without bias. When n is 2, the video data for the two pixel areas of the first and second pixel areas are corrected alternately. Accordingly, in the panel controller, the video data for the first pixel area and the video data for the second pixel area are alternately format-converted for each frame and written to the first or second video memory, and the first and second video memories are written. The amount of video data stored in the video memory can be approximately halved.

  Preferably, the deterioration compensation circuit corrects video data in accordance with the cumulative lighting time stored in the counter circuit that detects the cumulative lighting time of each pixel, the storage circuit that stores the cumulative lighting time, and the storage circuit. A signal correction unit that stores correction data based on a change in luminance characteristics of the light emitting element over time, and video data using the correction data stored in the correction data storage unit. An arithmetic circuit for generating corrected video data by performing a predetermined calculation on the memory, and reading the accumulated lighting time of pixels belonging to the pixel area where the video data is corrected in each frame period from the memory circuit unit and accessing the correction data storage unit And an address conversion unit for converting the address into an address for performing correction, and the correction data storage unit outputs correction data corresponding to the address to the arithmetic circuit. That. In such a deterioration compensation circuit, since the amount of video data corrected in each frame period is 1 / n of the input video data, the cumulative lighting time of the corresponding pixel is read from the memory circuit unit to the address conversion unit. Will be reduced accordingly. Accordingly, it is possible to use a memory with a low access speed and a low power consumption and an inexpensive memory as the memory circuit portion.

  In each frame period, when the deterioration compensation circuit outputs the corrected video data generated for the selected one of the first to nth pixel areas to the panel controller, the panel controller itself writes the corrected video data in the video memory. Even if it does not have a function for reducing the amount of information of video data, the panel controller converts the format of 1 / n video data corrected by the deterioration compensation circuit and writes it to the video memory. A memory having a small capacity, a small size and a low cost can be used.

  In that case, preferably, the signal correction unit further includes a latch connected to the input of the arithmetic circuit, and the video data is input to the arithmetic circuit via the latch. By controlling the latch, the video data for the selected one of the first to nth pixel regions to be corrected in each frame period is sampled and input to the arithmetic circuit, so that the first to nth. Video data for a selected one of the pixel areas can be corrected by an arithmetic circuit and output.

  Further, in each frame period, the corrected video data for the selected one of the first to nth pixel areas is sent from the arithmetic circuit to the adder of the counter unit, and the cumulative lighting time of the pixels belonging to the selected pixel area Is read from the memory circuit unit and sent to the adder, where the cumulative lighting time and the corrected video data are added to update the cumulative lighting time, thereby reducing the number of times the cumulative lighting time is read from the memory circuit unit to the adder. In addition, a memory having a low access speed, low power consumption, and low cost can be used as the memory circuit portion.

  Alternatively, in each frame period, the deterioration compensation circuit outputs the corrected video data for the selected one of the first to nth pixel areas and the uncorrected video data for the other pixel areas to the panel controller. It can also be. In such a deterioration compensation circuit, the signal correction unit further includes a selector provided between the arithmetic circuit and the correction data storage unit, and the selector has two input ends and one output end, and outputs One end is connected to the input end of the correction circuit, one of the two input ends is connected to the output end of the correction data storage unit, and a predetermined value is input to the other of the two input ends. In the period, when video data for the selected one of the first to nth pixel regions is input to the arithmetic circuit, the correction data stored in the correction data storage unit is input to the arithmetic circuit, When video data in another pixel area is input to the arithmetic circuit, a predetermined value is input to the arithmetic circuit, and the predetermined value is used by the arithmetic circuit to perform an operation on the video data. Even changing the video data It can be assumed to be without value. Even in such a structure, the video data corrected in the arithmetic circuit is 1 / n of the input video data in each frame period. In addition, the number of pixels for which the cumulative lighting time is actually updated when the cumulative lighting time is periodically updated is also 1 / n of the total number of pixels. Therefore, in order to generate an address for reading correction data used for video data correction from the correction data storage unit, the number of times of reading the accumulated lighting time of the pixels stored in the storage circuit unit to the address conversion unit is 1 / n. Therefore, a memory with low access speed and low power consumption and low cost can be used as the memory circuit portion.

  In each frame period, when the corrected video data for the selected one of the first to nth pixel regions and the uncorrected video data for the other pixel regions are sent from the arithmetic circuit to the counter unit, the counter unit is an adder. And a latch connected to the input terminal of the adder, and the latch of the counter unit periodically samples the correction video data for the selected one of the first to nth pixel areas and adds the adder. The adder reads the accumulated lighting time of the pixels belonging to the pixel area to which the corrected video data is sent to the adder from the storage circuit unit, and adds the corrected video data to the read accumulated lighting time to accumulate the lighting. It is recommended to update the time. Accordingly, the number of times of reading the cumulative lighting time from the storage circuit unit to the adder can be reduced, and a low-power consumption and low-cost memory having a low access speed can be used as the storage circuit unit.

  The above display device is preferably a time gray scale display device. In addition, when an electronic device is formed using the display device as described above, it is easy to reduce the size and cost of the electronic device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 3 is a block diagram showing a preferred embodiment of a display device according to the present invention. The display device 31 includes, for example, an active matrix display panel 32 using a self-luminous material such as an organic EL, and format conversion of input video data, and the format-converted video data is displayed at an appropriate timing. And a panel controller 33 for supplying to the printer.

  As in the conventional example shown in FIG. 1, the panel controller 33 includes a format conversion unit 34, first and second video memories 35 and 36, a display control unit 37, and first and second tristate buffers 38. , 39 and a selector 40.

  In the embodiment shown in FIG. 3, the pixels of the display panel 32 are divided into, for example, first and second pixel areas, and the format converter 34 converts only the video data for the first pixel area in a certain frame period. In the next frame period, only the video data for the second pixel region is format-converted and written to the second video memory 36, and this is repeated alternately. The display control unit 37, as in the conventional case, performs the writing of the video data having undergone format conversion into one of the first video memory 35 and the second video memory 36, while the first video memory 35, the second video memory 35, The format-converted video data stored in the other video memory 36 is read out and sent to the display panel 32 for display.

  In this manner, as shown in the time chart of FIG. 4, video data is written to the first pixel area and read for displaying the video data to the second pixel area in a certain frame period, and in the next frame period. The video data is written to the second pixel area and the video data is read to display the first pixel area, and reading and writing are alternately repeated in each pixel.

  As an example of the first and second pixel regions, for example, as shown in FIGS. 5A and 5B, the first and second pixel regions include pixels located on every other column or row, respectively. (Stripe pattern), as shown in FIG. 5C, the pixels included in the first and second pixel regions form a checkered pattern, and the other pixels in the horizontal and vertical directions of each pixel included in one pixel region It can be considered that the pixels in the pixel region are arranged adjacent to each other. The selection of the first and second pixel regions is preferably performed so that the pixels in the other pixel region are arranged as close as possible to each pixel in the one pixel region. 5A to 5C exemplify pixels of 5 rows × 5 columns, it goes without saying that the number of rows and columns of pixels of the display panel 32 is not limited to this.

  The display control unit 37 outputs video data (pixel data) of each pixel belonging to a pixel area (non-read pixel area) from which video data is not read from the first video memory 35 or the second video memory 36 in each frame period. Although it can be fixed to a certain value, image flickering may appear. In order to reduce this, the video data of the pixels belonging to the non-readout pixel area is predicted from the video data of the pixels belonging to the pixel area (readout pixel area) to which the video data is sent, which is located adjacent to or adjacent to the surrounding area. Or it can be approximated. For example, a bit of video data (for example, 8 bits) for one pixel has a first bit group UB (for example, upper 4 bits) having a large influence on the light emission luminance of the pixel and a second bit group LB (for example, lower 4 bits) having a small influence In the subframe period corresponding to the second bit group LB, the bit value of each pixel in the non-read pixel area is fixed to a certain value (for example, “1” (lighted) or “0” (not lighted)), In the sub-frame period corresponding to the first bit group UB, statistics of the bit values of the pixels belonging to the readout pixel area located adjacent to or in the vicinity of the respective pixels belonging to the non-readout pixel area are taken, and the result is It is possible to determine the bit value of the pixel in the readout pixel region. As a special case, it is assumed that the first bit group UB includes only the most significant bit (MUB), and a majority vote can be adopted as statistical processing (that is, the most significant pixel belonging to the read pixel area around the target pixel). When the number of bits is large, the most significant bit of the pixel is set to 1. When the number of bits is large, the most significant bit of the pixel is set to 0.

  In the case where the display control unit 37 takes statistics of the video data of the pixels belonging to the readout pixel area as described above, the video data sent from the first video memory 35 and the second video memory 36 is temporarily stored if necessary. A small-capacity memory 41 for holding may be provided. In particular, when only the most significant bit of each pixel is statistically processed as described above, the capacity of the memory 41 can be made extremely small.

  As described above, the pixels of the display panel 32 are divided into first and second pixel regions, and the format conversion unit 34 alternately converts the video data for the first pixel region and the video data for the second pixel region for each frame. Thus, the amount of video data stored in the first video memory 35 and the second video memory 36 is substantially halved by sending it to the first video memory 35 or the second video memory 36. Can do. Therefore, it is possible to use a small and inexpensive video memory with a small capacity even if the amount of information of the input video data is large.

  In the embodiment shown in FIG. 3, the pixels of the display panel 32 are divided into two for the first pixel region and the second pixel region. However, a larger number of divisions such as three divisions or four divisions may be used. it can. In this embodiment, two video memories are used. However, the present invention is not limited to this, and more video memories can be used. In general, when dividing into n (n ≧ 2) pixel areas in the first to n-th pixel areas, the format conversion unit 34 performs video for a selected one of the first to n-th pixel areas in each frame period. Only the data is format-converted and written into one of the first video memory 35 and the second video memory 36. In each frame period, the pixel region in which the video data is subjected to format conversion is cyclically selected from the first to nth pixel regions (that is, selected in the order of the first, second,..., Nth pixel regions). Then, after the nth pixel area, the process returns to the first pixel area). As a result, the amount of video data stored in the video memory is approximately 1 / n.

  FIG. 6 is a block diagram showing another embodiment of the display device according to the present invention. The display device 50 includes a display panel 51 using an EL element as a light emitting element, a panel controller 52, and a deterioration compensation circuit 53, and video data is input to the deterioration compensation circuit 53. The deterioration compensation circuit 53 corrects video data to compensate for the deterioration of the EL element of each pixel based on the accumulated lighting time or the like. The panel controller 52 converts the corrected video data input from the deterioration compensation circuit 53 into, for example, video data for time gradation and supplies it to the display panel 51, and has the same configuration as the panel controller 33 shown in FIG. It can be.

  In the embodiment shown in FIG. 6, as in the embodiment shown in FIG. 3, the pixels of the display panel 51 are divided into n (n is 2 or more) pixel regions. The deterioration compensation circuit 53 corrects the video data for the first pixel area in a certain frame period and supplies it to the panel controller 52, and corrects the video data for the second pixel area in the next frame period and supplies it to the panel controller 52. In this manner, the same processing is sequentially repeated for the video data for each pixel region, and in the next frame period in which the video data correction processing for the nth pixel region is performed, the processing returns to the video data correction processing for the first pixel region. Therefore, as shown in FIG. 6, in each frame period, the information amount of the corrected video data sent to the panel controller 52 is 1 / n of the input video data. Accordingly, even if the panel controller 52 (more specifically, its format conversion unit) does not have a function of reducing the amount of information of video data to be written to the video memory as in the panel controller 33 of FIG. Since only 1 / n video data corrected by the compensation circuit 53 is converted in format and written to the video memory, a small capacity, small size and low cost video memory can be used for the panel controller 52. It becomes.

  FIG. 7 is a block diagram showing details of the deterioration compensation circuit 53 of FIG. The degradation compensation circuit 53 includes a counter unit 54, a storage circuit unit 55, and a signal correction unit 56, similarly to the degradation compensation circuit 20 of FIG. The counter unit 54 includes an adder 60 that functions as a counter and two latches 61 and 62. The memory circuit unit 55 includes a volatile memory 63 and a nonvolatile memory 64. The signal correction unit 56 includes a multiplier 65 serving as an arithmetic circuit, a deterioration coefficient holding register 66, an address conversion unit 67, and two latches 68 and 69.

  The volatile memory 63 stores the cumulative lighting time of each pixel. The video data before the format conversion of each pixel usually represents the luminance of the pixel. However, in the time gradation method, the luminance of the pixel in a certain frame is substantially equivalent to the lighting time of the pixel in the frame. The cumulative lighting time of each pixel can be obtained by cumulatively adding the video data.

  The non-volatile memory 64 has a cumulative lighting time backup area 64a, and the data of the volatile memory 63 is stored in the non-volatile memory 64 at regular time intervals (for example, every hour or when the power is shut down), as in the prior art. Is written in the accumulated lighting time backup area 64a (store). When the power is turned on, the cumulative lighting time data is read from the cumulative lighting time backup area 64a to the volatile memory 63 (recall).

  The non-volatile memory 64 has a deterioration coefficient holding area 64b in which a deterioration coefficient as correction data generated based on a change with time of the luminance characteristics of the EL element is stored in advance. For example, the deterioration coefficient holding area when the power is turned on. Data in 64b is read out to the deterioration coefficient holding register 66 of the signal correction unit 56.

  In the deterioration compensation circuit 53, the video data is sent to the multiplier 65 via the latch 69 of the signal correction unit 56. At this time, by appropriately controlling the latch 69, the video data is supplied to the first pixel region in a certain frame period. Only the video data is sent to the multiplier 65, and in the next frame period, only the video data for the second pixel area is sent to the multiplier 65, which is sequentially processed up to the video data corresponding to the nth pixel area, and then the first pixel again. It is possible to return to the video data for the area and repeat the same processing. That is, the pixel area where video data is sent to the multiplier 65 in each frame period is cyclically selected from the first to nth pixel areas. Thereby, in each frame period, approximately 1 / n of the video data of the input video data is sent to the multiplier 65. When n = 2, video data for the two pixel areas of the first and second pixel areas are alternately sent to the multiplier 65, and the video data supplied to the multiplier 65 in each frame period is input video. Approximately half of the data.

  The address conversion unit 67 converts the accumulated lighting time of each pixel into an address for accessing the deterioration coefficient holding register 66 corresponding to the 1 / n video data sent to the multiplier 65, and the deterioration coefficient holding register 66. Reads out the degradation coefficient stored at the designated address and sends it to the multiplier 65. In this case, the deterioration coefficient holding register 66 functions as a correction data storage unit. Alternatively, as indicated by the dotted arrow, the address conversion unit 67 sets the accumulated lighting time of each pixel in the deterioration coefficient holding area 64 b of the nonvolatile memory 64 in accordance with the 1 / n video data sent to the multiplier 65. It is also possible to convert the address into an address for access, read out the degradation coefficient stored at the designated address in the degradation coefficient holding area 64 b, and send it to the multiplier 65 via the degradation coefficient holding register 66. In this case, the deterioration coefficient holding area 64b of the nonvolatile memory 64 functions as a correction data holding unit. In the latter case, it is not necessary to read the data in the deterioration coefficient holding area 64b to the deterioration coefficient holding register 66 when the power is turned on.

  The multiplier 65 multiplies the input deterioration coefficient and the video data to generate corrected video data. As described above, since the video data input to the multiplier 65 is 1 / n of the input video data, the corrected video data output from the multiplier 65 is also 1 / n of the input video data. Further, since the deterioration coefficient sent from the deterioration coefficient holding register 66 to the multiplier 65 only needs to correspond to 1 / n video data input to the multiplier 65, the number of accesses to the deterioration coefficient holding register 66 is greatly increased. Accordingly, the number of times of accessing the volatile memory 63 for reading the accumulated lighting time of each pixel necessary for generating an address for accessing the degradation coefficient holding register 66 can be reduced.

  The corrected video data is sampled periodically (for example, every second) via the latch 61 of the counter unit 54 and input to the adder 60. The volatile memory 63 sends the cumulative lighting time of the pixels belonging to the pixel area to which the corrected video data is sent to the adder 60 to the adder 60 via the latch 62, and the adder 60 stores the corrected video data of each pixel. The cumulative lighting time is added to update the cumulative lighting time. Therefore, the frequency of accessing the volatile memory 63 to read the accumulated lighting time sent to the adder 60 is reduced to 1 / n. The updated accumulated lighting time is stored in the volatile memory 63.

  As described above, the capacity of the video memory in the panel controller 52 that receives the corrected video data from the degradation compensation circuit 53 by setting the information amount of the corrected video data output from the degradation compensation circuit 53 to 1 / n of the input video data. Can be reduced. In the deterioration compensation circuit 53, the video data corrected by the multiplier 65 is 1 / n of the input video data in each frame period. Accordingly, the number of pixels for which the cumulative lighting time is updated in the update (detection) of the cumulative lighting time that is periodically performed in the counter unit 54 is also 1 / n of the total number of pixels. Accordingly, since the number of times of reading the cumulative lighting time of the pixels stored in the volatile memory 63 to the address conversion unit 67 and the adder 60 is reduced to 1 / n, the volatile memory 63 has a low access speed and low power consumption. And inexpensive memory can be used.

  FIG. 8 is a block diagram showing still another embodiment of the display device according to the present invention. The display device 50a includes the same display panel 51, panel controller 52a, and deterioration compensation circuit 53a as in the embodiment of FIG. 6, and video data is input to the deterioration compensation circuit 53a. In the embodiment shown in FIG. 8, the video data corrected by the deterioration compensation circuit 53a in each frame period is 1 / n of the input video data, but the remaining (1- 1 / n) The difference from the embodiment of FIG. 6 is that uncorrected video data is also sent to the panel controller 52a. Therefore, in the embodiment of FIG. 8, the amount of information of the video data input to the panel controller 52a is the same as the video data input to the deterioration compensation circuit 53a. Therefore, the panel controller 52a has its internal video memory. In order to reduce the amount of video data to be written in, in the same manner as the panel controller 33 described with reference to FIG. 3, the function of converting only the video data for the selected pixel area in each frame period and writing it into the video memory is provided. Have.

  FIG. 9 is a block diagram showing details of the deterioration compensation circuit 53a shown in FIG. In this figure, parts similar to those in FIG. In the degradation compensation circuit 53a, the video correction data is directly input to the multiplier 65 without a latch in the signal correction unit 56a, and the degradation coefficient and the fixed value “1” from the degradation coefficient holding register 66 are supplied to the selector 70. 7 is different from that shown in FIG. 7 in that it is selectively input to the multiplier 65. In other words, one of the two input terminals of the selector 70 is connected to the output terminal of the deterioration coefficient holding register 66, the fixed value “1” is always input to the other, and the output terminal is connected to the two input terminals of the multiplier 65. It is connected to one side (video data is inputted to the other of the two input ends of the multiplier 65). When the video data of the pixel region to be corrected in each frame period is input to the multiplier and inputted to the multiplier 70, the selector 70 sends the deterioration coefficient from the deterioration coefficient holding register 66 to the multiplier 65 to correct the video data. When the video data of the pixel region to be corrected is input to the multiplier 65, the deterioration coefficient “1” is sent to the multiplier 65 so that the video data is not corrected. Thus, the video data output from the deterioration compensation circuit 53a includes 1 / n corrected video data and (1-1 / n) uncorrected video data.

  Since both 1 / n corrected video data and (1-1 / n) uncorrected video data are also sent to the latch 61 of the counter unit 54, the latch 61 adds only 1 / n corrected video data. The video data is sampled for input to the device 60.

  Also in FIG. 9, the video data corrected by the multiplier 65 becomes 1 / n of the input video data in each frame period. In addition, the number of pixels for which the cumulative lighting time is actually updated when the cumulative lighting time is periodically updated is also 1 / n of the total number of pixels. Accordingly, the number of times of reading out the cumulative lighting time of the pixels stored in the volatile memory 63 for the video data correction and the cumulative lighting time update to the address conversion unit 67 and the adder 60 is reduced to 1 / n. As the memory 63, an inexpensive memory with low access speed and low power consumption can be used.

  The panel controller and / or the deterioration compensation circuit as described above can be provided separately from the display panel and placed outside the display panel. Alternatively, as shown in FIG. 10, the panel controller and / or the deterioration compensation circuit can be integrally formed on the same substrate as the display panel. 10 includes a panel controller 201, a source signal line driver circuit 202, gate signal line driver circuits 203 and 204, a pixel matrix portion (or display panel) 205, a deterioration compensation circuit 206, a connector, and the like on a substrate 200. 208 is integrally formed, and video data is input via a flexible printed circuit board (FPC) 207 connected to the connector 208. As the panel controller 201, the panel controller 33 as shown in FIG. 3 can be used, and as the deterioration compensation circuit 206, the deterioration compensation circuit 53 shown in FIG. 7 or the deterioration compensation circuit 53a shown in FIG. 9 is used. be able to. A glass substrate can be preferably used as the substrate 200, but another substrate such as a heat-resistant plastic substrate can be used in addition to the glass substrate. Known source signal line driver circuits 202 and gate signal line driver circuits 203 and 204 can be used, and one gate signal line driver circuit may be provided depending on the circuit configuration.

  Thus, by integrally forming the panel controller 201 and the deterioration compensation circuit 206 on the same substrate as the display panel 205, it is possible to realize cost reduction, space saving, and high-speed driving by greatly reducing the number of components. .

  Electronic devices to which the present invention can be applied include desktop, floor-standing, or wall-mounted displays, video cameras, digital cameras, goggles-type displays, navigation systems, sound playback devices (car audio, audio components, etc.), computers, game devices, Images and still images recorded on a recording medium such as a portable information terminal (mobile computer, mobile phone, portable game machine, electronic book, etc.), and an image playback device (specifically, Digital Versatile Disc (DVD)) equipped with a recording medium And a device equipped with a display capable of reproducing a picture and displaying it. Specific examples of these electronic devices are illustrated in FIGS.

  FIG. 11A illustrates a desktop, floor-standing, or wall-mounted display, which includes a housing 301, a support base 302, a display portion 303, a speaker portion 304, a video input terminal 305, and the like. Such a display can be used as an arbitrary information display device such as a computer, a TV broadcast receiver, and an advertisement display.

  FIG. 11B illustrates a digital camera, which includes a main body 311, a display portion 312, an image receiving portion 313, operation keys 314, an external connection port 315, a shutter 316, and the like.

  FIG. 11C illustrates a computer, which includes a main body 321, a housing 322, a display portion 323, a keyboard 324, an external connection port 325, a pointing mouse 326, and the like. Note that the computer includes a so-called notebook computer in which a central processing unit (CPU), a recording medium, and the like are integrated, and a so-called desktop computer separated.

  FIG. 11D illustrates a mobile computer, which includes a main body 331, a display portion 332, a switch 333, operation keys 334, an infrared port 335, and the like.

  FIG. 11E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 341, a housing 342, a first display portion 343, a second display portion 344, and a recording medium. (DVD etc.) It has a reading unit 345, operation keys 346, a speaker unit 347, and the like. The first display unit 343 mainly displays image information, and the second display unit 344 mainly displays character information. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

  FIG. 11F illustrates a goggle type display, which includes a main body 351, a display portion 352, and an arm portion 353.

  FIG. 11G illustrates a video camera, which includes a main body 361, a display portion 362, a housing 363, an external connection port 364, a remote control receiving portion 365, an image receiving portion 366, a battery 367, an audio input portion 368, operation keys 369, and the like. .

  FIG. 11H illustrates a cellular phone, which includes a main body 371, a housing 372, a display portion 373, an audio input portion 374, an audio output portion 375, operation keys 376, an external connection port 377, an antenna 378, and the like.

  The display device of the present invention can be applied to the display units 303, 312, 323, 332, 343, 344, 352, 362, and 373 of the various electronic devices described above. As a memory, it is possible to use a memory having a low access speed, a small size, a low cost, and low power consumption, and the whole apparatus can be easily downsized.

  Note that, in addition to a display device using an EL element, the present invention can be applied to a display device having a light-emitting element (pixel) that deteriorates when used for a long time, and the display device to which the present invention is applied. May be a plasma display panel (PDP) or a field emission display (FED).

  In addition, the correction of the video data for the compensation of the deterioration of the light emitting element is performed by adding an appropriate value to the video data by using an adder as an arithmetic circuit in addition to multiplying the video data and the deterioration coefficient by a multiplier. Another method such as subtraction may be used.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields.

The block diagram which shows an example of the display apparatus of the time gradation system provided with the conventional panel controller. The block diagram which shows an example of the conventional deterioration compensation circuit. The block diagram which shows the suitable Example of the display apparatus based on this invention. The time chart for demonstrating operation | movement of the panel controller of FIG. The schematic diagram which shows the example of a pixel area | region. The block diagram which shows another Example of the display apparatus based on this invention. FIG. 7 is a block diagram showing details of the deterioration compensation circuit 53 of FIG. 6. The block diagram which shows another Example of the display apparatus based on this invention The block diagram which shows the detail of the deterioration compensation circuit 53a of FIG. FIG. 11 illustrates an example of a display device using the present invention. The perspective view which shows the electronic device with which this invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display apparatus 2 Display panel 3 Panel controller 4 Format conversion part 5 1st video memory 6 2nd video memory 7 Display control part 8, 9 Tristate buffer 10 Selector 11A 1st video signal 11B 2nd video signal 12 Counter 13 Volatile memory 14 Non-volatile memory 15 Correction circuit 16 Correction data storage unit 17 Display device 20 Degradation compensation circuit 21 Counter unit 22 Storage circuit unit 23 Signal correction unit 31 Display device 32 Display panel 33 Panel controller 34 Format conversion unit 35 1 video memory 36 second video memory 37 display control unit 38 tristate buffer 39 tristate buffer 40 selector 41 memory 50, 50a display device 51 display panel 52, 52a panel controller 53, 53a deterioration compensation circuit 54 count Data storage unit 56, 56a Signal correction unit 60 Adder 61 Latch 62 Latch 63 Volatile memory 64 Non-volatile memory 64a Cumulative lighting time backup area 64b Degradation coefficient holding area 65 Multiplier 66 Degradation coefficient holding register 67 Address conversion Unit 68 Latch 69 Latch 70 Selector 200 Substrate 201 Panel controller 202 Source signal line drive circuit 203 Gate signal line drive circuit 204 Gate signal line drive circuit 205 Pixel matrix unit (display panel)
206 Degradation compensation circuit 208 Connector 207 Flexible printed circuit board (FPC)

Claims (17)

A display panel having a plurality of pixels;
A panel controller that converts the format of the input video data into data for display in a predetermined digital gradation and supplies the converted data to the display panel;
The panel controller
First and second video memories;
A format converter that converts the format of the input video data in units of frames and alternately writes the format-converted video data to the first video memory or the second video memory;
A display control unit that reads out the format-converted video data stored in the first video memory or the second video memory and transmits the data to the display panel;
The plurality of pixels of the display panel are divided into first to nth pixel regions (n ≧ 2),
In each frame period, the format conversion unit converts the format of video data for the selected one of the first to n-th pixel regions and writes it to one of the first and second video memories, and the display control unit Reads out the format-converted video data for one of the first to n-th pixel areas written in the other of the first and second video memories in the previous frame period and transmits it to the display panel A display device. The pixel areas in which the format conversion of the video data is performed by the format conversion unit in each frame period are first, second,. . . 2. The display device according to claim 1, wherein the display device is selected in the order of the nth pixel region, and the next to the nth pixel region returns to the first pixel region. The display device according to claim 2, wherein n is two. The display control unit fixes the video data of each pixel belonging to a pixel area in which video data is not read from the first or second video memory to a predetermined value in each frame period. The display device according to claim 1. In each frame period, the display control unit outputs the video data of each pixel belonging to a pixel area from which video data is not read from the first or second video memory, to the first or second video signal located around the pixel. 4. The display device according to claim 1, wherein the display device is determined from a result of statistical processing of video data of pixels belonging to a pixel area from which video data is read out from the video memory. A display panel having a plurality of pixels;
A deterioration compensation circuit that corrects video data input to compensate for deterioration of the light emitting element of each pixel;
A panel controller that converts the format of the video data from the deterioration compensation circuit into data for display in a predetermined digital gradation and supplies the converted data to the display panel;
The panel controller
First and second video memories;
A format converter that converts video data from the deterioration compensation circuit in units of frames and alternately writes the format-converted video data to the first video memory or the second video memory;
A display control unit that reads out the format-converted video data stored in the first video memory or the second video memory and transmits the data to the display panel;
The plurality of pixels of the display panel are divided into first to nth pixel regions (n ≧ 2),
The deterioration compensation circuit corrects video data for a selected one of the first to n-th pixel regions among video data for one frame in each frame period, and generates corrected video data.
The display device of the panel controller, wherein the format converter converts the format of the corrected video data generated by the deterioration compensation circuit and writes the converted video data to the first video memory or the second video memory . The pixel regions in which video data is corrected by the deterioration compensation circuit in each frame period are first, second,. . . The display device according to claim 6, wherein the n-th pixel region is selected in order, and the next to the n-th pixel region returns to the first pixel region. The display device according to claim 7, wherein n is two. The deterioration compensation circuit is:
A counter unit for detecting the cumulative lighting time of each pixel;
A storage circuit unit for storing the cumulative lighting time;
A signal correction unit that corrects the video data according to the accumulated lighting time stored in the storage circuit unit;
The signal correction unit is
A correction data storage unit that stores correction data based on a change in luminance characteristics of the light emitting element over time;
An arithmetic circuit for performing the predetermined calculation on the video data using the correction data stored in the correction data storage unit to generate the corrected video data;
An address conversion unit that reads an accumulated lighting time of pixels belonging to a pixel region in which video data is corrected in each frame period from the storage circuit unit and converts it into an address for accessing the correction data storage unit;
The display device according to claim 6, wherein the correction data storage unit outputs correction data corresponding to the address to the arithmetic circuit. 10. The display device according to claim 9, wherein in each frame period, the deterioration compensation circuit outputs the corrected video data for the selected one of the first to n-th pixel regions to the panel controller. The signal correction unit further includes a latch connected to an input of the arithmetic circuit, and the video data is input to the arithmetic circuit via the latch, and the latch is corrected in each frame period. The display device according to claim 10, wherein video data for the selected one of the first to nth pixel regions is sampled and input to the arithmetic circuit. The counter unit includes an adder and a latch connected to an input terminal of the adder,
In each frame period, the corrected video data for the selected one of the first to nth pixel regions is sent from the arithmetic circuit to the latch of the counter unit,
The latch of the counter unit periodically samples the corrected video data and sends it to the adder,
The adder reads the accumulated lighting time of the pixels belonging to the pixel area to which the corrected video data is sent to the adder from the storage circuit unit, and adds the corrected video data to the read accumulated lighting time. The display device according to claim 11, wherein the cumulative lighting time is updated. In each frame period, the deterioration compensation circuit outputs the corrected video data for the selected one of the first to nth pixel regions and the uncorrected video data for the other pixel regions to the panel controller. The display device according to claim 9, wherein The signal correction unit further includes a selector provided between the arithmetic circuit and the correction data storage unit, the selector has two input ends and one output end, and the output end is the correction unit. Connected to an input terminal of the circuit, one of the two input terminals is connected to an output terminal of the correction data storage unit, and a predetermined value is input to the other of the two input terminals,
The selector stores the correction stored in the correction data storage unit when video data for the selected one of the first to nth pixel regions is input to the arithmetic circuit in each frame period. Data is input to the arithmetic circuit, and when video data of another pixel region is input to the arithmetic circuit, the predetermined value is input to the arithmetic circuit, and the predetermined value 14. The display device according to claim 13, wherein the display device is a value that does not change the video data even when the arithmetic circuit performs an operation on the video data using the predetermined value. The counter unit includes an adder and a latch connected to an input terminal of the adder;
In each frame period, the corrected video data for the selected one of the first to nth pixel regions and the uncorrected video data for the other pixel regions are sent from the arithmetic circuit to the latch of the counter unit,
The latch of the counter unit periodically samples correction video data for the selected one of the first to n-th pixel regions and sends it to the adder,
The adder reads the accumulated lighting time of the pixels belonging to the pixel area to which the corrected video data is sent to the adder from the storage circuit unit, and adds the corrected video data to the read accumulated lighting time. The display device according to claim 14, wherein the cumulative lighting time is updated. 16. The display device according to claim 1, wherein a time gray scale method is used. An electronic apparatus comprising the display device according to claim 1.

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