JP2008153367A - Semiconductor device, and its manufacturing method - Google Patents

Semiconductor device, and its manufacturing method Download PDF

Info

Publication number
JP2008153367A
JP2008153367A JP2006338599A JP2006338599A JP2008153367A JP 2008153367 A JP2008153367 A JP 2008153367A JP 2006338599 A JP2006338599 A JP 2006338599A JP 2006338599 A JP2006338599 A JP 2006338599A JP 2008153367 A JP2008153367 A JP 2008153367A
Authority
JP
Japan
Prior art keywords
electrode
soft
semiconductor device
hard
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006338599A
Other languages
Japanese (ja)
Other versions
JP4853644B2 (en
Inventor
Satoru Miyairi
哲 宮入
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2006338599A priority Critical patent/JP4853644B2/en
Publication of JP2008153367A publication Critical patent/JP2008153367A/en
Application granted granted Critical
Publication of JP4853644B2 publication Critical patent/JP4853644B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Abstract

<P>PROBLEM TO BE SOLVED: To suppress occurrence of crack or cutting of a wiring disposed on a resinous layer. <P>SOLUTION: This semiconductor device has: a semiconductor substrate 10 having an integrated circuit 12 and an electrode 14 connected electrically to the integrated circuit 12; a passivation film 16 evading at least a part of the electrode 14 and located on the semiconductor substrate 10; a resinous layer 20 located on a part of the passivation film 16; and a wiring 30 connected electrically to the electrode 14 on the electrode 14, extending from the electrode 14 to the resinous layer 20 and coming into contact with a surface of the passivation film 16 between the electrode 14 and the resinous layer 20. The resinous layer 20 contains a hard part 22 and a soft part 24 of a relatively different hardness. At a portion overlapped with the wiring 30 of the resinous layer 20, a volume ratio occupied by the soft part 24 at an end on the opposite side to the electrode 14 is greater than that occupied by the soft part 24 at an end on the near side to the electrode 14. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

近年、電子機器の高性能化の要求に伴い、半導体装置の回路の高集積化が進み、配線の狭ピッチ化が要求されている。これに対応して、半導体チップに樹脂層を形成し、樹脂層上に配線を形成することで、狭いピッチで多数の配線を形成する技術が開発されている（特許文献１参照）。しかしながら、これまでに知られている技術では、樹脂の上に配線を形成するので、樹脂の変形に伴って配線の亀裂・切断が発生するおそれがあり、対策が求められている。
特開２００１−１１０８３１号公報 In recent years, along with the demand for higher performance of electronic equipment, higher integration of circuits of semiconductor devices has progressed, and there is a demand for narrower wiring pitches. Corresponding to this, a technique has been developed in which a resin layer is formed on a semiconductor chip and wirings are formed on the resin layer, thereby forming a large number of wirings at a narrow pitch (see Patent Document 1). However, in the techniques known so far, since the wiring is formed on the resin, there is a possibility that the wiring may be cracked or cut along with the deformation of the resin, and a countermeasure is required.
JP 2001-110831 A

本発明は、樹脂層上に配置した配線の亀裂・切断の発生を抑えることを目的とする。   An object of this invention is to suppress generation | occurrence | production of the crack and cutting | disconnection of the wiring arrange | positioned on the resin layer.

（１）本発明に係る半導体装置は、
集積回路及び前記集積回路に電気的に接続された電極を有する半導体基板と、
前記電極の少なくとも一部を避けて前記半導体基板上に位置するパッシベーション膜と、
前記パッシベーション膜の一部上に位置する樹脂層と、
前記電極上で前記電極に電気的に接続し、前記電極から前記樹脂層上に延びる配線と、
を有し、
前記樹脂層は、硬質部及び前記硬質部よりも軟らかい軟質部を含み、
前記樹脂層の前記配線とオーバーラップする部分において、前記電極とは反対側の端部で前記軟質部が占める体積比率が、前記電極に近い側の端部で前記軟質部が占める体積比率よりも大きい。本発明によれば、樹脂層が、電極とは反対側の端部においてその柔らかさゆえに変形しやすくなって応力を吸収するため、電極に近い側の端部の変形を抑えることができる。したがって、電極に近い側の端部上での配線の亀裂・切断の発生を抑えることができる。一方、電極とは反対側の端部上では、配線に亀裂・切断が発生しても電極との電気的な接続に影響がない。
（２）この半導体装置において、
前記樹脂層の、前記電極に近い側の前記端部では、前記軟質部が占める体積比率が０％であってもよい。
（３）この半導体装置において、
前記樹脂層の、前記電極とは反対側の前記端部では、前記軟質部が占める体積比率が１００％であってもよい。
（４）この半導体装置において、
前記樹脂層の、前記電極とは反対側の前記端部では、前記軟質部の少なくとも一部を覆うように前記硬質部が位置していてもよい。
（５）この半導体装置において、
前記配線は、前記樹脂層の、前記電極とは反対側の前記端部を越えて、前記パッシベーション膜上に到るように配置されていてもよい。
（６）この半導体装置において、
前記配線は、前記樹脂層の、前記電極とは反対側の前記端部上に先端が位置していてもよい。
（７）本発明に係る半導体装置の製造方法は、
（ａ）集積回路及び前記集積回路に電気的に接続された電極を有し、パッシベーション膜が前記電極の少なくとも一部を避けて位置する半導体基板を用意する工程と、
（ｂ）前記パッシベーション膜の一部上に、硬質部及び前記硬質部よりも軟らかい軟質部を含むように、樹脂層を形成する工程と、
（ｃ）前記電極上で前記電極に電気的に接続し、前記電極から前記樹脂層上に延びるように、配線を形成する工程と、
を含み、
前記（ｂ）工程で、前記電極とは反対側の端部で前記軟質部が占める体積比率が、前記電極に近い側の端部で前記軟質部が占める体積比率よりも大きくなるように、前記樹脂層を形成し、
前記（ｃ）工程で、前記樹脂層の、前記電極に近い側の前記端部上から、前記電極とは反対側の前記端部上に、前記配線を形成する。本発明によれば、樹脂層が、電極とは反対側の端部においてその柔らかさゆえに変形しやすくなって応力を吸収するため、電極に近い側の端部の変形を抑えることができる。したがって、電極に近い側の端部上での配線の亀裂・切断の発生を抑えることができる。一方、電極とは反対側の端部上では、配線に亀裂・切断が発生しても電極との電気的な接続に影響がない。
（８）この半導体装置の製造方法において、
前記（ｂ）工程は、
前記軟質部を構成するための軟質樹脂前駆体層を形成する工程と、
前記軟質樹脂前駆体層をパターニングし、前記パッシベーション膜の一部に前記軟質樹脂前駆体層を残す工程と、
前記硬質部を構成するための硬質樹脂前駆体層を、前記パターニングされた軟質樹脂前駆体層を覆うように形成する工程と、
前記硬質樹脂前駆体層をパターニングし、前記パッシベーション膜の一部に前記硬質樹脂前駆体層を残す工程と、
を含んでもよい。
（９）この半導体装置の製造方法において、
前記（ｂ）工程は、
前記軟質部を構成するための軟質樹脂前駆体層を形成する工程と、
前記軟質樹脂前駆体層をパターニングし、前記パッシベーション膜の一部に前記軟質樹脂前駆体層を残す工程と、
前記パターニングされた軟質樹脂前駆体層を加熱し、前記軟質部を形成する工程と、
前記軟質部を形成する工程の後、前記硬質部を構成するための硬質樹脂前駆体層を、前記軟質部を覆うように形成する工程と、
前記硬質樹脂前駆体層をパターニングし、前記パッシベーション膜の一部に前記硬質樹脂前駆体層を残して前記硬質部を形成する工程と、
を含んでもよい。 (1) A semiconductor device according to the present invention includes:
A semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit;
A passivation film located on the semiconductor substrate avoiding at least a portion of the electrode;
A resin layer located on a portion of the passivation film;
A wiring electrically connected to the electrode on the electrode and extending from the electrode onto the resin layer;
Have
The resin layer includes a hard part and a soft part softer than the hard part,
In the portion of the resin layer that overlaps the wiring, the volume ratio occupied by the soft portion at the end opposite to the electrode is larger than the volume ratio occupied by the soft portion at the end near the electrode. large. According to the present invention, the resin layer easily deforms and absorbs stress at the end opposite to the electrode because of its softness, so that deformation of the end near the electrode can be suppressed. Therefore, it is possible to suppress the occurrence of cracking and cutting of the wiring on the end near the electrode. On the other hand, on the end opposite to the electrode, even if cracks or cuts occur in the wiring, the electrical connection with the electrode is not affected.
(2) In this semiconductor device,
In the end portion of the resin layer on the side close to the electrode, the volume ratio occupied by the soft portion may be 0%.
(3) In this semiconductor device,
The volume ratio occupied by the soft portion may be 100% at the end portion of the resin layer opposite to the electrode.
(4) In this semiconductor device,
The hard part may be located so as to cover at least a part of the soft part at the end of the resin layer opposite to the electrode.
(5) In this semiconductor device,
The wiring may be disposed so as to reach the passivation film beyond the end of the resin layer opposite to the electrode.
(6) In this semiconductor device,
A tip of the wiring may be located on the end of the resin layer opposite to the electrode.
(7) A method for manufacturing a semiconductor device according to the present invention includes:
(A) providing a semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit, wherein the passivation film is located avoiding at least a part of the electrode;
(B) forming a resin layer on a part of the passivation film so as to include a hard part and a soft part softer than the hard part;
(C) electrically connecting to the electrode on the electrode and forming a wiring so as to extend from the electrode onto the resin layer;
Including
In the step (b), the volume ratio occupied by the soft portion at the end opposite to the electrode is larger than the volume ratio occupied by the soft portion at the end close to the electrode. Forming a resin layer,
In the step (c), the wiring is formed on the end portion of the resin layer on the side opposite to the electrode from the end portion on the side close to the electrode. According to the present invention, the resin layer easily deforms and absorbs stress at the end opposite to the electrode because of its softness, so that deformation of the end near the electrode can be suppressed. Therefore, it is possible to suppress the occurrence of cracking and cutting of the wiring on the end near the electrode. On the other hand, on the end opposite to the electrode, even if cracks or cuts occur in the wiring, the electrical connection with the electrode is not affected.
(8) In this method of manufacturing a semiconductor device,
The step (b)
Forming a soft resin precursor layer for constituting the soft part;
Patterning the soft resin precursor layer, leaving the soft resin precursor layer in a portion of the passivation film;
Forming a hard resin precursor layer for constituting the hard portion so as to cover the patterned soft resin precursor layer;
Patterning the hard resin precursor layer and leaving the hard resin precursor layer in a portion of the passivation film;
May be included.
(9) In this method of manufacturing a semiconductor device,
The step (b)
Forming a soft resin precursor layer for constituting the soft part;
Patterning the soft resin precursor layer, leaving the soft resin precursor layer in a portion of the passivation film;
Heating the patterned soft resin precursor layer to form the soft portion;
After the step of forming the soft portion, a step of forming a hard resin precursor layer for constituting the hard portion so as to cover the soft portion;
Patterning the hard resin precursor layer, leaving the hard resin precursor layer in a part of the passivation film, and forming the hard portion; and
May be included.

図１（Ａ）は、本発明の実施の形態に係る半導体装置を示す平面図であり、図１（Ｂ）は、半導体装置の、図１（Ａ）に示すＩＢ−ＩＢ線断面の一部を示す図である。半導体装置は、半導体基板１０を有する。半導体基板１０は、図１（Ａ）に示す最終製品としての半導体装置においては半導体チップであるが、最終製品を得る前の段階では、半導体ウエハである。半導体ウエハを切断して半導体チップが得られる。半導体基板１０には、集積回路１２（半導体チップには１つの集積回路１２／半導体ウエハには複数の集積回路１２）が形成されている。半導体基板１０は、内部配線（図示せず）を介して集積回路１２に電気的に接続された電極１４を有する。図１（Ａ）の例では、半導体基板１０が一方向に長い形状（平面形状が長方形）であって、長い方の辺に沿って、複数の電極１４が配列されている。半導体基板１０には、電極１４の少なくとも一部が露出する様にパッシベーション膜１６が形成されている。パッシベーション膜１６は、例えば、ＳｉＯ２やＳｉＮ等の無機材料のみで形成されていてもよいし、無機材料からなる層とポリイミド樹脂などの有機材料からなる層の複数層から形成されてもよい。 1A is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a part of a cross section taken along line IB-IB in FIG. 1A of the semiconductor device. FIG. The semiconductor device has a semiconductor substrate 10. The semiconductor substrate 10 is a semiconductor chip in the semiconductor device as the final product shown in FIG. 1A, but is a semiconductor wafer in a stage before obtaining the final product. A semiconductor chip is obtained by cutting the semiconductor wafer. An integrated circuit 12 (one integrated circuit 12 for a semiconductor chip / a plurality of integrated circuits 12 for a semiconductor wafer) is formed on the semiconductor substrate 10. The semiconductor substrate 10 has an electrode 14 that is electrically connected to the integrated circuit 12 via internal wiring (not shown). In the example of FIG. 1A, the semiconductor substrate 10 has a shape that is long in one direction (planar shape is rectangular), and a plurality of electrodes 14 are arranged along the longer side. A passivation film 16 is formed on the semiconductor substrate 10 so that at least a part of the electrode 14 is exposed. For example, the passivation film 16 may be formed of only an inorganic material such as SiO 2 or SiN, or may be formed of a plurality of layers including a layer made of an inorganic material and a layer made of an organic material such as polyimide resin.

パッシベーション膜１６の一部上には樹脂層２０が形成されている。樹脂層２０は、相対的に硬さ（ヤング率・圧縮強度）の異なる硬質部２２及び硬質部２２よりも軟らかい軟質部２４を含む。例えば、ポリイミド樹脂（圧縮強度２５３ｋｇ／ｃｍ２）、ポリカーボネート樹脂（圧縮強度７６０ｋｇ／ｃｍ２）、アクリル樹脂（圧縮強度１２６０ｋｇ／ｃｍ２）のうち２つを組み合わせて硬質部２２及び軟質部２４を構成することができる。図１（Ａ）の例では、半導体基板１０の長手方向（電極１４の配列方向）に沿って（平行に）、連続的に樹脂層２０（硬質部２２及び軟質部２４のそれぞれ）が延びている。あるいは、硬質部２２及び軟質部２４の一方のみが断続的に（間隔をあけて途切れるように）形成されていてもよい。 A resin layer 20 is formed on part of the passivation film 16. The resin layer 20 includes a hard portion 22 having a relatively different hardness (Young's modulus and compressive strength) and a soft portion 24 that is softer than the hard portion 22. For example, the hard portion 22 and the soft portion 24 are configured by combining two of polyimide resin (compressive strength 253 kg / cm 2 ), polycarbonate resin (compressive strength 760 kg / cm 2 ), and acrylic resin (compressive strength 1260 kg / cm 2 ). can do. In the example of FIG. 1A, the resin layer 20 (each of the hard part 22 and the soft part 24) continuously extends along (in parallel) the longitudinal direction of the semiconductor substrate 10 (the arrangement direction of the electrodes 14). Yes. Alternatively, only one of the hard portion 22 and the soft portion 24 may be formed intermittently (so as to be interrupted at intervals).

樹脂層２０の配線３０とオーバーラップする部分において、電極１４とは反対側の端部（中心よりも電極１４の反対側の部分）２６で軟質部２４が占める体積比率が、電極１４に近い側の端部（中心よりも電極１４に近い側の部分）２８で軟質部２４が占める体積比率よりも大きい。なお、端部２６，２８の体積が同じであることを前提とする。端部２６，２８の体積が、それぞれ、樹脂層２０の配線３０とオーバーラップする部分の１／２であってもよい。本実施の形態では、樹脂層２０の、電極１４に近い側の端部２８では、軟質部２４が占める体積比率が０％である（すなわち軟質層が存在しない）。樹脂層２０の、電極１４とは反対側の端部２６では、軟質部２４の少なくとも一部を覆うように硬質部２２が位置していてもよい。   In the portion of the resin layer 20 that overlaps the wiring 30, the volume ratio occupied by the soft portion 24 at the end portion 26 on the opposite side of the electrode 14 (the portion on the opposite side of the electrode 14 from the center) is closer to the electrode 14. Is larger than the volume ratio occupied by the soft portion 24 at the end portion 28 (the portion closer to the electrode 14 than the center). It is assumed that the ends 26 and 28 have the same volume. The volumes of the end portions 26 and 28 may each be ½ of the portion overlapping the wiring 30 of the resin layer 20. In the present embodiment, the volume ratio occupied by the soft portion 24 is 0% at the end portion 28 on the side close to the electrode 14 of the resin layer 20 (that is, there is no soft layer). The hard portion 22 may be positioned so as to cover at least a part of the soft portion 24 at the end portion 26 of the resin layer 20 opposite to the electrode 14.

樹脂層２０上には配線３０が形成されている。配線３０は、電極１４上で電極１４に電気的に接続している。すなわち、配線３０と電極１４は直接接触していてもよいし、両者間に導電膜（図示せず）が介在していてもよい。配線３０は、電極１４から樹脂層２０上に延びている。配線３０は、電極１４と樹脂層２０の間でパッシベーション膜１６の表面に接触している。配線３０は、樹脂層２０の、電極１４とは反対側の端部２６を越えて、パッシベーション膜１６上に到るように形成されている。   A wiring 30 is formed on the resin layer 20. The wiring 30 is electrically connected to the electrode 14 on the electrode 14. That is, the wiring 30 and the electrode 14 may be in direct contact, or a conductive film (not shown) may be interposed between them. The wiring 30 extends from the electrode 14 onto the resin layer 20. The wiring 30 is in contact with the surface of the passivation film 16 between the electrode 14 and the resin layer 20. The wiring 30 is formed so as to reach the passivation film 16 beyond the end portion 26 of the resin layer 20 opposite to the electrode 14.

本実施の形態によれば、樹脂層２０が、電極１４とは反対側の端部２６においてその柔らかさゆえに変形しやすくなって応力を吸収するため、電極１４に近い側の端部２８の変形を抑えることができる。したがって、電極１４に近い側の端部２８上での配線３０の亀裂・切断の発生を抑えることができる。一方、電極１４とは反対側の端部２６上では、配線３０に亀裂・切断が発生しても電極１４との電気的な接続に影響がない。   According to the present embodiment, the resin layer 20 is easily deformed at the end portion 26 on the side opposite to the electrode 14 due to its softness and absorbs stress, so that the deformation of the end portion 28 near the electrode 14 is performed. Can be suppressed. Therefore, it is possible to suppress the occurrence of cracking / cutting of the wiring 30 on the end portion 28 on the side close to the electrode 14. On the other hand, on the end 26 opposite to the electrode 14, even if the wiring 30 is cracked or cut, the electrical connection with the electrode 14 is not affected.

（変形例）
図２は、上記実施の形態の第１の変形例を示す図である。この変形例では、樹脂層１２０の構造が上記実施の形態と異なっている。樹脂層１２０の、電極１４とは反対側の端部で、軟質部１２４の一部（端部）が硬質部１２２から露出している。樹脂層１２０の、電極１４とは反対側の端部では、軟質部１２４が占める体積比率が１００％である。軟質部１２４の一部（端部）が、硬質部１２２から横（半導体基板１０の表面に平行方向）に突出し、硬質部１２２と軟質部１２４の境目に段（窪み）が形成される。配線１３０は、硬質部１２２の表面と軟質部１２４の表面に接触していてもよい。 (Modification)
FIG. 2 is a diagram showing a first modification of the above embodiment. In this modification, the structure of the resin layer 120 is different from that of the above embodiment. At the end of the resin layer 120 opposite to the electrode 14, a part (end) of the soft portion 124 is exposed from the hard portion 122. At the end of the resin layer 120 opposite to the electrode 14, the volume ratio occupied by the soft portion 124 is 100%. A part (end) of the soft portion 124 protrudes laterally (in a direction parallel to the surface of the semiconductor substrate 10) from the hard portion 122, and a step (dent) is formed at the boundary between the hard portion 122 and the soft portion 124. The wiring 130 may be in contact with the surface of the hard part 122 and the surface of the soft part 124.

図３は、上記実施の形態の第２の変形例を示す図である。この変形例では、樹脂層２２０の、電極１４とは反対側の端部で、軟質部２２４の一部（端部）が硬質部２２２から露出しているが、軟質部２２４と硬質部２２２の境目がなだらかな（窪みを有しない）曲面を描いている。その上の配線２３０もなだらかな（窪みを有しない）曲面を描く形状になっている。   FIG. 3 is a diagram showing a second modification of the above embodiment. In this modification, at the end of the resin layer 220 opposite to the electrode 14, a part (end) of the soft part 224 is exposed from the hard part 222, but the soft part 224 and the hard part 222 The curved line has a gentle boundary (no dent). The wiring 230 thereabove also has a shape that draws a gentle (no dent) curved surface.

図４は、上記実施の形態の第３の変形例を示す図である。この変形例では、配線３３０は、樹脂層２２０の、電極１４とは反対側の端部を越えずにその端部上に先端が位置している。   FIG. 4 is a diagram showing a third modification of the above embodiment. In this modification, the end of the wiring 330 is positioned on the end of the resin layer 220 without exceeding the end of the resin layer 220 opposite to the electrode 14.

図５は、上記実施の形態の第４の変形例を示す図である。この変形例では、１つの樹脂層４２０上に１つの配線４３０が形成されている点で、図１（Ａ）の例（１つの樹脂層２０上に複数の配線３０）とは異なっている。この例にも、上記第１〜３の変形例の内容を適用することが可能である。   FIG. 5 is a diagram showing a fourth modification of the above embodiment. This modification is different from the example of FIG. 1A (a plurality of wirings 30 on one resin layer 20) in that one wiring 430 is formed on one resin layer 420. The contents of the first to third modifications can also be applied to this example.

（製造方法）
図６（Ａ）〜図６（Ｄ）は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。本実施の形態では、上述した半導体基板（例えば半導体ウエハ）１０を使用し、パッシベーション膜１６の一部上に、相対的に硬さの異なる硬質部１２２及び軟質部１２４を含むように樹脂層１２０を形成する（図２参照）。なお、樹脂前駆体が化学反応（重合反応・架橋反応）して樹脂になる。 (Production method)
6A to 6D are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the present embodiment, the above-described semiconductor substrate (for example, a semiconductor wafer) 10 is used, and a resin layer 120 is included on a portion of the passivation film 16 so as to include a hard portion 122 and a soft portion 124 having relatively different hardnesses. (See FIG. 2). The resin precursor is chemically reacted (polymerization reaction / crosslinking reaction) to become a resin.

詳しくは、軟質部１２４を構成するための軟質樹脂前駆体層１４０を形成する（図６（Ａ）参照）。軟質樹脂前駆体層１４０をパターニングし、パッシベーション膜１６の一部に軟質樹脂前駆体層１４０を残す（図６（Ｂ）参照）。パターニングにはフォトリソグラフィを適用してもよい。そして、硬質部１２２を構成するための硬質樹脂前駆体層１５０を、パターニングされた軟質樹脂前駆体層１４０を覆うように形成する（図６（Ｃ）参照）。硬質樹脂前駆体層１５０をパターニングし、パッシベーション膜１６の一部に硬質樹脂前駆体層１５０を残す（図６（Ｄ）参照）。その後、パターニングされた軟質樹脂前駆体層１４０及びパターニングされた硬質樹脂前駆体層１５０を加熱して溶融すると、表面張力で表面が曲面になる。そして、軟質樹脂前駆体層１４０及び硬質樹脂前駆体層１５０を化学反応（重合反応・架橋反応）させて、表面が曲面になった硬質部１２２及び軟質部１２４が得られる（図２参照）。なお、軟質樹脂前駆体層１４０及び硬質樹脂前駆体層１５０の材料として熱可塑性樹脂を使用してもよいが、熱硬化性樹脂であっても硬化反応前には熱によって溶融するので表面を曲面にすることができる。   Specifically, a soft resin precursor layer 140 for forming the soft portion 124 is formed (see FIG. 6A). The soft resin precursor layer 140 is patterned to leave the soft resin precursor layer 140 in part of the passivation film 16 (see FIG. 6B). Photolithography may be applied for patterning. And the hard resin precursor layer 150 for comprising the hard part 122 is formed so that the patterned soft resin precursor layer 140 may be covered (refer FIG.6 (C)). The hard resin precursor layer 150 is patterned to leave the hard resin precursor layer 150 in a part of the passivation film 16 (see FIG. 6D). Thereafter, when the patterned soft resin precursor layer 140 and the patterned hard resin precursor layer 150 are heated and melted, the surface becomes a curved surface due to surface tension. Then, the soft resin precursor layer 140 and the hard resin precursor layer 150 are chemically reacted (polymerization reaction / crosslinking reaction) to obtain a hard portion 122 and a soft portion 124 having curved surfaces (see FIG. 2). A thermoplastic resin may be used as the material of the soft resin precursor layer 140 and the hard resin precursor layer 150. However, even a thermosetting resin is melted by heat before the curing reaction, so the surface is curved. Can be.

さらに、配線１３０を形成する（図２参照）。配線１３０は、電極１４上で電極１４に電気的に接続し、電極１４から樹脂層１２０上に延び、電極１４と樹脂層１２０の間でパッシベーション膜１６の表面に接触するように形成する。その他の詳細は、上述した半導体装置の構造から自明な製造方法であるため説明を省略する。   Further, a wiring 130 is formed (see FIG. 2). The wiring 130 is electrically connected to the electrode 14 on the electrode 14, extends from the electrode 14 onto the resin layer 120, and is formed so as to contact the surface of the passivation film 16 between the electrode 14 and the resin layer 120. Since other details are a manufacturing method that is obvious from the structure of the semiconductor device described above, description thereof is omitted.

図７（Ａ）〜図７（Ｂ）は、上記実施の形態の変形例に係る半導体装置の製造方法を説明する図である。この変形例では、硬質樹脂前駆体層１５０を形成する前に、パターニングされた軟質樹脂前駆体層１４０（図６（Ｂ）参照）を化学反応（重合反応・架橋反応）させて軟質部１２４にする。軟質部１２４は、表面が曲面になるように形成する。表面を曲面にするのに加熱すればよいことは上述した通りである。そして、図７（Ａ）に示すように、軟質部１２４を覆うように、硬質部１２２（図２参照）を構成するための硬質樹脂前駆体層１５０を形成する。続いて、図７（Ｂ）に示すように、硬質樹脂前駆体層１５０をパターニングし、これを化学反応（重合反応・架橋反応）させて硬質部１２２（図２参照）を形成する。以上のプロセス及びその後のプロセスには、上述した半導体装置の製造方法の内容を適用することができる。   7A to 7B are diagrams illustrating a method for manufacturing a semiconductor device according to a variation of the above embodiment. In this modification, before the hard resin precursor layer 150 is formed, the patterned soft resin precursor layer 140 (see FIG. 6B) is chemically reacted (polymerization reaction / crosslinking reaction) to form the soft portion 124. To do. The soft part 124 is formed so that the surface becomes a curved surface. As described above, the surface may be heated to form a curved surface. Then, as shown in FIG. 7A, a hard resin precursor layer 150 for forming the hard portion 122 (see FIG. 2) is formed so as to cover the soft portion 124. Subsequently, as shown in FIG. 7B, the hard resin precursor layer 150 is patterned, and this is subjected to a chemical reaction (polymerization reaction / crosslinking reaction) to form a hard portion 122 (see FIG. 2). The contents of the semiconductor device manufacturing method described above can be applied to the above process and subsequent processes.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

図１（Ａ）は、本発明の実施の形態に係る半導体装置を示す平面図であり、図１（Ｂ）は、半導体装置の、図１（Ａ）に示すＩＢ−ＩＢ線断面の一部を示す図である。1A is a plan view showing a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a part of a cross section taken along line IB-IB in FIG. 1A of the semiconductor device. FIG. 上記実施の形態の第１の変形例を示す図である。It is a figure which shows the 1st modification of the said embodiment. 上記実施の形態の第２の変形例を示す図である。It is a figure which shows the 2nd modification of the said embodiment. 上記実施の形態の第３の変形例を示す図である。It is a figure which shows the 3rd modification of the said embodiment. 上記実施の形態の第４の変形例を示す図である。It is a figure which shows the 4th modification of the said embodiment. 図６（Ａ）〜図６（Ｄ）は、本発明の実施の形態に係る半導体装置の製造方法を説明する図である。6A to 6D are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 図７（Ａ）〜図７（Ｂ）は、上記実施の形態の変形例に係る半導体装置の製造方法を説明する図である。7A to 7B are diagrams illustrating a method for manufacturing a semiconductor device according to a variation of the above embodiment.

符号の説明Explanation of symbols

１０…半導体基板、 １２…集積回路、 １４…電極、 １６…パッシベーション膜、 ２０…樹脂層、 ２２…硬質部、 ２４…軟質部、 ２６…端部、 ２８…端部、 ３０…配線、 １２０…樹脂層、 １２２…硬質部、 １２４…軟質部、 １３０…配線、 １４０…軟質樹脂前駆体層、 １５０…硬質樹脂前駆体層、 ２２０…樹脂層、 ２２２…硬質部、 ２２４…軟質部、 ２３０…配線、 ３３０…配線、 ４２０…樹脂層、 ４３０…配線   DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 12 ... Integrated circuit, 14 ... Electrode, 16 ... Passivation film, 20 ... Resin layer, 22 ... Hard part, 24 ... Soft part, 26 ... End part, 28 ... End part, 30 ... Wiring, 120 ... Resin layer, 122 ... hard portion, 124 ... soft portion, 130 ... wiring, 140 ... soft resin precursor layer, 150 ... hard resin precursor layer, 220 ... resin layer, 222 ... hard portion, 224 ... soft portion, 230 ... Wiring, 330 ... wiring, 420 ... resin layer, 430 ... wiring

Claims (9)

集積回路及び前記集積回路に電気的に接続された電極を有する半導体基板と、
前記電極の少なくとも一部を避けて前記半導体基板上に位置するパッシベーション膜と、
前記パッシベーション膜の一部上に位置する樹脂層と、
前記電極上で前記電極に電気的に接続し、前記電極から前記樹脂層上に延びる配線と、
を有し、
前記樹脂層は、硬質部及び前記硬質部よりも軟らかい軟質部を含み、
前記樹脂層の前記配線とオーバーラップする部分において、前記電極とは反対側の端部で前記軟質部が占める体積比率が、前記電極に近い側の端部で前記軟質部が占める体積比率よりも大きい半導体装置。 A semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit;
A passivation film located on the semiconductor substrate avoiding at least a portion of the electrode;
A resin layer located on a portion of the passivation film;
A wiring electrically connected to the electrode on the electrode and extending from the electrode onto the resin layer;
Have
The resin layer includes a hard part and a soft part softer than the hard part,
In the portion of the resin layer that overlaps the wiring, the volume ratio occupied by the soft portion at the end opposite to the electrode is larger than the volume ratio occupied by the soft portion at the end near the electrode. Large semiconductor device. 請求項１に記載された半導体装置において、
前記樹脂層の、前記電極に近い側の前記端部では、前記軟質部が占める体積比率が０％である半導体装置。 The semiconductor device according to claim 1,
The semiconductor device in which a volume ratio occupied by the soft portion is 0% at the end portion of the resin layer on the side close to the electrode. 請求項１又は２に記載された半導体装置において、
前記樹脂層の、前記電極とは反対側の前記端部では、前記軟質部が占める体積比率が１００％である半導体装置。 The semiconductor device according to claim 1 or 2,
The semiconductor device in which a volume ratio occupied by the soft portion is 100% at the end portion of the resin layer opposite to the electrode. 請求項１又は２に記載された半導体装置において、
前記樹脂層の、前記電極とは反対側の前記端部では、前記軟質部の少なくとも一部を覆うように前記硬質部が位置している半導体装置。 The semiconductor device according to claim 1 or 2,
The semiconductor device in which the hard portion is positioned so as to cover at least a part of the soft portion at the end portion of the resin layer opposite to the electrode. 請求項１から４のいずれか1項に記載された半導体装置において、
前記配線は、前記樹脂層の、前記電極とは反対側の前記端部を越えて、前記パッシベーション膜上に到るように配置されてなる半導体装置。 5. The semiconductor device according to claim 1, wherein:
The semiconductor device, wherein the wiring is disposed so as to reach the passivation film beyond the end of the resin layer opposite to the electrode. 請求項１から４のいずれか1項に記載された半導体装置において、
前記配線は、前記樹脂層の、前記電極とは反対側の前記端部上に先端が位置してなる半導体装置。 5. The semiconductor device according to claim 1, wherein:
The wiring is a semiconductor device in which a tip is located on the end of the resin layer opposite to the electrode. （ａ）集積回路及び前記集積回路に電気的に接続された電極を有し、パッシベーション膜が前記電極の少なくとも一部を避けて位置する半導体基板を用意する工程と、
（ｂ）前記パッシベーション膜の一部上に、硬質部及び前記硬質部よりも軟らかい軟質部を含むように、樹脂層を形成する工程と、
（ｃ）前記電極上で前記電極に電気的に接続し、前記電極から前記樹脂層上に延び、るように、配線を形成する工程と、
を含み、
前記（ｂ）工程で、前記電極とは反対側の端部で前記軟質部が占める体積比率が、前記電極に近い側の端部で前記軟質部が占める体積比率よりも大きくなるように、前記樹脂層を形成し、
前記（ｃ）工程で、前記樹脂層の、前記電極に近い側の前記端部上から、前記電極とは反対側の前記端部上に、前記配線を形成する半導体装置の製造方法。 (A) providing a semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit, wherein the passivation film is located avoiding at least a part of the electrode;
(B) forming a resin layer on a part of the passivation film so as to include a hard part and a soft part softer than the hard part;
(C) forming a wiring so as to be electrically connected to the electrode on the electrode and extend from the electrode onto the resin layer;
Including
In the step (b), the volume ratio occupied by the soft portion at the end opposite to the electrode is larger than the volume ratio occupied by the soft portion at the end close to the electrode. Forming a resin layer,
The manufacturing method of the semiconductor device which forms the said wiring on the said edge part on the opposite side to the said electrode from the said edge part of the said resin layer near the said electrode by the said (c) process. 請求項７に記載された半導体装置の製造方法において、
前記（ｂ）工程は、
前記軟質部を構成するための軟質樹脂前駆体層を形成する工程と、
前記軟質樹脂前駆体層をパターニングし、前記パッシベーション膜の一部に前記軟質樹脂前駆体層を残す工程と、
前記硬質部を構成するための硬質樹脂前駆体層を、前記パターニングされた軟質樹脂前駆体層を覆うように形成する工程と、
前記硬質樹脂前駆体層をパターニングし、前記パッシベーション膜の一部に前記硬質樹脂前駆体層を残す工程と、
を含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 7,
The step (b)
Forming a soft resin precursor layer for constituting the soft part;
Patterning the soft resin precursor layer, leaving the soft resin precursor layer in a portion of the passivation film;
Forming a hard resin precursor layer for constituting the hard portion so as to cover the patterned soft resin precursor layer;
Patterning the hard resin precursor layer and leaving the hard resin precursor layer in a portion of the passivation film;
A method of manufacturing a semiconductor device including: 請求項７に記載された半導体装置の製造方法において、
前記（ｂ）工程は、
前記軟質部を構成するための軟質樹脂前駆体層を形成する工程と、
前記軟質樹脂前駆体層をパターニングし、前記パッシベーション膜の一部に前記軟質樹脂前駆体層を残す工程と、
前記パターニングされた軟質樹脂前駆体層を加熱し、前記軟質部を形成する工程と、
前記軟質部を形成する工程の後、前記硬質部を構成するための硬質樹脂前駆体層を、前記軟質部を覆うように形成する工程と、
前記硬質樹脂前駆体層をパターニングし、前記パッシベーション膜の一部に前記硬質樹脂前駆体層を残して前記硬質部を形成する工程と、
を含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 7,
The step (b)
Forming a soft resin precursor layer for constituting the soft part;
Patterning the soft resin precursor layer, leaving the soft resin precursor layer in a portion of the passivation film;
Heating the patterned soft resin precursor layer to form the soft portion;
After the step of forming the soft portion, a step of forming a hard resin precursor layer for constituting the hard portion so as to cover the soft portion;
Patterning the hard resin precursor layer, leaving the hard resin precursor layer in a part of the passivation film, and forming the hard portion; and
A method of manufacturing a semiconductor device including:
JP2006338599A 2006-12-15 2006-12-15 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4853644B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006338599A JP4853644B2 (en) 2006-12-15 2006-12-15 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006338599A JP4853644B2 (en) 2006-12-15 2006-12-15 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2008153367A true JP2008153367A (en) 2008-07-03
JP4853644B2 JP4853644B2 (en) 2012-01-11

Family

ID=39655248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006338599A Expired - Fee Related JP4853644B2 (en) 2006-12-15 2006-12-15 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4853644B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097394A (en) * 2009-12-15 2011-06-15 瑞萨电子株式会社 Semiconductor device and method for manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340369A (en) * 1998-03-23 1999-12-10 Seiko Epson Corp Semiconductor device, its manufacture, circuit board and electronic apparatus
JP2000150716A (en) * 1998-11-16 2000-05-30 Nec Corp Package structure and semiconductor device, manufacture of package and semiconductor device
JP2001110831A (en) * 1999-10-07 2001-04-20 Seiko Epson Corp External connecting protrusion and its forming method, semiconductor chip, circuit board and electronic equipment
JP2004509449A (en) * 2000-03-31 2004-03-25 インフィネオン　テクノロジーズ　アクチエンゲゼルシャフト Electronic component having flexible connection and method of manufacturing the same
JP2005340452A (en) * 2004-05-26 2005-12-08 Seiko Epson Corp Semiconductor device and its manufacturing method
JP2006093383A (en) * 2004-09-24 2006-04-06 Seiko Epson Corp Semiconductor device and its manufacturing method, circuit substrate, electro-optical device and electronic apparatus

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340369A (en) * 1998-03-23 1999-12-10 Seiko Epson Corp Semiconductor device, its manufacture, circuit board and electronic apparatus
JP2000150716A (en) * 1998-11-16 2000-05-30 Nec Corp Package structure and semiconductor device, manufacture of package and semiconductor device
JP2001110831A (en) * 1999-10-07 2001-04-20 Seiko Epson Corp External connecting protrusion and its forming method, semiconductor chip, circuit board and electronic equipment
JP2004509449A (en) * 2000-03-31 2004-03-25 インフィネオン　テクノロジーズ　アクチエンゲゼルシャフト Electronic component having flexible connection and method of manufacturing the same
JP2005340452A (en) * 2004-05-26 2005-12-08 Seiko Epson Corp Semiconductor device and its manufacturing method
JP2006093383A (en) * 2004-09-24 2006-04-06 Seiko Epson Corp Semiconductor device and its manufacturing method, circuit substrate, electro-optical device and electronic apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097394A (en) * 2009-12-15 2011-06-15 瑞萨电子株式会社 Semiconductor device and method for manufacturing the same
JP2011129578A (en) * 2009-12-15 2011-06-30 Renesas Electronics Corp Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JP4853644B2 (en) 2012-01-11

Similar Documents

Publication Publication Date Title
JP2008258258A (en) Semiconductor device
JP2007067332A (en) Semiconductor device
JP2006253289A5 (en)
TW202105839A (en) Flexible electronic device
JP2009033010A (en) Electronic device and method of manufacturing the same, and semiconductor device
JP4147433B2 (en) Semiconductor device and manufacturing method thereof
JP4061506B2 (en) Manufacturing method of semiconductor device
JP4853644B2 (en) Semiconductor device and manufacturing method thereof
JP4145902B2 (en) Semiconductor device and manufacturing method thereof
JP2009158741A5 (en)
JP2006229018A (en) Tape carrier substrate, its manufacturing method and semiconductor device
JP2007019408A (en) Semiconductor device
JP2005101144A (en) Semiconductor device and method for manufacturing semiconductor device
JP4273356B2 (en) Manufacturing method of semiconductor device
JP2007201044A (en) Electronic device
US20080224331A1 (en) Electronic device and method for manufacturing the same
JP2009260389A (en) Semiconductor device
TW202103528A (en) Stress relief structures on outer frame of rigid-flex hybrid circuit boards
TWI730819B (en) Electronic device
JP2006173434A (en) Wiring board, and semiconductor device, and its manufacturing method
JP2006173435A (en) Wiring board, semiconductor device, and its manufacturing method
JP2007281216A (en) Semiconductor device, method of manufacturing same, and electronic apparatus
JP6459690B2 (en) Electronic component and manufacturing method thereof
JP3449329B2 (en) Semiconductor integrated circuit
JP2012129376A (en) Semiconductor device

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20080701

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090806

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110706

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110707

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110905

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110928

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20111011

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20141104

Year of fee payment: 3

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees