JP2008152018A - Electro-optical device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electro-optical device and its manufacturing method capable of controlling the brightness of illumination light in an appropriate manner. <P>SOLUTION: The element panel 11 has a PIN structure photo detector 48 disposed at least a part on the outer periphery of the image display area, and its facing panel 12 has a green filter layer 74 overlapping the photo detector 48 in a plan view. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electro-optical device and a method for manufacturing the electro-optical device.

The liquid crystal display device is mainly composed of a pair of substrates and a liquid crystal layer sandwiched between the pair of substrates. For example, in a transmissive liquid crystal display device, backlight light is irradiated from the outside of one substrate, and the backlight light is modulated to display an image.
In such a liquid crystal display device, for example, the intensity of illumination light may be controlled when the intensity of ambient light is high, such as outdoors, and when the intensity of ambient light is low, such as indoors. As this liquid crystal display device, one having a light receiving element for receiving ambient light has been proposed (see, for example, Patent Document 1).
JP 2002-62856 A

  However, the following problems remain in the conventional liquid crystal display device. That is, the wavelength characteristic of sensitivity in the light receiving element depends on the material constituting the light receiving element. Therefore, the detection intensity of external light by the light receiving element is different from human visibility, and there is a problem that the intensity of illumination light cannot be controlled appropriately.

  SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device that can appropriately adjust the luminance of illumination light and a method for manufacturing the electro-optical device.

  The present invention employs the following configuration in order to solve the above problems. That is, an electro-optical device according to the present invention is an electro-optical device in which an electro-optical layer is sandwiched between a pair of substrates, and an image display region is provided in a formation region of the electro-optical layer, and the one substrate Has a light receiving element having a PIN structure provided on at least a part of the outer peripheral portion of the image display area, and one of the pair of substrates has a green filter layer overlapping the light receiving element in plan view. Features.

In this invention, when the light receiving element receives the environmental light transmitted through the green filter layer, the wavelength characteristic of the detection sensitivity of the light receiving element can be brought close to human visual sensitivity, and the luminance of the illumination light can be adjusted appropriately.
In other words, since human visibility is high in the wavelength band of green light, a detection result close to human sensitivity characteristics can be obtained by receiving the green ambient light transmitted through the green filter layer with the light receiving element. it can. Therefore, the brightness adjustment of the illumination light can be performed more appropriately.
Here, by providing the light receiving element on the outer periphery of the image display area that does not contribute to the image display in the image display area, the space can be used effectively.

In the electro-optical device according to the aspect of the invention, it is preferable that the light receiving element and a driving element for driving the electro-optical layer are formed on the same layer.
In the present invention, since the light receiving element and the drive element can be formed in the same process, the light receiving element can be formed without greatly increasing the number of manufacturing steps.

In the electro-optical device according to the aspect of the invention, it is preferable that the image display region has a substantially rectangular shape in plan view, and the light receiving elements are formed on at least two sides of the outer peripheral portion.
In the present invention, the light receiving area of the light receiving element is increased by forming it on at least two sides of the outer peripheral portion of the substantially rectangular image display region in plan view, and environmental light can be detected with higher accuracy.

In the electro-optical device according to the invention, the electro-optical layer may be a liquid crystal layer, and the pair of substrates may be bonded together with a sealing material.
In this invention, a pair of substrates are bonded together with a sealing material, and the liquid crystal layer is sealed with the pair of substrates and the sealing material, thereby functioning as a liquid crystal device.

In the electro-optical device according to the invention, it is preferable that the light receiving element is formed inside a region where the sealing material is formed.
According to the present invention, the space can be effectively used by providing the light receiving element in a region between the outer peripheral portion of the image display region and the inner side of the sealing material that does not contribute to image display.

Also, the electro-optical device according to the present invention includes a green filter and a color filter layer provided corresponding to a color displayed in a pixel area constituting the image display area. Preferably, the green filter layer and the color filter layer are formed on the same layer.
In this invention, a green filter layer can be formed without increasing a manufacturing process by forming a color filter layer and a green filter layer on the same layer.

The method for manufacturing an electro-optical device according to the present invention is a method for manufacturing an electro-optical device in which an electro-optical layer is sandwiched between a pair of substrates, and an image display region is provided in the formation region of the electro-optical layer. Forming a driving element for driving the electro-optic layer on the one substrate, and forming a light receiving element having a PIN structure on at least a part of the outer periphery of the image display region, and either of the pair of substrates. And a step of forming a green filter layer that overlaps the light receiving element in plan view, wherein the driving element and the light receiving element are formed on the same layer.
In the present invention, as described above, the wavelength characteristic of the detection sensitivity can be brought close to the human visual sensitivity, and the luminance of the illumination light can be adjusted appropriately. Here, since the drive element and the light receiving element are formed on the same layer, the drive element and the light receiving element can be formed in the same process, and the manufacturing process can be simplified.

[First Embodiment]
Hereinafter, a first embodiment of an electro-optical device according to the invention will be described with reference to the drawings. In each drawing used in the following description, the scale is appropriately changed to make each member a recognizable size. 1A shows a liquid crystal display device, FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along line AA in FIG. 2A, FIG. 2 is an equivalent circuit diagram showing the liquid crystal display device, and FIG. FIG. 4 is a cross-sectional view showing the outer periphery of the image display area, and FIG. 5 is a cross-sectional view showing the outside of the image display area.

[Liquid Crystal Display]
A liquid crystal display device (electro-optical device) 1 according to this embodiment is a transmissive color liquid crystal display device, and includes three sub-lights that output light of each color of R (red), G (green), and B (blue). This is a liquid crystal display device in which one pixel is formed in a pixel region. Here, the display area which is the minimum unit constituting the display is referred to as a “sub-pixel area (pixel area)”.

First, a schematic configuration of the liquid crystal display device 1 will be described. As shown in FIGS. 1A and 1B, the liquid crystal display device 1 includes an element substrate (one substrate) 11, a counter substrate (the other substrate) 12 disposed to face the element substrate 11, and an element substrate. 11 and a liquid crystal layer (electro-optic layer) 13 sandwiched between the opposing substrate 12. In the liquid crystal display device 1, the element substrate 11 and the counter substrate 12 are bonded together with a sealing material 14, and the liquid crystal layer 13 is sealed in a region partitioned by the sealing material 14. The liquid crystal display device 1 has a substantially rectangular image display region 15 provided in an inner region of the sealing material 14 in a plan view (when the element substrate 11 is viewed from the counter substrate 12 side).
Further, the liquid crystal display device 1 includes a data line driving circuit 16 and a scanning line driving circuit 17 provided in an outer region of the sealing material 14, a connection terminal 18 that is electrically connected to the data line driving circuit 16 and the scanning line driving circuit 17, and Wiring 19 for connecting the scanning line driving circuit 17 is provided.

In the image display area 15 of the liquid crystal display device 1, as shown in FIGS. 1 and 2, a plurality of sub-pixel areas 20 are arranged in a matrix.
As shown in FIG. 2, each of the plurality of sub-pixel regions 20 is provided with a pixel electrode 21 and a TFT (Thin Film Transistor) element (drive element) 22 for switching control of the pixel electrode 21. Yes. In the image display area 15, a plurality of data lines 23 and scanning lines 24 are arranged in a grid pattern.

  The TFT element 22 has a source connected to the data line 23, a gate connected to the scanning line 24, and a drain connected to the pixel electrode 21. The data line 23 is connected to the data line driving circuit 16 and is configured to supply the image signals S1, S2,..., Sn supplied from the data line driving circuit 16 to each sub-pixel region 20. . The scanning lines 24 are connected to the scanning line driving circuit 17 and are configured to supply the scanning signals G1, G2,..., Gm supplied from the scanning line driving circuit 17 to the sub-pixel regions 20. . Here, the data line driving circuit 16 may supply the image signals S1 to Sn line-sequentially in this order, or may supply each of the data lines 23 adjacent to each other for each group. Further, the scanning line driving circuit 17 supplies the scanning signals G1 to Gm in a pulse-sequential manner at a predetermined timing.

  In the liquid crystal display device 1, the TFT elements 22 serving as switching elements are turned on for a certain period by the input of scanning signals G1 to Gm, so that the image signals S1 to Sn supplied from the data line 23 are at a predetermined timing. The pixel electrode 21 is written. Then, image signals S1 to Sn of a predetermined level written to the liquid crystal through the pixel electrode 21 are held for a certain period between the pixel electrode 21 and a common electrode 75 (described later) arranged to face each other through the liquid crystal layer 13. The Here, in order to prevent the held image signals S1 to Sn from leaking, the storage capacitor 25 is provided so as to be connected in parallel with the liquid crystal capacitor formed between the pixel electrode 21 and the common electrode 75. Yes. The storage capacitor 25 is provided between the drain of the TFT element 22 and the capacitor line 26.

Next, a detailed configuration of the liquid crystal display device 1 will be described with reference to FIGS.
As shown in FIGS. 3 to 5, the liquid crystal display device 1 includes a polarizing plate 27 provided outside the element substrate 11 (on the side opposite to the liquid crystal layer 13) and a polarizing plate 28 provided outside the counter substrate 12. And an illumination device (not shown) that is provided outside the polarizing plate 27 and that emits illumination light from the outer surface side of the element substrate 11. The liquid crystal display device 1 is configured such that ambient light is incident from the outside of the counter substrate 12 (on the side opposite to the liquid crystal layer 13).

The element substrate 11 includes, for example, a substrate body 31 made of a light-transmitting material such as glass, quartz, and plastic, a base protective film 32 that is sequentially laminated on the inner surface (the liquid crystal layer 13 side) of the substrate body 31, and a gate. An insulating film 33, a first interlayer insulating film 34, a second interlayer insulating film 35, and an alignment film 36 are provided.
Further, the element substrate 11 is formed on the inner surface of the gate insulating film 33 and the semiconductor layer 41 and the capacitor electrode 42 disposed on the inner surface of the base protective film 32 in the sub-pixel region 20 as shown in FIG. Pixels disposed on the inner surface of the second interlayer insulating film 35, the scanning lines 24 and the capacitor lines 26 disposed, the data lines 23 and the connection electrodes 43 disposed on the inner surface of the first interlayer insulating film 34 An electrode 21 is provided.
The element substrate 11 includes a semiconductor layer 45 disposed on the inner surface of the base protective film 32 and an inner surface of the first interlayer insulating film 34 at the outer periphery of the image display region 15 as shown in FIG. And take-out electrodes 46 and 47.
Further, the element substrate 11 is formed outside the image display region 15 on the inner layers of the semiconductor layers 51 and 52 disposed on the inner surface of the base protective film 32 and the inner surface of the gate insulating film 33 as shown in FIG. The gate electrodes 53 and 54 are disposed, and source electrodes 55 and 56 and drain electrodes 57 and 58 are disposed on the inner surface of the first interlayer insulating film 34.

The base protective film 32 is made of a translucent silicon oxide such as SiO ₂ (silicon oxide) and covers the inner surface of the substrate body 31. The base protective film 32 is not limited to SiO ₂ but may be made of an insulating material such as SiOx (silicon oxide), SiN (silicon nitride), SiON (silicon oxynitride), or a ceramic thin film.
The gate insulating film 33 is made of a translucent material such as SiO _2, and is provided so as to cover the semiconductor layers 41, 45, 51, 52 and the capacitor electrode 42 formed on the base protective film 32. Yes.

As shown in FIGS. 3 to 5, the first interlayer insulating film 34 is made of a light-transmitting material such as SiO ₂ , and the gate insulating film 33 and the scanning line 24 formed on the gate insulating film 33. The capacitor line 26 and the gate electrodes 53 and 54 are provided.
The second interlayer insulating film 35 is made of a translucent material such as SiO ₂ , for example, and includes the first interlayer insulating film 34, the data line 23 formed on the first interlayer insulating film 34, the connection electrode 43, and the source. It is provided so as to cover the electrodes 55 and 56 and the drain electrodes 57 and 58.
The alignment film 36 is made of, for example, a resin material such as polyimide, and is provided so as to cover the second interlayer insulating film 35 and the pixel electrode 21 formed on the second interlayer insulating film 35. The surface of the alignment film 36 is subjected to an alignment process that regulates the initial alignment state of the liquid crystal molecules constituting the liquid crystal layer 13.

As shown in FIG. 3, the semiconductor layer 41 is partially formed in a region overlapping the data line 23 through the gate insulating film 33 in plan view, and is made of a semiconductor such as polysilicon. The semiconductor layer 41 is provided with a channel region 41a in a region overlapping with the scanning line 24 through the gate insulating film 33 in plan view.
In addition, since the TFT element 22 adopts an LDD (Lightly Doped Drain) structure in the semiconductor layer 41, a high concentration region having a relatively high impurity concentration and a relatively low concentration in the source region and the drain region. (LDD) regions are respectively formed. That is, in the semiconductor layer 41, a low concentration source region 41b and a high concentration source region 41c are formed in the source region, and a low concentration drain region 41d and a high concentration drain region 41e are formed in the drain region. The TFT element 22 is configured with the semiconductor layer 41 as a main component.
These low-concentration source region 41b, high-concentration source region 41c, low-concentration drain region 41d and high-concentration drain region 41e are formed by implanting impurity ions into polysilicon. The channel region 41a is formed by not implanting impurity ions into polysilicon.

  The capacitor electrode 42 is partially formed in a region overlapping the capacitor line 26 through the gate insulating film 33 in plan view, and is made of a semiconductor such as polysilicon like the semiconductor layer 41. The capacitor electrode 42 is formed continuously with the high concentration drain region 41 e of the semiconductor layer 41. The capacitor electrode 42 is formed by implanting impurity ions into polysilicon.

The scanning line 24 is arranged along the short axis direction of the rectangular sub-pixel region 20 in plan view, and is made of a metal material such as Al. Further, a region of the scanning line 24 that overlaps with the channel region 41a through the gate insulating film 33 in plan view functions as a gate electrode.
The capacitance line 26 is arranged along the minor axis direction of the sub-pixel region 20 in a plan view, and is made of a metal material such as Al as in the case of the scanning line 24. In addition, the capacitor line 26 constitutes the storage capacitor 25 with the capacitor electrode 42 disposed so as to face the gate insulating film 33 in a plan view.

The data line 23 is arranged along the major axis direction of the sub-pixel region 20 in plan view, and is made of a metal material such as Al, for example. The data line 23 is connected to the high concentration source region 41c of the semiconductor layer 41 through a contact hole H1 that penetrates the gate insulating film 33 and the first interlayer insulating film 34.
As described above, the scanning lines 24, the capacitor lines 26, and the data lines 23 are wired in a substantially lattice shape in plan view.
The connection electrode 43 is connected to the high-concentration drain region 41 e of the semiconductor layer 41 through a contact hole H 2 that penetrates the gate insulating film 33 and the first interlayer insulating film 34.

  The pixel electrode 21 has a substantially rectangular shape in plan view and is made of a light-transmitting conductive material such as ITO (indium tin oxide). Further, the pixel electrode 21 is connected to the connection electrode 43 through a contact hole H3 that penetrates the second interlayer insulating film 35. Thereby, the pixel electrode 21 is connected to the drain of the TFT element 22.

  As shown in FIG. 4, the semiconductor layer 45 is provided on three sides of the outer periphery of the substantially rectangular image display region 15 in plan view so as to be substantially U-shaped in plan view. Similarly to the semiconductor layer 41, the semiconductor layer 45 is made of a semiconductor such as polysilicon. The semiconductor layer 45 is provided with an intrinsic region 45a, a p-type region 45b, and an n-type region 45c that are sequentially arranged from the inside of the image display region 15. The intrinsic region 45a is formed by not implanting impurity ions. The p-type region 45b and the n-type region 45c are formed by implanting p-type and n-type impurity ions, respectively.

The extraction electrodes 46 and 47 are made of a metal material such as Al. The extraction electrode 46 is connected to the p-type region 45b of the semiconductor layer 45 through a contact hole H4 that penetrates the gate insulating film 33 and the first interlayer insulating film 34. Similarly, the extraction electrode 47 is connected to the n-type region 45c of the semiconductor layer 45 through the contact hole H5.
The light receiving element 48 is formed by the semiconductor layer 45 and the extraction electrodes 46 and 47. Here, the light receiving element 48 is configured to output the detected intensity information of the ambient light to the control unit of the illumination device. And an illuminating device adjusts the intensity | strength of illumination light based on this intensity | strength information.

As shown in FIG. 5, the semiconductor layers 51 and 52 are formed outside the image display area 15, respectively, and are made of a semiconductor such as polysilicon, like the semiconductor layers 41 and 45. In the semiconductor layer 51, a channel region 51a, a low concentration source region 51b, a high concentration source region 51c, a low concentration drain region 51d, and a high concentration drain region 51e are formed. In the semiconductor layer 52, a channel region 52a, a source region 52b, and a drain region 52c are formed.
The gate electrodes 53 and 54 are made of a metal material such as Al, for example. The gate electrode 53 overlaps the channel region 51a of the semiconductor layer 51 through the gate insulating film 33 in plan view. Similarly, the gate electrode 54 overlaps the channel region 52a of the semiconductor layer 52 through the gate insulating film 33 in plan view.

The source electrodes 55 and 56 and the drain electrodes 57 and 58 are made of a metal material such as Al. The source electrode 55 is connected to the high-concentration source region 51 c of the semiconductor layer 51 through a contact hole H 6 that penetrates the gate insulating film 33 and the first interlayer insulating film 34. Similarly, the source electrode 56 is connected to the source region 52b of the semiconductor layer 52 through the contact hole H7, and the drain electrode 57 is connected to the high concentration drain region 51e of the semiconductor layer 51 through the contact hole H8. The drain electrode 58 is connected to the drain region 52c of the semiconductor layer 52 through the contact hole H9.
The semiconductor layer 51, the gate electrode 53, the source electrode 55, and the drain electrode 57 constitute a TFT element 61 that constitutes the data line driving circuit 16. The semiconductor layer 52, the gate electrode 54, the source electrode 56, and the drain electrode 58 constitute a TFT element 62 that constitutes the data line driving circuit 16.

On the other hand, as shown in FIGS. 3 and 4, the counter substrate 12 includes a substrate body 71 made of a translucent material such as glass, quartz, and plastic, and an inner side (the liquid crystal layer 13 side) of the substrate body 71. A light shielding film 72, a color filter layer 73, a green filter layer 74, a common electrode 75, and an alignment film 76 are sequentially stacked on the surface.
The light shielding film 72 is formed in a region of the surface of the substrate body 71 that overlaps the edge of the sub pixel region 20 in plan view, and borders the sub pixel region 20.

The color filter layer 73 is arranged corresponding to each sub-pixel region 20, and is made of, for example, acrylic and contains a color material corresponding to the color displayed in each sub-pixel region 20.
As shown in FIG. 4, the green filter layer 74 is disposed corresponding to the outer peripheral portion of the image display region 15. The green filter layer 74 is formed integrally with the color filter layer 73 and is the same as the color material in the sub-pixel region that outputs the G color light in the sub-pixel region 20 of the color filter layer 73. It is formed using a color material. In addition, a part of the area between the image display area 15 and the sealing material 14 where the green filter layer 74 is not provided is provided with a peripheral parting (not shown).

As shown in FIGS. 3 and 4, the common electrode 75 is made of a light-transmitting conductive material such as ITO, like the pixel electrode 21. The common electrode 75 is provided so as to cover the light shielding film 72 and the substrate body 71.
Similar to the alignment film 76, the alignment film 76 is made of a resin material such as polyimide, and is provided so as to cover the common electrode 75. The surface of the alignment film 76 is subjected to an alignment process in which the alignment direction is antiparallel to the alignment direction of the alignment film 36.

The liquid crystal layer 13 is configured to operate in a TN (Twisted Nematic) mode using a liquid crystal having positive dielectric anisotropy.
The polarizing plates 27 and 28 are provided so that their transmission axes are substantially orthogonal to each other. Here, an optical compensation film (not shown) may be disposed on one or both of the inner sides of the polarizing plates 27 and 28. By disposing the optical compensation film, it is possible to compensate for the phase difference of the liquid crystal layer 13 when the liquid crystal display device 1 is perspective, and to reduce light leakage and increase the contrast. As the optical compensation film, a combination of a negative uniaxial medium and a positive uniaxial medium or a biaxial medium having a refractive index in each direction of nx>nz> ny is used.

[Manufacturing method of liquid crystal display device]
Next, a method for manufacturing the liquid crystal display device 1 having the above configuration will be described with reference to FIGS. Here, FIGS. 6 to 8 are process diagrams showing the manufacturing process of the element substrate 11.
First, the base protective film 32 is formed on the substrate body 31. Here, the base protective film 32 is formed using a CVD (Chemical Vapor Deposition) method, a sputtering method, or the like (FIG. 6A).

  Next, semiconductor layers 41, 45, 51, 52 are formed on the base protective film 32. Here, an amorphous semiconductor layer made of amorphous silicon is first deposited using a PECVD (plasma enhancement chemical vapor deposition (plasma CVD)) method or the like. Then, for example, an amorphous semiconductor layer is crystallized by irradiation with an excimer laser of XeCl (xenon chloride) or the like to form a polycrystalline semiconductor layer. Next, the semiconductor layers 41, 45, 51, and 52 are formed by patterning using a photolithography technique (FIG. 6B).

Subsequently, a gate insulating film 33 that covers the semiconductor layers 41, 42, 45, 51, 52 and the base protective film 32 is formed. Here, the gate insulating film 33 is formed using a CVD method or the like.
Next, low concentration impurity ions are implanted into the capacitor electrode 42. Here, a resist layer 81 </ b> A covering the semiconductor layer 41 is formed on the gate insulating film 33. In addition, a resist layer 81 </ b> B that covers the semiconductor layer 45 is formed on the gate insulating film 33. Then, a resist layer 81 </ b> C that covers the semiconductor layer 51 is formed on the gate insulating film 33. Further, a resist layer 81D that covers the semiconductor layer 52 is formed on the gate insulating film 33.
Then, low-concentration impurity ions (phosphorus ions) are implanted into the opening regions of the resist layers 81 </ b> A to 81 </ b> D with a dose amount of about 0.1 × 10 ¹³ / cm ² to about 10 × 10 ¹³ / cm ² . At this time, the resist layers 81A to 81D function as a mask. Thereafter, the resist layers 81A to 81D are removed. Thereby, the capacitive electrode 42 is formed (FIG. 6C).

Subsequently, high-concentration impurity ions are implanted into the semiconductor layers 41, 45, 51. Here, a resist layer 82A that covers the regions of the semiconductor layer 41 that will become the channel region 41a, the low concentration source region 41b, and the low concentration drain region 41d, and a resist layer 82B that covers the capacitor electrode 42 are formed on the gate insulating film 33. Form. In addition, a resist layer 82 </ b> C is formed on the gate insulating film 33 so as to cover the regions to be the intrinsic region 45 a and the n-type region 45 c in the semiconductor layer 45. Then, a resist layer 82D is formed on the gate insulating film 33 so as to cover the regions of the semiconductor layer 51 that become the channel region 51a, the low concentration source region 51b, and the low concentration drain region 51d. Further, a resist layer 82E that covers the entire surface of the semiconductor layer 52 is formed on the gate insulating film 33.
Then, high-concentration impurity ions (phosphorus ions) are implanted into the opening regions of the resist layers 82 </ b> A to 82 </ b> E at a dose of about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ² . At this time, the resist layers 82A to 82E function as a mask. Thereafter, the resist layers 82A to 82E are removed. Thereby, the high concentration source region 41c and the high concentration drain region 41e, the p-type region 45b, and the high concentration source region 51c and the high concentration drain region 51e are formed (FIG. 7A).

  Next, the scanning line 24, the capacitor line 26, and the gate electrodes 53 and 54 are formed on the gate insulating film 33. Here, a metal film constituting the scanning line 24 and the gate electrodes 53 and 54 is formed on the gate insulating film 33 by using a sputtering method or the like, and this metal film is patterned by using a photolithography technique or the like. Then, gate electrodes 53 and 54 are formed (FIG. 7B).

Subsequently, low concentration impurity ions are implanted into the semiconductor layers 41 and 51 and the capacitor electrode 42. Here, resist layers 83 </ b> A and 83 </ b> B covering the entire surface of the semiconductor layer 45 and the entire surface of the semiconductor layer 52 are formed on the gate insulating film 33.
Then, low-concentration impurity ions (phosphorus ions) are implanted into the opening regions of the resist layers 83A and 83B at a dose of about 0.1 × 10 ¹³ / cm ² to about 10 × 10 ¹³ / cm ² . At this time, the resist layers 83A and 83B, the scanning line 24, the capacitor line 26, and the gate electrode 53 function as a mask. Thereafter, the resist layers 83A and 83B are removed. Thereby, the low concentration source region 41b and the low concentration drain region 41d, and the low concentration source region 51b and the low concentration drain region 51d are formed (FIG. 7C).

Next, high-concentration impurity ions are implanted into the semiconductor layers 45 and 52. Here, a resist layer 84 </ b> A that covers the entire surface of the semiconductor layer 41 is formed on the gate insulating film 33. Further, a resist layer 84 </ b> B that covers the intrinsic region 45 a and the p-type region 45 b in the semiconductor layer 45 is formed on the gate insulating film 33. Then, a resist layer 84 </ b> C that covers the entire surface of the semiconductor layer 51 is formed on the gate insulating film 33.
Then, high-concentration impurity ions (boron ions) are implanted into the opening region at a dose of about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / cm ² . At this time, the resist layers 84A to 84C, the capacitor line 26, and the gate electrode 54 function as a mask. Thereafter, the resist layers 84A to 84C are removed. As a result, an n-type region 45c, and a source region 52b and a drain region 52c are formed (FIG. 8A).

Next, a first interlayer insulating film 34 that covers the scanning lines 24, the gate electrodes 53 and 54, and the gate insulating film 33 is formed. Here, the first interlayer insulating film 34 is formed using a CVD method or the like. Then, contact holes H1, H2, and H4 to H9 penetrating the first interlayer insulating film 34 and the gate insulating film 33 are formed.
Subsequently, the data line 23, the connection electrode 43, the extraction electrodes 46 and 47, the source electrodes 55 and 56, and the drain electrodes 57 and 58 are formed on the first interlayer insulating film 34. Here, a metal film constituting the data line 23, the connection electrode 43, the extraction electrodes 46 and 47, the source electrodes 55 and 56, and the drain electrodes 57 and 58 is formed on the first interlayer insulating film 34 using a sputtering method or the like. . Then, the metal film is patterned using a photolithography technique or the like to form the data line 23, the connection electrode 43, the extraction electrodes 46 and 47, the source electrodes 55 and 56, and the drain electrodes 57 and 58 (FIG. 8B). ).

  At this time, the data line 23 is connected to the high concentration source region 41c of the semiconductor layer 41 through the contact hole H1, and the connection electrode 43 is connected to the high concentration drain region 41e through the contact hole H2. The extraction electrode 46 is connected to the p-type region 45b of the semiconductor layer 45 through the contact hole H4, and the extraction electrode 47 is connected to the n-type region 45c through the contact hole H5. The source electrode 55 is connected to the high concentration source region 51c of the semiconductor layer 51 through the contact hole H6, and the drain electrode 58 is connected to the high concentration drain region 51e through the contact hole H7. Further, the source electrode 56 is connected to the source region 52b of the semiconductor layer 52 through the contact hole H8, and the drain electrode 58 is connected to the drain region 52c through the contact hole H9.

Next, the second interlayer insulating film 35 that covers the data line 23, the connection electrode 43, the extraction electrodes 46 and 47, the source electrodes 55 and 56, the drain electrodes 57 and 58, and the first interlayer insulating film 34 is formed. Here, the second interlayer insulating film 35 is formed using a CVD method or the like. Then, a contact hole H3 penetrating the second interlayer insulating film 35 is formed.
Then, the pixel electrode 21 is formed on the second interlayer insulating film 35. Here, an ITO film constituting the pixel electrode 21 is formed on the second interlayer insulating film 35, and the ITO film is patterned using a photolithography technique to form the pixel electrode 21. Here, the pixel electrode 21 is connected to the connection electrode 43 through the contact hole H3 penetrating the second interlayer insulating film 35 (FIG. 8C).

Thereafter, polyimide or the like is applied so as to cover the pixel electrode 21, and a rubbing process is performed on the surface to form an alignment film 36. The element substrate 11 is manufactured as described above (FIGS. 3 to 5).
Then, the element substrate 11 and the separately formed counter substrate 12 are bonded together with the sealing material 14 described above, and liquid crystal is injected and sealed, thereby forming the liquid crystal layer 13. At this time, the green filter layer 74 formed on the counter substrate 12 is bonded so as to overlap the light receiving element 48. Further, polarizing plates 27 and 28 are provided on the outer surfaces of the element substrate 11 and the counter substrate 12. As described above, the liquid crystal display device 1 as shown in FIGS. 1 to 5 is manufactured.

〔Electronics〕
The liquid crystal display device 1 having the above configuration is used as a display unit 101 of a cellular phone (electronic device) 100 as shown in FIG. The cellular phone 100 includes a display unit 101, a plurality of operation buttons 102, an earpiece 103, a mouthpiece 104, and a main body unit including the display unit 101.

As described above, according to the liquid crystal display device 1 and the manufacturing method thereof in the present embodiment, since the light receiving element 48 receives the ambient light transmitted through the green filter layer 74, the wavelength characteristic of the detection sensitivity of the light receiving element 48 is reduced. Can be close to the visual sensitivity. Thereby, luminance adjustment of illumination light can be performed more appropriately.
In addition, since the light receiving element 48 is formed in a region that does not contribute to image display between the outer peripheral portion of the image display region 15 and the sealing material 14, space can be effectively used.
Since the light receiving elements 48 are formed on the three sides of the outer periphery of the image display region 15, the light receiving area of the light receiving elements 48 is increased, and the accuracy of detection sensitivity of ambient light can be improved.
Furthermore, since the light receiving element 48 and the TFT element 22 are formed on the same layer and can be formed in the same process, the light receiving element 48 can be formed without increasing the number of manufacturing steps.
Moreover, since the color filter layer 73 and the green filter layer 74 are formed on the same layer, the green filter layer 74 can be formed without increasing the number of manufacturing steps.

In addition, this invention is not limited to the said embodiment, A various change can be added in the range which does not deviate from the meaning of this invention.
For example, the light receiving element has a configuration in which a p-type region, an intrinsic region, and an n-type region are sequentially arranged from the inside of the image display region, but may have other configurations such as a configuration in which a plurality of light receiving elements are connected in parallel. May be.
Further, although the light receiving elements are formed on the three sides of the outer peripheral portion of the image display area, it may be two or more sides or only one side. Here, the shape of the image display area is not limited to a substantially rectangular shape in plan view.
The light receiving element is formed in a region between the seal material and the image display region, but may be formed on the outer peripheral portion of the image display region, and may be formed outside the seal material.
Further, although the light receiving element and the TFT element arranged in the sub-pixel region are formed on the same layer, they may be formed on different layers.
Further, although a TFT element is used as a driving element, other driving elements such as a TFD (Thin Film Diode) may be used as long as the element controls switching of the pixel electrode.

In addition, the color filter layer is configured to display three colors of R, G, and B, but can be configured to display only one of the colors of R, G, and B, or other one color. It is good also as a structure which can perform color display of a color and four or more colors. Here, the color filter layer may be provided on the element substrate without providing the color filter layer on the counter substrate.
The green filter layer may be formed using a color material that is different from the color material that displays the G color of the color filter layer, or may be formed in a different process from the color filter layer. Here, similarly to the above, the color filter layer may be provided on the element substrate without providing the green color filter layer on the counter substrate as long as the light receiving element receives the environmental light transmitted through the green filter layer. .

In addition, the liquid crystal display device has an electrode structure in which a pixel electrode is provided on an element substrate and a common electrode is provided on a counter substrate. However, the pixel electrode and the common electrode are formed on the element substrate to form a substrate with respect to the liquid crystal layer. An electrode structure using a so-called lateral electric field method such as an IPS (In-Plane Switching) method or an FFS (Fringe-Field Switching) method for generating an electric field in the plane direction may be employed.
As the liquid crystal layer, a liquid crystal operating in the TN mode is used. However, the liquid crystal layer is not limited to the TN mode. Other liquid crystals such as (Optical Compensated Bend) mode may be used.
The liquid crystal display device is not limited to a transmissive configuration, and may be a transflective liquid crystal display device.

In addition, the electronic device provided with the liquid crystal display device is not limited to a mobile phone, but a PDA (Personal Digital Assistant), a personal computer, a notebook personal computer, a workstation, a digital still camera, an in-vehicle monitor, a car Navigation device, head-up display, digital video camera, television receiver, viewfinder type or monitor direct-view type video tape recorder, pager, electronic notebook, calculator, electronic book or projector, word processor, video phone, POS terminal, touch panel It may be another electronic device such as a device provided, a lighting device or the like.
The electro-optical device is not limited to a liquid crystal display device and may be any other device such as an organic EL (electroluminescence) device as long as it changes the optical characteristics of the electro-optical layer by generating an electric field by applying a voltage. An electro-optical device may be used.

(A) which shows the liquid crystal display device of one Embodiment is a top view, (b) is sectional drawing. FIG. 2 is an equivalent circuit diagram of FIG. 1. It is sectional drawing which shows a subpixel area | region. It is sectional drawing which shows the outer peripheral part of an image display area. It is sectional drawing which shows the element substrate in the exterior of an image display area. It is process drawing which shows the manufacturing process of an element substrate. Similarly, it is process drawing which shows the manufacturing process of an element substrate. Similarly, it is process drawing which shows the manufacturing process of an element substrate. It is a schematic perspective view which shows a mobile telephone provided with a liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device (electro-optical device), 11 Element substrate (one board | substrate), 12 Opposite substrate (the other board | substrate), 13 Liquid crystal layer (electro-optical layer), 14 Seal material, 15 Image display area, 20 Sub pixel area | region 22 TFT elements (drive elements), 48 light receiving elements, 73 color filter layers, 74 green filter layers

Claims (7)

An electro-optical device in which an electro-optical layer is sandwiched between a pair of substrates, and an image display region is provided in a formation region of the electro-optical layer,
The one substrate has a light receiving element having a PIN structure provided on at least a part of the outer peripheral portion of the image display area,
One of the pair of substrates has a green filter layer overlapping the light receiving element in plan view.   The electro-optical device according to claim 1, wherein the light receiving element and a driving element that drives the electro-optical layer are formed on the same layer. The image display area has a substantially rectangular shape in plan view;
The electro-optical device according to claim 1, wherein the light receiving element is formed on at least two sides of the outer peripheral portion. The electro-optic layer is a liquid crystal layer;
The electro-optical device according to any one of claims 1 to 3, wherein the pair of substrates are bonded together with a sealing material.   The electro-optical device according to claim 4, wherein the light receiving element is formed inside a region where the sealing material is formed. One of the pair of substrates has the green filter and a color filter layer provided corresponding to a color displayed in a pixel region constituting the image display region,
6. The electro-optical device according to claim 4, wherein the green filter layer and the color filter layer are formed on the same layer. An electro-optical device manufacturing method in which an electro-optical layer is sandwiched between a pair of substrates, and an image display region is provided in a formation region of the electro-optical layer,
Forming a driving element for driving the electro-optic layer on the one substrate, and forming a light receiving element having a PIN structure on at least a part of the outer periphery of the image display region;
Forming a green filter layer overlapping with the light receiving element in a plan view on any of the pair of substrates,
A method of manufacturing an electro-optical device, wherein the driving element and the light receiving element are formed on the same layer.

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