JP2008147622A - モジュール型センサアセンブリ及びその製作方法 - Google Patents
モジュール型センサアセンブリ及びその製作方法 Download PDFInfo
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- JP2008147622A JP2008147622A JP2007261451A JP2007261451A JP2008147622A JP 2008147622 A JP2008147622 A JP 2008147622A JP 2007261451 A JP2007261451 A JP 2007261451A JP 2007261451 A JP2007261451 A JP 2007261451A JP 2008147622 A JP2008147622 A JP 2008147622A
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Abstract
【解決手段】モジュール型センサアセンブリ(10)並びにモジュール型センサアセンブリ(10)の製作方法(70)を提供する。モジュール型センサアセンブリ(10)は、電子素子アレイ(14)とスタック式構成で結合させたセンサアレイ(12)を含む。センサアレイ(12)は、その各々が複数のセンササブアレイ(18)を備えた複数のセンサモジュール(22)を備える。電子素子アレイ(14)は、その各々が複数の集積回路チップ(20)を備えた複数の集積回路モジュール(24)を備える。センサモジュール(22)は、フリップチップテクノロジーを介して電子素子モジュール(24)と結合させることがある。
【選択図】図3
Description
12 センサアレイ
14 電子素子アレイ
16 相互接続
17 インタフェース
18 センササブアレイ
20 ICチップ
22 センサモジュール
24 電子素子/I/Cモジュール
26 I/Oパッド領域
28 ウェハ
30 良好なダイ
32 不良のダイ
34 電気的に良好なモジュール
36 導電性バンプ
38 導電性パッド
39 導電性パッド
40 導電性パッド
42 アンダーフィル材料
44 フレックスケーブル
46 導電性バンプ
48 サブストレート
50 結合ワイヤ
52 ワイヤ結合パッド
54 ワイヤ結合パッド
56 結合ワイヤパッド
58 センサ
60 ウェハ
62 ウェハ貫通ビア
64 再分布層
66 パッド
68 導電経路
70 処理法
72 処理工程
74 処理工程
76 処理工程
78 処理工程
80 処理工程
82 処理工程
84 処理工程
86 処理工程
Claims (10)
- その各々が複数のセンササブアレイ(18)を備える複数のセンサモジュール(22)を備えたセンサアレイ(12)と、
前記センサアレイ(12)と結合されると共に、その各々が複数の集積回路チップ(20)を備える複数の集積回路モジュール(24)を備えた電子素子アレイ(14)と、
を備えるセンサアセンブリ(10)。 - 相互接続(16)は、フリップチップバンプ結合、原子結合、低温融合結合、張り合わせ式金製バンプまたはインジウム製バンプ、銅圧縮結合、異方性導電フィルム、あるいはこれらの組み合わせのうちの1つを備える、請求項2に記載のセンサアセンブリ(10)。
- 前記センササブアレイ(18)の各々は、容量性マイクロマシン加工超音波トランスジューサ(cMUT)、テルル化亜鉛カドミウム(CZT)センサ、圧電トランスジューサ(PZT)、圧電マイクロマシン加工超音波トランスジューサ(PMUT)、フォトセンサアレイのうちの1つを備える、請求項1に記載のセンサアセンブリ(10)。
- 前記複数の集積回路チップ(20)の各々は、該集積回路チップ(20)の単一のエッジに沿って配列されると共に該集積回路チップ(20)をセンサシステムに結合するように構成させた入力/出力パッド領域(26)を備える、請求項1に記載のセンサアセンブリ(10)。
- 前記複数の集積回路チップ(20)の各々は、該集積回路チップ(20)の複数のエッジに沿って配列されると共に該集積回路チップ(20)を超音波システムに結合するように構成させた入力/出力パッド領域(26)を備える、請求項1に記載のセンサアセンブリ(10)。
- 前記センサアレイ(12)は前記電子素子アレイ(14)の上に重ね合わされている、請求項1に記載のセンサアセンブリ(10)。
- 前記センサアレイ(12)を前記電子素子アレイ(14)に結合するように構成させた相互接続(16)をさらに備えており、該相互接続(16)は該センサアレイ(12)を該電子素子アレイ(14)に機械的に結合すると共に該センサアレイ(12)と該電子素子アレイ(14)の間で電気信号を送信するように構成させた複数の導電性バンプ(36)を備えている、請求項1に記載のセンサアセンブリ(10)。
- センサアセンブリ(10)の製作方法であって、
その各々が複数のセンササブアレイ(18)を備える複数のセンサモジュール(22)を提供する工程と、
その各々が複数の集積回路チップ(20)を備える複数の電子素子モジュール(24)を提供する工程と、
前記複数のセンサモジュール(22)の各々を複数の集積回路モジュール(24)のうちの対応するモジュールにスタック配列で結合させる工程と、
を含む方法。 - 複数のセンサモジュール(22)を提供する前記工程は、
前記複数のセンササブアレイ(18)の各々をウェハ(28)上に製作する工程と、
前記複数のセンササブアレイ(18)の各々を電気的にテストする工程と、
前記ウェハ(28)上で電気的に良好なセンササブアレイ(34)を特定する工程と、
電気的に良好なセンササブアレイ(34)の前記特定の後に、前記ウェハ(28)をスクライビングし、単一の横列に配列されたM個のセンササブアレイ(18)をその各々が備える複数のセンサモジュール(22)を生成する工程であって、スクライビングパターンが該センサモジュール(22)の数を最大化するように選択されており、該センサモジュール(22)内のあらゆるセンササブアレイ(34)が電気的に良好なセンササブアレイ(34)であるような生成工程と、
を含む請求項8に記載の方法。 - 複数の電子素子モジュール(24)を提供する前記工程は、
前記複数の集積回路チップ(20)の各々をウェハ上に製作する工程と、
前記複数の集積回路チップ(20)の各々を電気的にテストする工程と、
前記ウェハ上で電気的に良好な集積回路チップ(20)を特定する工程と、
電気的に良好な集積回路チップ(20)の前記特定の後に、前記ウェハをスクライビングし、単一の横列に配列されたN個の集積回路チップ(20)をその各々が備える複数の電子素子モジュール(24)を生成する工程であって、スクライビングパターンが該電子素子モジュール(24)の数を最大化するように選択されており、該電子素子モジュール(24)内のあらゆる集積回路チップ(20)が電気的に良好な集積回路チップであるような生成工程と、
を含む請求項8に記載の方法。
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