JP2008147446A - Ceramic circuit board and its manufacturing method - Google Patents

Ceramic circuit board and its manufacturing method Download PDF

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JP2008147446A
JP2008147446A JP2006333383A JP2006333383A JP2008147446A JP 2008147446 A JP2008147446 A JP 2008147446A JP 2006333383 A JP2006333383 A JP 2006333383A JP 2006333383 A JP2006333383 A JP 2006333383A JP 2008147446 A JP2008147446 A JP 2008147446A
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circuit board
ceramic substrate
ceramic
gap
brazing material
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JP4930833B2 (en
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Taku Fujita
卓 藤田
Junichi Watanabe
渡辺　　純一
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Proterial Ltd
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Hitachi Metals Ltd
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/16—Acidic compositions
    • C23F1/18—Acidic compositions for etching copper or alloys thereof
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/16—Acidic compositions
    • C23F1/30—Acidic compositions for etching other metallic material

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ceramic circuit board that has excellent electric insulation properties even after being applied with cleaning for removing a reaction product and cleaning for removing a brazing filler metal, and to provide its manufacturing method. <P>SOLUTION: The method has a bonding step of obtaining a joint body by bonding a metal circuit board to a ceramic substrate via a brazing-filler-metal layer, a pattern forming step, in which a gap is formed as a circuit pattern by immersing the joint body into an etching solution so as to remove unwanted parts of the metal circuit board, a first removal step, in which the brazing-filler-metal layer is exposed by removing a reaction product, covering the brazing-filler-metal layer protruding into the gap, while immersing the joint body formed with the circuit pattern into a neutral cleaning liquid, and a second removal step for removing the exposed brazing-filler-metal layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は高信頼性および高放熱性を要するパワーモジュール等に使用されるセラミックス回路基板に関する。   The present invention relates to a ceramic circuit board used for a power module or the like that requires high reliability and high heat dissipation.

近年、高周波トランジスタ、パワーＩＣ等の発熱量の大きい半導体素子の発展に伴い、良好な熱伝導を有するセラミックス基板に銅やアルミニウム等の金属板を接合した、セラミックス回路基板の需要が増加している。また、上記のセラミックス回路基板を使用するインバータは小型化の一途を辿っており、よってセラミックス回路基板の小型化も要求されている。その結果、回路パターン間をより狭くすることにより微細パターン化する必要がある。   In recent years, with the development of high-temperature semiconductor elements such as high-frequency transistors and power ICs, there is an increasing demand for ceramic circuit boards in which a metal plate such as copper or aluminum is bonded to a ceramic board having good heat conduction. . In addition, inverters using the above-described ceramic circuit board are being miniaturized, and accordingly, downsizing of the ceramic circuit board is also required. As a result, it is necessary to make a fine pattern by narrowing the space between circuit patterns.

しかし、微細パターン化することによりセラミックス基板と金属板の接合に用いるろう材やエッチング後の導体残留物の一部が基板上のギャップに存在し、隣り合う回路パターン間の絶縁性が低下したり、ショートするという問題が発生した。   However, by forming a fine pattern, a part of the brazing material used for joining the ceramic substrate and the metal plate and the conductor residue after the etching exists in the gap on the substrate, and the insulation between adjacent circuit patterns decreases. The problem of short-circuiting occurred.

この問題を解決するために、エッチング処理後にろう材除去工程を行われている。ろう材除去には特許文献１などで報告されているサンドブラスト法や、特許文献２などで報告されているフッ化アンモニウム溶液を用いた方法などが行われている。しかし、サンドブラストによるろう材除去では、物理的衝撃によるセラミックス基板のクラック発生が懸念される。一方、フッ化アンモニウム溶液を用いたろう材除去では、基板へのダメージは少ないが、フッ化アンモニウム溶液は銅板も溶かすため、長時間基板を浸漬させた場合、溶液が著しく劣化し交換頻度が高くなるためコストがかかってしまう。また、銅板の溶出によりエッチング後の回路パターン寸法が更に小さくなり、目標回路パターン寸法と製品の回路パターン寸法が異なってしまう可能性などが考えられる。
特開２００２−１７１０２９号公報 特開平９−１８１４２３号公報 In order to solve this problem, a brazing material removing step is performed after the etching process. For removing the brazing filler metal, a sand blast method reported in Patent Document 1 or the like, a method using an ammonium fluoride solution reported in Patent Document 2 or the like is performed. However, when removing the brazing filler metal by sand blasting, there is a concern that the ceramic substrate may be cracked by physical impact. On the other hand, the brazing material removal using the ammonium fluoride solution causes little damage to the substrate, but the ammonium fluoride solution also dissolves the copper plate. Therefore, when the substrate is immersed for a long time, the solution deteriorates significantly and the replacement frequency increases. Therefore, it costs. In addition, there is a possibility that the circuit pattern dimension after etching is further reduced due to elution of the copper plate, and the target circuit pattern dimension and the circuit pattern dimension of the product are different.
JP 2002-171029 A JP-A-9-181423

そのため、フッ化アンモニウム溶液を用いたろう材除去を施す前に、ろう材除去を阻害するエッチング処理後の導体残留物やろう材とエッチング溶液の反応物を、酸洗浄によって取り除くことで、ろう材除去時間の短縮化が行われている。   Therefore, before removing the brazing filler metal using the ammonium fluoride solution, removal of the brazing filler metal by removing the conductive residue after the etching treatment, which hinders the removal of the brazing filler metal, and the reaction product of the brazing filler metal and the etching solution by acid cleaning. Time has been shortened.

しかし、酸洗浄溶液はセラミックス基板表面から粒界相中のガラス相（例えばＳｉＯ２など）を溶出させる。その結果、溶出部分は空隙となった変質層がセラミックス基板表面に形成され、セラミックス基板の特長である電気絶縁性を低下させてしまうといった問題があった。変質した部分の絶縁抵抗は小さいため実質的に変質層の厚さ分だけセラミックス基板は薄くなり、とりわけセラミックス基板の厚み方向の絶縁性能を大幅に低下させてしまう。 However, the acid cleaning solution elutes the glass phase (for example, SiO 2 ) in the grain boundary phase from the ceramic substrate surface. As a result, there has been a problem that a deteriorated layer having voids formed in the elution portion is formed on the surface of the ceramic substrate, and the electrical insulation characteristic of the ceramic substrate is lowered. Since the insulation resistance of the altered portion is small, the ceramic substrate becomes substantially thinner by the thickness of the altered layer, and in particular, the insulation performance in the thickness direction of the ceramic substrate is significantly reduced.

本発明は前記問題点を解決するためになされたものであり、反応物を除去する洗浄およびろう材を除去する洗浄を施した後においても、優れた電気絶縁性を有するセラミックス回路基板を提供することを目的とする。   The present invention has been made to solve the above-described problems, and provides a ceramic circuit board having excellent electrical insulation even after cleaning for removing reactants and cleaning for removing brazing material. For the purpose.

本発明者らは前記目的を達成するため、ろう材除去処理前の酸洗浄工程を見直した。そして、酸溶液の代わりに中性洗剤を加えた水溶液を用いた洗浄は、酸洗浄と同等の洗浄能力を有し、かつ酸洗浄のようなガラス相の溶出が起こらないという第一の知見を得た。本知見にたどり着くため、本発明者らはエッチング工程後に生成する反応生成物の性状解析を行った。その結果、反応生成物は銀もしくは銅の化合物、たとえば酸化銀や塩化銅などから成り、これらを化学的に除去するためには硫酸や塩酸などの酸性の薬液を用いた溶解が必要である。しかし、反応生成物の形態は塵状の集合体のような形状であり、反応生成物下部にあるろう材層との密着力は小さいことがわかった。そこで中性洗剤水溶液を用いた物理的な洗浄でも反応生成物を充分に除去できるという結論に至った。更に、酸洗浄に用いる酸溶液の濃度および処理時間を最適化することで、ガラス相の溶出量を減少させることができる、という第二の知見を得た。   In order to achieve the above object, the present inventors reviewed the acid cleaning step before the brazing material removal treatment. The first finding is that cleaning using an aqueous solution in which a neutral detergent is added instead of an acid solution has a cleaning ability equivalent to that of acid cleaning, and the glass phase does not elute like acid cleaning. Obtained. In order to arrive at this knowledge, the present inventors conducted the property analysis of the reaction product produced | generated after an etching process. As a result, the reaction product is composed of a silver or copper compound, such as silver oxide or copper chloride, and in order to chemically remove them, dissolution using an acidic chemical such as sulfuric acid or hydrochloric acid is required. However, it was found that the form of the reaction product was like a dusty aggregate, and the adhesion with the brazing material layer below the reaction product was small. Therefore, it was concluded that the reaction product can be sufficiently removed even by physical washing using a neutral detergent aqueous solution. Furthermore, the second finding was obtained that the elution amount of the glass phase can be reduced by optimizing the concentration and treatment time of the acid solution used for the acid cleaning.

本発明者らは、前記知見に基づいて本発明に至ったものである。すなわち本願第一の発明は、セラミックス基板にろう材層を介して金属回路板を接合して接合体を得る接合工程と、前記接合体をエッチング溶液に浸漬して金属回路板の不要部分を除去してギャップを形成し回路パターンとするパターン形成工程と、回路パターンを形成した接合体を中性洗浄液に浸漬してギャップにはみ出たろう材層を覆う反応性生物を除去してろう材層を露出させる第一除去工程と、露出した前記ろう材層を除去する第二除去工程とを有することを特徴とするセラミックス回路基板の製造方法である。   The present inventors have arrived at the present invention based on the above findings. That is, the first invention of the present application is a joining step of joining a metal circuit board to a ceramic substrate through a brazing material layer to obtain a joined body, and removing the unnecessary portion of the metal circuit board by immersing the joined body in an etching solution. Then, the pattern forming process to form a gap and form a circuit pattern, and the joined body on which the circuit pattern is formed are immersed in a neutral cleaning solution to remove the reactive organisms covering the brazing filler metal layer protruding into the gap and expose the brazing filler metal layer. And a second removal step of removing the exposed brazing material layer. A method of manufacturing a ceramic circuit board.

本願第二の発明によるセラミックス基板は、セラミックス基板と、前記セラミックス基板にろう材層を介して接合された金属回路板とを有するセラミックス回路基板であって、前記金属回路板はギャップによって分割されており、前記セラミックス基板の厚みｔと前記ギャップに形成される前記セラミックス基板の表面変質層の最大厚みＡとの比Ａ／ｔが０．０８以下であり、前記セラミックス基板厚みが０．１５ｍｍ以下であり、その絶縁耐圧がＡＣ３ｋＶ以上であることを特徴とする。   A ceramic substrate according to a second invention of the present application is a ceramic circuit substrate having a ceramic substrate and a metal circuit board joined to the ceramic substrate via a brazing material layer, the metal circuit board being divided by a gap. And the ratio A / t between the thickness t of the ceramic substrate and the maximum thickness A of the surface-modified layer of the ceramic substrate formed in the gap is 0.08 or less, and the ceramic substrate thickness is 0.15 mm or less. The dielectric strength is AC 3 kV or more.

本願第三の発明によるセラミックス基板は、セラミックス基板と、前記セラミックス基板にろう材層を介して接合された金属回路板とを有するセラミックス回路基板であって、前記金属回路板はギャップによって分割されており、前記セラミックス基板の厚みｔと前記ギャップに形成される前記セラミックス基板の表面変質層の最大厚みＡとの比Ａ／ｔが０．０８以下であり、前記セラミックス基板厚みが０．２ｍｍ以下であり、その絶縁耐圧がＡＣ５ｋＶ以上であることを特徴とする。   A ceramic substrate according to a third invention of the present application is a ceramic circuit substrate having a ceramic substrate and a metal circuit board bonded to the ceramic substrate via a brazing material layer, the metal circuit board being divided by a gap. And the ratio A / t between the thickness t of the ceramic substrate and the maximum thickness A of the surface-modified layer of the ceramic substrate formed in the gap is 0.08 or less, and the ceramic substrate thickness is 0.2 mm or less. The dielectric strength is AC 5 kV or more.

本願第四の発明によるセラミックス基板は、セラミックス基板と、前記セラミックス基板にろう材層を介して接合された金属回路板とを有するセラミックス回路基板であって、前記金属回路板はギャップによって分割されており、前記セラミックス基板の厚みｔと前記ギャップに形成される前記セラミックス基板の表面変質層の最大厚みＡとの比Ａ／ｔが０．０５以下であり、前記セラミックス基板厚みが０．３５ｍｍ以下であり、その絶縁耐圧がＡＣ７ｋＶ以上であることを特徴とする。   A ceramic substrate according to a fourth invention of the present application is a ceramic circuit substrate having a ceramic substrate and a metal circuit board joined to the ceramic substrate via a brazing material layer, the metal circuit board being divided by a gap. And the ratio A / t between the thickness t of the ceramic substrate and the maximum thickness A of the surface-modified layer of the ceramic substrate formed in the gap is 0.05 or less, and the ceramic substrate thickness is 0.35 mm or less. The dielectric strength is AC 7 kV or more.

表面変質層とは、セラミックス基板が酸洗浄溶液等に曝された際にセラミックス基板中のガラス相が溶出することによりできるセラミックス基板の表面層である。この表面層はガラス相が溶出した後にできる空隙を有しており実質的に電気絶縁性に寄与しない。その結果、表面変質層を有するセラミックス基板は電気絶縁に寄与する実質的な厚さが減少したことになり絶縁耐圧が著しく低下する。本発明ではセラミックス回路基板の製造過程で化学的又は物理的影響を受けたことにより実質的に電気絶縁性に寄与しなくなった表面層をセラミックス基板の表面変質層と定義する。前記ギャップに露出しているセラミックス基板の表面変質層の最大厚さの測定方法として、ギャップに露出しているセラミックス基板の断面を１視野以上観察する。この時、分析能の観点から走査型電子顕微鏡を使用することが好ましい。なお、最大厚さに着目するのは、セラミックス基板の絶縁耐圧が当該基板の最小厚さ、即ち表面変質層の最大厚さに依存する傾向があるためである。   The surface-affected layer is a surface layer of the ceramic substrate that is formed by elution of the glass phase in the ceramic substrate when the ceramic substrate is exposed to an acid cleaning solution or the like. This surface layer has voids formed after the glass phase is eluted and does not substantially contribute to electrical insulation. As a result, the ceramic substrate having the surface-modified layer has a substantial thickness that contributes to electric insulation, and the withstand voltage is remarkably lowered. In the present invention, a surface layer that does not substantially contribute to electrical insulation due to a chemical or physical influence during the manufacturing process of the ceramic circuit board is defined as a surface-modified layer of the ceramic substrate. As a method of measuring the maximum thickness of the surface altered layer of the ceramic substrate exposed in the gap, one or more views of the cross section of the ceramic substrate exposed in the gap are observed. At this time, it is preferable to use a scanning electron microscope from the viewpoint of analytical ability. The reason for paying attention to the maximum thickness is that the dielectric strength of the ceramic substrate tends to depend on the minimum thickness of the substrate, that is, the maximum thickness of the surface-modified layer.

また、絶縁耐圧は、信頼性の観点より同一手順を用いて製造した２０枚以上のセラミックス回路基板を用いて、絶縁破壊電圧を測定し、その結果のワイブルプロットより求めた破壊確率１０ｐｐｍにおける絶縁破壊電圧の値と定義する。   In addition, the dielectric breakdown voltage is measured with a breakdown probability of 10 ppm obtained from a Weibull plot obtained by measuring a dielectric breakdown voltage using 20 or more ceramic circuit boards manufactured using the same procedure from the viewpoint of reliability. It is defined as the voltage value.

本発明によれば、ろう材除去を施した後においても、優れた電気絶縁性を有するセラミックス回路基板を提供することができる。   According to the present invention, it is possible to provide a ceramic circuit board having excellent electrical insulation even after brazing material removal.

本発明に関わるセラミックス回路基板は、例えば図1に示す手順で製造される。   The ceramic circuit board according to the present invention is manufactured, for example, according to the procedure shown in FIG.

接合工程（Ｓ１）
まずセラミックス基板と金属板を用意して、活性金属ろう材をスクリーン印刷法にてセラミックス基板の表面にパターン印刷する。この時、活性金属ろう材の塗布高さは、セラミックス基板と金属板との熱膨張差をより緩和させるために２０〜５０μｍ程度であることが好ましい。次に活性金属ろう材を塗布したセラミックス基板に銅板を加圧密着させ、真空中やアルゴン雰囲気のような不活性雰囲気中にて、前記活性金属ろう材の溶融温度以上で接合処理を行いセラミックス基板と金属板が一体となった接合体を得る。 Joining process (S1)
First, a ceramic substrate and a metal plate are prepared, and an active metal brazing material is pattern printed on the surface of the ceramic substrate by a screen printing method. At this time, the application height of the active metal brazing material is preferably about 20 to 50 μm in order to further relax the difference in thermal expansion between the ceramic substrate and the metal plate. Next, a copper plate is pressed and adhered to the ceramic substrate coated with the active metal brazing material, and the ceramic substrate is subjected to a bonding treatment at a temperature higher than the melting temperature of the active metal brazing material in a vacuum or an inert atmosphere such as an argon atmosphere. And a joined body in which the metal plates are integrated.

パターン形成工程（Ｓ２）
その後、前記接合体にエッチング処理にてパターン外の不要な金属板の除去を行う。この際にエッチング処理後の導体残留物やろう材とエッチング溶液とが反応して生成する反応生成物がろう材層を覆うように残留する。この反応生成物はろう材除去液では除去が困難であるばかりか、ろう材除去液と回路パターンからはみ出たろう材との接触の妨げとなる。よって、回路パターンからはみ出たろう材を除去する前に、この反応生成物は除去されなければならない。 Pattern formation process (S2)
Thereafter, unnecessary metal plates outside the pattern are removed from the joined body by etching. At this time, the conductor residue after the etching treatment or the reaction product produced by the reaction between the brazing material and the etching solution remains so as to cover the brazing material layer. This reaction product is not only difficult to remove with the brazing material removal solution, but also hinders contact between the brazing material removal solution and the brazing material protruding from the circuit pattern. Therefore, this reaction product must be removed before the brazing material protruding from the circuit pattern is removed.

第一除去工程（Ｓ３）
次に前記の反応生成物を除去するため、回路パターン形成後の接合体に酸洗浄もしくは中性洗剤溶液中にて超音波洗浄を施す。反応生成物は除去されその下から回路パターンからはみ出たろう材が露出する。中性洗浄溶液中ではセラミックス基板からガラス相が溶出することは殆どない。 First removal step (S3)
Next, in order to remove the reaction product, the bonded body after the circuit pattern is formed is subjected to an acid cleaning or an ultrasonic cleaning in a neutral detergent solution. The reaction product is removed, and the brazing material protruding from the circuit pattern from below is exposed. In the neutral cleaning solution, the glass phase is hardly eluted from the ceramic substrate.

第二除去工程（Ｓ４）
その後、前記反応生成物を除去した接合体をフッ化アンモニウム溶液に浸漬してろう材除去処理を行う。フッ化アンモニウム溶液中では金属回路板およびセラミックス基板のガラス相が溶出するが、前工程で既に反応生成物が除去されているため、短い浸漬時間でろう材除去は完了し、金属回路板寸法の縮小およびガラス相の溶出を抑制することができる。 Second removal step (S4)
Thereafter, the joined body from which the reaction product has been removed is immersed in an ammonium fluoride solution to perform a brazing material removal treatment. In the ammonium fluoride solution, the glass phase of the metal circuit board and ceramic substrate elutes. However, since the reaction product has already been removed in the previous process, the removal of the brazing filler metal is completed in a short immersion time. Reduction and elution of the glass phase can be suppressed.

研磨工程（Ｓ５）、めっき工程（Ｓ６）
さらに化学研磨処理を行い、最後に防錆処理やめっきを施すことで所定の金属回路パターンを有するセラミックス回路基板が製造される。 Polishing process (S5), plating process (S6)
Further, a ceramic polishing substrate having a predetermined metal circuit pattern is manufactured by performing a chemical polishing treatment and finally applying a rust prevention treatment or plating.

以下、本発明を実施例と比較例をあげて図２を参照しながら具体的に説明する。   Hereinafter, the present invention will be specifically described with reference to FIG.

Ａｇ、Ｃｕを主原料とする活性金属ろう材５，６をスクリーン印刷法を用いて□５０ｍｍ×厚み１５０μｍ，２００μｍ，３２０μｍに加工した窒化珪素焼結体２の両面に塗布する。ろう材塗布済み基板を乾燥後、回路パターン側および放熱パターン側にそれぞれ０．３ｍｍの銅板３，４を接触配置させ、真空中加圧下にて７５０〜８５０℃で２０分熱処理して窒化珪素基板と銅板の接合体１を製造した（図２）。   The active metal brazing materials 5 and 6 containing Ag and Cu as main raw materials are applied to both sides of the silicon nitride sintered body 2 processed into □ 50 mm × thickness 150 μm, 200 μm, and 320 μm using a screen printing method. After drying the brazing material coated substrate, 0.3 mm copper plates 3 and 4 are placed in contact with the circuit pattern side and the heat radiation pattern side, respectively, and heat-treated at 750 to 850 ° C. for 20 minutes under vacuum and silicon nitride substrate And the joined body 1 of the copper plate was manufactured (FIG. 2).

次いで、この接合体の銅板上に紫外線硬化タイプのエッチングレジストを塗布し、エッチングレジストパターンを形成した後、塩化第２鉄溶液にてパターン外の不要な銅板の除去を行い銅板３にギャップ９を形成し回路パターンを形成した。その後前記レジストを除去した。ギャップ９では窒化珪素焼結体２の表面にろう材層７がはみ出し、それを覆うように反応生成物８が残留する（図３）。反応生成物８を除去するため、アルキルエーテル硫酸エステルナトリウムを含む中性洗剤が３０ｗｔ％入った２５℃の水溶液中にエッチング後の窒化珪素回路基板を投入し、およそ２０分間、６００Ｗ、３５ｋＨｚの超音波洗浄を行ってろう材７を露出させた後（図４）、４０℃の市販フッ化アンモニウム溶液に浸漬してろう材７が銅回路パターン間（ギャップ９）から無くなるまでろう材除去を施した。その後化学研磨およびニッケルめっきを施した。このようにして表１および表２および表３の実施例１および実施例２および実施例４に示す窒化珪素回路基板を完成させた。   Next, an ultraviolet curable etching resist is applied on the copper plate of the joined body, and an etching resist pattern is formed. Then, an unnecessary copper plate outside the pattern is removed with a ferric chloride solution, and a gap 9 is formed in the copper plate 3. Forming a circuit pattern. Thereafter, the resist was removed. In the gap 9, the brazing filler metal layer 7 protrudes from the surface of the silicon nitride sintered body 2, and the reaction product 8 remains so as to cover it (FIG. 3). In order to remove the reaction product 8, the etched silicon nitride circuit board was put into an aqueous solution at 25 ° C. containing 30 wt% of a neutral detergent containing alkyl ether sulfate sodium salt, and approximately 20 minutes, 600 W, over 35 kHz. After the brazing material 7 is exposed by sonic cleaning (FIG. 4), the brazing material is removed by immersion in a commercially available ammonium fluoride solution at 40 ° C. until the brazing material 7 disappears between the copper circuit patterns (gap 9). did. Thereafter, chemical polishing and nickel plating were performed. Thus, the silicon nitride circuit boards shown in Example 1, Example 2 and Example 4 of Table 1, Table 2 and Table 3 were completed.

また、中性洗剤溶液の超音波洗浄を用いずに、酸洗浄として２０％硫酸溶液に１５分浸漬し、エッチング処理後の導体残留物やろう材とエッチング溶液の黒色反応物を除去した窒化珪素回路基板を比較例１および実施例３および実施例５とした。以上の工程のうち、酸洗浄処理、ろう材除去処理および化学研磨処理を施すことによりセラミックス基板２からガラス相が溶出して表面変質層２ａが形成される（図５）。   Further, without using ultrasonic cleaning of the neutral detergent solution, the silicon nitride is immersed in a 20% sulfuric acid solution for 15 minutes as an acid cleaning to remove the conductive residue and the brazing material after etching and the black reaction product of the etching solution. The circuit board was set as Comparative Example 1, Example 3, and Example 5. Of the above steps, by performing an acid cleaning process, a brazing material removal process, and a chemical polishing process, the glass phase is eluted from the ceramic substrate 2 to form a surface altered layer 2a (FIG. 5).

また、前記酸洗浄の処理時間を６０分に変更した窒化珪素回路基板を比較例２〜４とした。なお、酸洗浄時間を１０分に変更した接合体では、反応生成物８がろう材７の上に残留していた。   Moreover, the silicon nitride circuit board which changed the processing time of the said acid cleaning to 60 minutes was made into Comparative Examples 2-4. In the joined body in which the acid cleaning time was changed to 10 minutes, the reaction product 8 remained on the brazing material 7.

実施例１〜５および比較例１〜４の回路パターン間のセラミックス基板の断面を、ＳＥＭを用いて観察し、表面変質層の最大厚みを測定した。その結果を表１〜３に合わせて示す。   The cross section of the ceramic substrate between the circuit patterns of Examples 1 to 5 and Comparative Examples 1 to 4 was observed using an SEM, and the maximum thickness of the surface-modified layer was measured. The result is shown according to Tables 1-3.

これら一連の処理にて製造された回路基板について、絶縁耐圧試験を実施した。表１〜３に示す各条件で作成した窒化珪素回路基板各２０枚を用いて、シリコンオイル中にて回路基板の放熱面側銅板と回路面側銅板間に周波数５０Hｚの交流電圧を徐々に加え、絶縁が保てなくなった時の電圧値を測定した。この測定結果のワイブルプロットより求めた破壊確率１０ｐｐｍの破壊電圧を表１〜３に合わせて示す。なお、絶縁破壊の状況は全てセラミックス基板を貫通するものだった。   With respect to the circuit board manufactured by these series of treatments, a dielectric strength test was performed. Using 20 silicon nitride circuit boards prepared under each condition shown in Tables 1 to 3, an AC voltage of 50 Hz is gradually applied between the heat radiation side copper plate and the circuit side copper plate of the circuit board in silicon oil. The voltage value when insulation could not be maintained was measured. The breakdown voltages with a breakdown probability of 10 ppm determined from the Weibull plot of the measurement results are shown in Tables 1-3. In addition, all dielectric breakdown conditions penetrated the ceramic substrate.

表１に示すとおり、本発明の実施例１では、セラミックス基板の厚みｔと回路パターン間のセラミックス基板表面のガラス相が溶出した表面変質層の最大厚みＡの比Ａ／ｔは全て０．０８以下であった。また、絶縁耐圧測定結果も全て３ｋＶ以上であった。これに対し、比較例１および比較例２はＡ／ｔは０．０８を超えており、絶縁耐圧測定結果も３ｋＶ未満であった。   As shown in Table 1, in Example 1 of the present invention, the ratio A / t between the thickness t of the ceramic substrate and the maximum thickness A of the surface altered layer from which the glass phase of the ceramic substrate surface between the circuit patterns was eluted was 0.08. It was the following. In addition, all dielectric breakdown voltage measurement results were 3 kV or more. On the other hand, in Comparative Examples 1 and 2, A / t exceeded 0.08, and the dielectric breakdown voltage measurement result was also less than 3 kV.

また、表２に示すとおり、本発明の実施例２および実施例３では、セラミックス基板の厚みｔと回路パターン間のセラミックス基板表面のガラス相が溶出した表面変質層の最大厚みＡの比Ａ／ｔは全て０．０８以下であった。また、絶縁耐圧測定結果も全て５ｋＶ以上であった。これに対し、比較例３はＡ／ｔは０．０８を超えており、絶縁耐圧測定結果も５ｋＶ未満であった。   Further, as shown in Table 2, in Example 2 and Example 3 of the present invention, the ratio A / of the maximum thickness A of the surface altered layer from which the glass phase of the ceramic substrate surface between the thickness t of the ceramic substrate and the circuit pattern eluted. t was all 0.08 or less. Moreover, the dielectric strength measurement results were all 5 kV or higher. In contrast, in Comparative Example 3, A / t exceeded 0.08, and the dielectric breakdown voltage measurement result was also less than 5 kV.

また、表３に示すとおり、本発明の実施例４および実施例５では、セラミックス基板の厚みｔと回路パターン間のセラミックス基板表面のガラス相が溶出した表面変質層の最大厚みＡの比Ａ／ｔは全て０．０５以下であった。また、絶縁耐圧測定結果も全て７ｋＶ以上であった。これに対し、比較例４はＡ／ｔは０．０５を超えており、絶縁耐圧測定結果も７ｋＶ未満であった。   Further, as shown in Table 3, in Example 4 and Example 5 of the present invention, the ratio A / of the maximum thickness A of the surface altered layer from which the glass phase of the ceramic substrate surface between the thickness t of the ceramic substrate and the circuit pattern eluted. t was all 0.05 or less. Moreover, the dielectric breakdown voltage measurement results were all 7 kV or higher. On the other hand, in Comparative Example 4, A / t exceeded 0.05, and the dielectric breakdown voltage measurement result was also less than 7 kV.

本発明の実施例では、最適条件の酸洗浄もしくは中性洗剤溶液を用いた超音波洗浄を行うことで、電気絶縁性を損なわないことが明らかとなった。なお、本実施例ではアルキルエーテル硫酸エステルナトリウムを含む溶剤を中性洗剤として用いたが、アルキルエーテル硫酸エステルナトリウムを含む中性洗剤に限定されるものではなく、その他の中性洗剤でも同様の効果が得られる。   In the Example of this invention, it became clear by performing the acid cleaning of the optimal conditions, or ultrasonic cleaning using a neutral detergent solution that electrical insulation property is not impaired. In this example, a solvent containing sodium alkyl ether sulfate ester was used as a neutral detergent. However, the present invention is not limited to the neutral detergent containing sodium alkyl ether sulfate ester, and other neutral detergents have the same effect. Is obtained.

本発明は、高信頼性および高放熱性を要するパワーモジュール等に使用されるセラミックス回路基板に利用できる。   INDUSTRIAL APPLICABILITY The present invention can be used for ceramic circuit boards used for power modules and the like that require high reliability and high heat dissipation.

本発明のセラミックス回路基板の各製造工程を示すフローである。It is a flow which shows each manufacturing process of the ceramic circuit board of this invention. 接合工程後のセラミックス回路基板の状況を示す図である。It is a figure which shows the condition of the ceramic circuit board after a joining process. パターン形成工程後のセラミックス回路基板の状況を示す図である。It is a figure which shows the condition of the ceramic circuit board after a pattern formation process. 第一除去工程（反応生成物除去）後のセラミックス回路基板の状況を示す図である。It is a figure which shows the condition of the ceramic circuit board after a 1st removal process (reaction product removal). 第二除去工程（ろう材除去）工程後または化学研磨工程後のセラミックス回路基板の状況を示す図である。It is a figure which shows the condition of the ceramic circuit board after a 2nd removal process (brazing material removal) process or a chemical polishing process.

符号の説明Explanation of symbols

１・・・接合体
２・・・窒化珪素焼結体
２ａ・・・表面変質層
３，４・・・銅板
５，６・・・ろう材
７・・・ろう材層
８・・・反応生成物
９・・・ギャップ
DESCRIPTION OF SYMBOLS 1 ... Bonding body 2 ... Silicon nitride sintered compact 2a ... Surface alteration layer 3, 4 ... Copper plate 5, 6 ... Brazing material 7 ... Brazing material layer 8 ... Reaction production | generation Item 9: Gap

Claims (4)

セラミックス基板にろう材層を介して金属回路板を接合して接合体を得る接合工程と、前記接合体をエッチング溶液に浸漬して金属回路板の不要部分を除去してギャップを形成し回路パターンとするパターン形成工程と、回路パターンを形成した接合体を中性洗浄液に浸漬してギャップにはみ出たろう材層を覆う反応生成物を除去してろう材層を露出させる第一除去工程と、露出した前記ろう材層を除去する第二除去工程とを有することを特徴とするセラミックス回路基板の製造方法。   A circuit pattern in which a metal circuit board is joined to a ceramic substrate through a brazing material layer to obtain a joined body, and the joined body is immersed in an etching solution to remove unnecessary portions of the metal circuit board to form a gap. A pattern forming step, a first removal step of exposing the brazing material layer by immersing the joined body on which the circuit pattern is formed in a neutral cleaning solution to remove the reaction product covering the brazing material layer protruding into the gap, and And a second removing step of removing the brazing filler metal layer. セラミックス基板と、前記セラミックス基板にろう材層を介して接合された金属回路板とを有するセラミックス回路基板であって、前記金属回路板はギャップによって分割されており、前記セラミックス基板の厚みｔと前記ギャップに形成される前記セラミックス基板の表面変質層の最大厚みＡとの比Ａ／ｔが０．０８以下であり、前記セラミックス基板厚みが０．１５ｍｍ以下であり、その絶縁耐圧がＡＣ３ｋＶ以上であることを特徴とするセラミックス回路基板。   A ceramic circuit board having a ceramic substrate and a metal circuit board joined to the ceramic board via a brazing material layer, the metal circuit board being divided by a gap, and the thickness t of the ceramic substrate and the The ratio A / t with respect to the maximum thickness A of the surface altered layer of the ceramic substrate formed in the gap is 0.08 or less, the ceramic substrate thickness is 0.15 mm or less, and its withstand voltage is AC 3 kV or more. A ceramic circuit board characterized by that. セラミックス基板と、前記セラミックス基板にろう材層を介して接合された金属回路板とを有するセラミックス回路基板であって、前記金属回路板はギャップによって分割されており、前記セラミックス基板の厚みｔと前記ギャップに形成される前記セラミックス基板の表面変質層の最大厚みＡとの比Ａ／ｔが０．０８以下であり、前記セラミックス基板厚みが０．２ｍｍ以下であり、その絶縁耐圧がＡＣ５ｋＶ以上であることを特徴とするセラミックス回路基板。   A ceramic circuit board having a ceramic substrate and a metal circuit board joined to the ceramic board via a brazing material layer, the metal circuit board being divided by a gap, and the thickness t of the ceramic substrate and the The ratio A / t to the maximum thickness A of the surface-modified layer of the ceramic substrate formed in the gap is 0.08 or less, the ceramic substrate thickness is 0.2 mm or less, and its withstand voltage is AC 5 kV or more. A ceramic circuit board characterized by that. セラミックス基板と、前記セラミックス基板にろう材層を介して接合された金属回路板とを有するセラミックス回路基板であって、前記金属回路板はギャップによって分割されており、前記セラミックス基板の厚みｔと前記ギャップに形成される前記セラミックス基板の表面変質層の最大厚みＡとの比Ａ／ｔが０．０５以下であり、前記セラミックス基板厚みが０．３５ｍｍ以下であり、その絶縁耐圧がＡＣ７ｋＶ以上であることを特徴とするセラミックス回路基板。
A ceramic circuit board having a ceramic substrate and a metal circuit board joined to the ceramic board via a brazing material layer, the metal circuit board being divided by a gap, and the thickness t of the ceramic substrate and the The ratio A / t to the maximum thickness A of the surface-modified layer of the ceramic substrate formed in the gap is 0.05 or less, the ceramic substrate thickness is 0.35 mm or less, and its withstand voltage is AC 7 kV or more. A ceramic circuit board characterized by that.
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