JP2008141030A - Laminate printed-wiring board - Google Patents

Laminate printed-wiring board Download PDF

Info

Publication number
JP2008141030A
JP2008141030A JP2006326540A JP2006326540A JP2008141030A JP 2008141030 A JP2008141030 A JP 2008141030A JP 2006326540 A JP2006326540 A JP 2006326540A JP 2006326540 A JP2006326540 A JP 2006326540A JP 2008141030 A JP2008141030 A JP 2008141030A
Authority
JP
Japan
Prior art keywords
layer
wiring
layers
wiring board
wiring layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006326540A
Other languages
Japanese (ja)
Other versions
JP4737055B2 (en
Inventor
Shinichi Kimura
伸一 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP2006326540A priority Critical patent/JP4737055B2/en
Publication of JP2008141030A publication Critical patent/JP2008141030A/en
Application granted granted Critical
Publication of JP4737055B2 publication Critical patent/JP4737055B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminate printed-wiring board in which it is possible to confirm the displacement of a wiring layer in each layer in a step before the mounting of an electronic component and the like easily and specify in which layer the wiring layer is displaced. <P>SOLUTION: In a laminate printed-wiring board 2 having a laminate structure in which a plurality of wiring layers 6A-6D is laminated, the wiring layers are insulated by a core member 12 having an insulating property or insulating layers 4A and 4B. The wiring layers have displacement confirming patterns 8A-8D for confirming the displacement of the wiring layers, respectively. Each displacement confirming pattern is formed in such a manner that the displacement confirming pattern is displaced for each wiring layer in a direction orthogonal to the direction of the lamination of each wiring layer. Consequently, the displacement of the wiring layer of each layer is easily confirmed in a step before the mounting of an electronic component and the like. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、積層印刷配線基板に係り、特に配線層の位置ずれを容易に視認可能な積層印刷配線基板に関する。   The present invention relates to a laminated printed wiring board, and more particularly to a laminated printed wiring board in which positional deviation of a wiring layer can be easily visually confirmed.

一般に、電子機器の小型軽量化に伴い、積層印刷配線基板は高密度高多層化された基板が要求されている。ここで、積層印刷配線基板(「多層プリント配線基板」とも称される)において各層の配線層ずれは、接続信頼性から最小状態が確保されなければならない。このため、現在では、ある程度の位置ずれを配慮し、接続ランドパターン径や非接続ランドクリアランス径を大きくして位置ずれに対応するようにしている。しかし、昨今の電子機器の更なる小型化に伴って高密度の積層印刷配線基板が増えてきており、上記接続ランドパターン径や非接続ランドクリアランス径も小さくなる方向にある。このことから、位置ずれによる配線層不良が無視できなくなり、各層の位置ずれ管理が更に必要となってきている。   In general, with the reduction in size and weight of electronic devices, a multilayer printed wiring board is required to have a high-density and multi-layered board. Here, in the laminated printed wiring board (also referred to as “multilayer printed wiring board”), the wiring layer shift of each layer must be ensured to have a minimum state from the connection reliability. For this reason, at present, a certain amount of misalignment is taken into consideration, and the connected land pattern diameter and the non-connected land clearance diameter are increased to cope with the misalignment. However, with the recent miniaturization of electronic devices, the number of high-density laminated printed wiring boards is increasing, and the connected land pattern diameter and the non-connected land clearance diameter are in the direction of decreasing. For this reason, wiring layer defects due to misalignment cannot be ignored, and the misregistration management of each layer is further required.

通常、積層印刷配線基板の検査としては、積層印刷配線基板に電子部品等を実装し、この電子部品に対して通電テストを行うことにより実施される。しかし、この段階で積層印刷配線基板に起因する問題が検出された場合には、実装された電子部品が無駄になってしまう。したがって、電子部品等を実装する前の積層印刷配線基板単体の状態で事前に検査できることが望ましい。   Usually, the inspection of the multilayer printed wiring board is performed by mounting an electronic component or the like on the multilayer printed wiring board and conducting an energization test on the electronic component. However, if a problem caused by the multilayer printed wiring board is detected at this stage, the mounted electronic component is wasted. Therefore, it is desirable to be able to inspect in advance in a state of a single layer printed wiring board before mounting electronic components or the like.

そこで、より精度の高い位置ずれ確認の方法として、積層印刷配線基板に位置精度検査用の基準ホールを形成し、配線層を印刷する時に基準ホールに対応したリング状の位置精度検証用マークを同時に印刷して付加することで、印刷位置の位置ずれを、上記基準ホールと位置精度検証用マークとの同軸度のずれとして確認する方法が開示されている(例えば特許文献1)。   Therefore, as a more accurate method for confirming misalignment, a reference hole for position accuracy inspection is formed on the multilayer printed wiring board, and a ring-shaped position accuracy verification mark corresponding to the reference hole is simultaneously printed when the wiring layer is printed. There has been disclosed a method of confirming the positional deviation of the printing position as a deviation of the coaxiality between the reference hole and the positional accuracy verification mark by printing and adding (for example, Patent Document 1).

特開平10−68696号公報JP-A-10-68696

しかしながら、上述したような特許文献1に開示されたような構造では、現在の積層印刷配線基板のように、より多くの配線層が多層に積層されるようになると、パターン自体の視認が困難になる、という課題があった。更に、複数層の内のどの層の配線層が位置ずれしているのかを特定することが困難である、という問題もあった。   However, in the structure as disclosed in Patent Document 1 as described above, when more wiring layers are stacked in multiple layers as in the current multilayer printed wiring board, it is difficult to visually recognize the pattern itself. There was a problem of becoming. Furthermore, there is a problem that it is difficult to specify which of the plurality of wiring layers is displaced.

本発明は、以上のような問題点に着目し、これを有効に解決すべく創案されたものである。本発明の目的は、電子部品等を実装する前段階で各層の配線層の位置ずれを容易に確認することができるのみならず、どの層の配線層が位置ずれしているのかを特定することができる積層印刷配線基板を提供することにある。   The present invention has been devised to pay attention to the above problems and to effectively solve them. The object of the present invention is not only to easily confirm the displacement of each wiring layer in the stage before mounting an electronic component etc., but also to identify which wiring layer is displaced. An object of the present invention is to provide a laminated printed wiring board that can be used.

請求項1に係る発明は、複数の配線層が積層された積層構造を有する積層印刷配線基板において、前記各配線層は、絶縁性を有するコア材または絶縁層によってそれぞれ絶縁されると共に、前記各配線層同士の位置ずれを確認するための位置ずれ確認用パターンをそれぞれ有し、前記各位置ずれ確認用パターンは、前記各配線層の積層方向に対して直交する方向へ前記各配線層毎に位置をずらして形成されていることを特徴とする積層印刷配線基板積層印刷配線基板である。
この場合、例えば請求項2に記載したように、前記各位置ずれ確認用パターンの形状は、バー形状またはL字形状を有する。
The invention according to claim 1 is the laminated printed wiring board having a laminated structure in which a plurality of wiring layers are laminated, wherein each of the wiring layers is insulated by a core material or an insulating layer having an insulating property, Each of the wiring layer has a misregistration confirmation pattern for confirming misregistration between the wiring layers, and each misregistration confirmation pattern is provided for each wiring layer in a direction perpendicular to the stacking direction of the wiring layers. It is a multilayer printed wiring board characterized by being formed by shifting the position.
In this case, for example, as described in claim 2, the shape of each misregistration confirmation pattern has a bar shape or an L shape.

本発明に係る積層印刷配線基板によれば、電子部品等を実装する前段階で各層の配線層の位置ずれを容易に確認することができるのみならず、どの層の配線層が位置ずれしているのかを特定することができる。   According to the multilayer printed wiring board according to the present invention, it is possible not only to easily check the displacement of the wiring layers of each layer before mounting electronic components, but also to which layer of the wiring layer is displaced. Can be identified.

以下に、本発明に係る積層印刷配線基板の一実施例を添付図面に基づいて詳述する。
図1は本発明に係る積層印刷配線基板の製造工程を示す工程図、図2は各配線層と位置ずれ確認用パターンの配置関係を示す部分平面図、図3は積層印刷配線基板を表面から見た時の一部の状態を示す部分平面図である。
Hereinafter, an embodiment of a multilayer printed wiring board according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a process diagram showing a manufacturing process of a laminated printed wiring board according to the present invention, FIG. 2 is a partial plan view showing an arrangement relationship between each wiring layer and a misregistration confirmation pattern, and FIG. It is a partial top view which shows the one part state when it sees.

図1において、完成された積層印刷配線基板2は、図1(E)に示されており、この積層印刷配線基板2は、複数の配線層、具体的には第1〜第4の4つの配線層6A、6B、6C、6Dを有しており、各配線層6A〜6Dは、絶縁性を有するコア部材12または絶縁層4によってそれぞれ絶縁されると共に、各配線層6A〜6Dの位置ずれを確認するための位置ずれ確認用パターン8A〜8Dを有している。すなわち1つの配線層に対して1つの位置ずれ確認用パターンが設けられている。そして、ここでは各配線層6A〜6Dの積層方向の中心に絶縁性を有する上記コア部材12が位置されており、その両側に上記配線層6A〜6Dが積層されている。   In FIG. 1, the completed multilayer printed wiring board 2 is shown in FIG. 1E, and this multilayer printed wiring board 2 has a plurality of wiring layers, specifically, first to fourth four layers. The wiring layers 6A, 6B, 6C, and 6D are provided, and the wiring layers 6A to 6D are insulated by the insulating core member 12 or the insulating layer 4, respectively, and the wiring layers 6A to 6D are displaced. Misregistration confirmation patterns 8A to 8D are provided. That is, one misregistration confirmation pattern is provided for one wiring layer. In this case, the insulating core member 12 is located at the center of the wiring layers 6A to 6D in the stacking direction, and the wiring layers 6A to 6D are stacked on both sides thereof.

ここで上記積層印刷配線基板2の製造方法について説明する。まず、図1(A)に示すように、絶縁性を有するコア材12の両表面には、例えば銅箔等よりなる導電層6が全面に形成されている。そして、このコア材12の両面の導電層6をパターンエッチングすることにより、図1(B)に示すように第1及び第2配線層6A、6Bを形成する。この際、同時に上記第1及び第2の位置ずれ確認用パターン8A、8Bも形成する。   Here, a method for manufacturing the laminated printed wiring board 2 will be described. First, as shown in FIG. 1A, conductive layers 6 made of, for example, copper foil or the like are formed on the entire surface of both surfaces of the insulating core material 12. Then, the conductive layers 6 on both surfaces of the core material 12 are subjected to pattern etching, thereby forming the first and second wiring layers 6A and 6B as shown in FIG. At this time, the first and second misregistration confirmation patterns 8A and 8B are also formed at the same time.

次に、図1(C)に示すように、上記第1及び第2配線層6A、6Bが形成されている各面の全面に、それぞれ絶縁層4A、4Bを形成すると共に、この各絶縁層4A、4Bの全表面に例えば銅箔よりなる導電層6をそれぞれ形成し、これにより図1(D)に示すような積層構造を作る。   Next, as shown in FIG. 1C, insulating layers 4A and 4B are formed on the entire surfaces of the surfaces on which the first and second wiring layers 6A and 6B are formed. Conductive layers 6 made of, for example, copper foil are respectively formed on the entire surfaces of 4A and 4B, thereby forming a laminated structure as shown in FIG.

次に、上記各導電層6をエッチングすることにより図1(E)に示すように、上記第3及び第4配線層6C、6Dを形成し、この際、同時に上記第3及び第4の位置ずれ確認用パターン8C、8Dも形成する。これにより、積層印刷配線基板2が完成されることになる。   Next, the conductive layers 6 are etched to form the third and fourth wiring layers 6C and 6D as shown in FIG. 1E. At this time, the third and fourth positions are simultaneously formed. Deviation confirmation patterns 8C and 8D are also formed. Thereby, the laminated printed wiring board 2 is completed.

上記各絶縁層4A、4B及びコア部材12は、それぞれ例えばガラス繊維を基材としており、透明、又は半透明な状態になされている。この各絶縁層4A,4Bの厚さは、それぞれ例えば0.1〜2.0mm程度であり、またコア部材12の厚さは例えば0.1〜2.0mm程度である。また各配線層6A〜6Dは配線パターンであり、ここでは便宜上、全て同一形状になっているが、実際には各層が個別の形状でパターン化される。   Each of the insulating layers 4A, 4B and the core member 12 is made of, for example, glass fiber as a base material, and is in a transparent or translucent state. Each of the insulating layers 4A and 4B has a thickness of about 0.1 to 2.0 mm, for example, and the core member 12 has a thickness of about 0.1 to 2.0 mm, for example. Each of the wiring layers 6A to 6D is a wiring pattern. Here, for convenience, all the wiring layers 6A to 6D have the same shape. However, each layer is actually patterned in an individual shape.

そして、上記各位置ずれ確認用パターン8A〜8Dは、上記配線層6A〜6Dの積層方向に対して直交する方向、すなわち表面方向へ各配線層6A〜6D毎に位置をずらして形成されている。具体的には、図1(A)に示すように、コア部材12も絶縁層として、相互に隣り合う配線層6A〜6D間においては、各位置ずれ確認用パターン8A〜8Dは配線層6A〜6Dの積層順に従って所定の間隔L1ずつ層毎に位置をずらして設けられている。尚、ここでは全ての位置ずれ確認用パターン8A〜8Dがバー状(棒状)に形成されている。   The misregistration confirmation patterns 8A to 8D are formed by shifting the positions of the wiring layers 6A to 6D in the direction orthogonal to the stacking direction of the wiring layers 6A to 6D, that is, in the surface direction. . Specifically, as shown in FIG. 1A, the core member 12 is also used as an insulating layer, and between the adjacent wiring layers 6A to 6D, the misregistration confirmation patterns 8A to 8D are formed from the wiring layers 6A to 6A. The positions are shifted for each layer by a predetermined interval L1 according to the 6D stacking order. Here, all the misregistration confirmation patterns 8A to 8D are formed in a bar shape (bar shape).

従って、図3に示すように、積層印刷配線基板2の一方の面より視認した時には、各配線層6A〜6Dの位置ずれが生じていない場合には、各隣り合う位置ずれ確認用パターン8A〜8D間の間隔L1がそれぞれ一定になって配列され、いわゆるゼブラパターンとなるように設定されている。   Therefore, as shown in FIG. 3, when the wiring layers 6 </ b> A to 6 </ b> D are not misaligned when viewed from one surface of the multilayer printed wiring board 2, the adjacent misregistration confirmation patterns 8 </ b> A to 8 </ b> The intervals L1 between 8Ds are arranged so as to be constant, and are set to be a so-called zebra pattern.

この場合、図2にも示すように、各位置ずれ確認用パターン8A〜8Dは直線状、或いは長方形状に形成され、その寸法は、縦H1が例えば0.2〜0.5mm程度、横H2が例えば1.0〜2.0mm程度である。ここで、相互に隣り合う配線層6A〜6Dに対応して、各位置ずれ確認用パターン8A〜8Dも相互に隣り合うように割り当てて配置するのが望ましいが、これに特に限定されるものでなく、各位置ずれ確認用パターン8A〜8Dの位置の割り当てはどのようにしてもよい。   In this case, as shown in FIG. 2, each of the misregistration confirmation patterns 8A to 8D is formed in a linear shape or a rectangular shape. Is, for example, about 1.0 to 2.0 mm. Here, it is desirable that the misregistration confirmation patterns 8A to 8D are also allocated and arranged so as to be adjacent to each other, corresponding to the wiring layers 6A to 6D adjacent to each other, but the present invention is particularly limited to this. In addition, the position of each of the misregistration confirmation patterns 8A to 8D may be assigned in any way.

上述したような各位置ずれ確認用パターン8A〜8Dは、例えば対応する配線層6A〜6Dを印刷形成する時に同時に形成すればよい。また、この位置ずれ確認用パターン8A〜8Dは、図3に示すように積層印刷配線基板2の一面側から見た時に、透明な、或いは半透明な各絶縁層4A、4B及び透明な、或いは半透明なコア材12を通して各位置ずれ確認用パターン8A〜8Dを視認できる程度の不透明な材料よりなる。   Each of the misregistration confirmation patterns 8A to 8D as described above may be formed at the same time when the corresponding wiring layers 6A to 6D are formed by printing, for example. Further, the misregistration confirmation patterns 8A to 8D are transparent or translucent insulating layers 4A and 4B and transparent or transparent when viewed from one side of the laminated printed wiring board 2 as shown in FIG. It is made of an opaque material that can visually recognize the misregistration confirmation patterns 8A to 8D through the semi-transparent core material 12.

さて、以上のように形成された積層印刷配線基板2を、そのいずれか一方の面より見た場合には、図3に示すような状態となり、各層の位置ずれ確認用パターン8A〜8Dを、いわゆるゼブラ状のパターンとして視認することができる。
ここで、ある配線層だけ、位置ずれが生じた状態で積層された場合には、該当する位置ずれ確認用パターン8だけが不規則な状態となったゼブラパターンとなり、容易に視認できる。例えば位置ずれ確認用パターン8の位置ずれが生ずると、隣り合う位置ずれ確認用パターン8との間隙L1が広くなったり、或いは狭くなったり、更には横方向に飛び出したりすることになる。そして、該当する位置ずれ確認用パターン8がどの層であるか、すなわち配線層6A〜6Dの内のどの配線層に割り当てたものであるかを把握することにより、位置ずれしている層を特定することができる。
Now, when the laminated printed wiring board 2 formed as described above is viewed from any one of the surfaces, the state as shown in FIG. 3 is obtained, and the misregistration confirmation patterns 8A to 8D of the respective layers It can be visually recognized as a so-called zebra pattern.
Here, when only a certain wiring layer is laminated in a state where a positional deviation has occurred, only the corresponding positional deviation confirmation pattern 8 becomes a zebra pattern in an irregular state and can be easily recognized. For example, when the positional deviation confirmation pattern 8 is misaligned, the gap L1 between the adjacent positional deviation confirmation patterns 8 is widened or narrowed, and further protrudes in the lateral direction. Then, by identifying which layer the corresponding misregistration confirmation pattern 8 is, that is, to which wiring layer of the wiring layers 6A to 6D is assigned, the misaligned layer is specified. can do.

このように、本発明によれば、電子部品等を実装する前段階で各層の配線層の位置ずれを容易に確認することができるのみならず、どの層の配線層が位置ずれしているのかを特定することができる。   As described above, according to the present invention, it is possible not only to easily check the displacement of the wiring layers of each layer before mounting the electronic component etc., but also which layer of the wiring layer is displaced. Can be specified.

次に、上記位置ずれ確認用パターン8の変形例について説明する。図4は位置ずれ確認用パターンの変形例を示す図であり、図4(A)は第1変形例を示し、図4(B)は第2変形例を示す。
図3に示されたように、ここでは4つの位置ずれ確認用パターン8A〜8Dで構成される一組のゼブラパターンの場合を例にとって説明したが、これに限定されず、図4(A)に示す第1変形例のように、上記ゼブラパターンの配列方向から90度回転した方向に配列される更に4つの位置ずれ確認用パターン10A、10B、10C、10Dを同じように形成し、ゼブラパターンを一対配置するようにしてもよい。
Next, a modified example of the positional deviation confirmation pattern 8 will be described. 4A and 4B are diagrams showing a modification of the misregistration confirmation pattern. FIG. 4A shows a first modification, and FIG. 4B shows a second modification.
As shown in FIG. 3, here, the case of a set of zebra patterns composed of four misregistration confirmation patterns 8A to 8D has been described as an example. However, the present invention is not limited to this, and FIG. As in the first modification shown in FIG. 4, four additional misregistration confirmation patterns 10A, 10B, 10C, and 10D arranged in a direction rotated 90 degrees from the arrangement direction of the zebra pattern are formed in the same manner. You may make it arrange | position a pair.

これによれば、位置ずれの方向をより確実に視認することができる。更には、図4(B)に示す第2変形例のように、位置ずれ確認用パターン8A〜8DをL字形状(或いは”く”の字形状)として配置するようにしてもよい。これによれば、位置ずれの方向をより確実に認識することができると共に、位置ずれ確認用パターン8A〜8Dの配置ペースを小さくできる利点を有する。   According to this, it is possible to visually recognize the direction of positional deviation more reliably. Further, as in the second modified example shown in FIG. 4B, the misregistration confirmation patterns 8A to 8D may be arranged in an L shape (or a “<”) shape. According to this, it is possible to recognize the direction of the positional deviation more reliably and to reduce the arrangement pace of the positional deviation confirmation patterns 8A to 8D.

本発明の積層印刷配線基板2によれば、位置ずれ確認用パターン8A〜8Dよりなる、或いは位置ずれ確認用パターン8A〜8D、10A〜10Dよりなるゼブラパターンをカメラ等のセンサ手段で画像として取り込んで画像解析を実施すれば、検査工程を自動化することも可能である。また、積層印刷配線基板の回路パターンの高密度化により、位置ずれ確認用パターンが極小となっても、光解析等のセンサ手段を利用できるものである。   According to the multilayer printed wiring board 2 of the present invention, the zebra pattern composed of the misregistration confirmation patterns 8A to 8D or the misregistration confirmation patterns 8A to 8D and 10A to 10D is captured as an image by a sensor means such as a camera. If the image analysis is carried out, the inspection process can be automated. Further, even if the positional deviation confirmation pattern is minimized by increasing the density of the circuit pattern of the laminated printed wiring board, sensor means such as optical analysis can be used.

尚、ここでは絶縁層4が4層の場合を例にとって説明したが、この層数に限定されないのは勿論である。また、ここではコア材12に両面側に配線層を積層した場合を例にとって説明したが、これに限定されず、コア材12の片面側のみに、絶縁層を介在させて配線層を多層に積層させるようにしてもよい。   Here, the case where the number of the insulating layers 4 is four has been described as an example, but it is needless to say that the number of layers is not limited. Further, here, the case where the wiring layer is laminated on both sides of the core material 12 has been described as an example, but the present invention is not limited to this, and the wiring layer is formed in multiple layers by interposing an insulating layer only on one side of the core material 12. You may make it laminate.

本発明に係る積層印刷配線基板の製造工程を示す工程図である。It is process drawing which shows the manufacturing process of the multilayer printed wiring board which concerns on this invention. 各配線層と位置ずれ確認用パターンの配置関係を示す部分平面図である。It is a fragmentary top view which shows the arrangement | positioning relationship of each wiring layer and the pattern for position shift confirmation. 積層印刷配線基板を表面から見た時の一部の状態を示す部分平面図である。It is a fragmentary top view which shows a partial state when a laminated printed wiring board is seen from the surface. 位置ずれ確認用パターンの変形例を示す図である。It is a figure which shows the modification of the pattern for position shift confirmation.

符号の説明Explanation of symbols

2…積層印刷配線基板、4A,4B…絶縁層、6,6A〜6D…配線層、8A〜8D,10A〜10D…位置ずれ確認用パターン、12…コア部材。

2 ... Laminated printed wiring board, 4A, 4B ... Insulating layer, 6, 6A-6D ... Wiring layer, 8A-8D, 10A-10D ... Misalignment confirmation pattern, 12 ... Core member.

Claims (2)

複数の配線層が積層された積層構造を有する積層印刷配線基板において、
前記各配線層は、絶縁性を有するコア材または絶縁層によってそれぞれ絶縁されると共に、前記各配線層同士の位置ずれを確認するための位置ずれ確認用パターンをそれぞれ有し、
前記各位置ずれ確認用パターンは、前記各配線層の積層方向に対して直交する方向へ前記各配線層毎に位置をずらして形成されていることを特徴とする積層印刷配線基板。
In a laminated printed wiring board having a laminated structure in which a plurality of wiring layers are laminated,
Each of the wiring layers is insulated by a core material or an insulating layer having an insulating property, and has a misregistration confirmation pattern for confirming misalignment between the wiring layers,
Each of the misregistration check patterns is formed by shifting the position of each wiring layer in a direction orthogonal to the stacking direction of the wiring layers.
前記各位置ずれ確認用パターンの形状は、バー形状またはL字形状を有することを特徴とする請求項1記載の積層印刷配線基板。
2. The multilayer printed wiring board according to claim 1, wherein each of the misregistration confirmation patterns has a bar shape or an L shape.
JP2006326540A 2006-12-04 2006-12-04 Multilayer printed wiring board Active JP4737055B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006326540A JP4737055B2 (en) 2006-12-04 2006-12-04 Multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006326540A JP4737055B2 (en) 2006-12-04 2006-12-04 Multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JP2008141030A true JP2008141030A (en) 2008-06-19
JP4737055B2 JP4737055B2 (en) 2011-07-27

Family

ID=39602182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006326540A Active JP4737055B2 (en) 2006-12-04 2006-12-04 Multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JP4737055B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7927294B2 (en) 2006-02-28 2011-04-19 Twinbird Corporation Massaging device
JP2014027278A (en) * 2012-07-27 2014-02-06 Samsung Electro-Mechanics Co Ltd Printed circuit board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5225265A (en) * 1975-08-22 1977-02-25 Fujitsu Ltd Method of measuring accuracy of pattern on multilayered printed wiring board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5225265A (en) * 1975-08-22 1977-02-25 Fujitsu Ltd Method of measuring accuracy of pattern on multilayered printed wiring board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7927294B2 (en) 2006-02-28 2011-04-19 Twinbird Corporation Massaging device
JP2014027278A (en) * 2012-07-27 2014-02-06 Samsung Electro-Mechanics Co Ltd Printed circuit board

Also Published As

Publication number Publication date
JP4737055B2 (en) 2011-07-27

Similar Documents

Publication Publication Date Title
US8302300B2 (en) Method for manufacturing multilayer printed circuit board with plated through holes
CN101472405B (en) Multi-layer circuit board manufacturing method
CN101212896A (en) Method of inspecting printed wiring board and printed wiring board
JP2009147397A (en) Inspection mark structure, substrate sheet laminate, multilayer circuit board, method of inspecting lamination matching precision of multilayer circuit board, and method of designing substrate sheet laminate
US20010030058A1 (en) Multi-layer printed circuit board registration
JP2010087168A (en) Method for manufacturing multilayer printed circuit board
KR20070082038A (en) Wired circuit board and production method thereof
JPH10163630A (en) Multi-layer printed circuit board and its manufacturing method
JP2007019267A (en) Wiring board and electronic equipment having the same
JP4737055B2 (en) Multilayer printed wiring board
JP5067048B2 (en) Printed wiring board
JP2010073961A (en) Multilayer electronic component, and method of manufacturing the same
JP2734367B2 (en) Multilayer printed wiring board and method of manufacturing the same
JP2006344847A (en) Substrate with built-in component, module equipped with built-in component using same, and method of manufacturing same
JP4817009B2 (en) Method for manufacturing printed wiring board
TWI399152B (en) Method for manufacturing blind hole in printed circuit board
US20070248800A1 (en) Multilayer board having layer configuration indicator portion
JP2005268318A (en) Method for manufacturing multilayer printed wiring board
JP2000294935A (en) Multilayer board and inspection method for the multilayer board
JP3206635B2 (en) Multilayer printed wiring board
JP2005322946A (en) Manufacturing method of printed wiring board and printed wiring board
JP2002252472A (en) Laminated printed board comprising circuit for detecting inter-layer dislocation
JP5104874B2 (en) Lamination sequence inspection method and wiring board manufacturing method
JPH08222859A (en) Multilayered printed board
JP2007234890A (en) Test coupon

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20081226

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110118

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110302

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110405

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110418

R151 Written notification of patent or utility model registration

Ref document number: 4737055

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140513

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140513

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140513

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350