JP2008135445A - Wiring structure and method of forming wiring layer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming wiring capable of fully preventing the separation of a wiring layer, even if the pitch of the wiring layer is narrowed. <P>SOLUTION: A channel 10x for constituting an anchor section 20x preventing the separation of the wiring layer 20 is formed inside the wiring arrangement region of a ground insulating layer 10, and then the wiring layer 20, having the anchor section 20x embedded in the groove 10x and projecting from the upper surface of the ground insulating layer 10, is formed in the wiring arranging region of the ground insulating layer 10. In the method of forming the wiring layer 20, a semi-additive process is preferably used. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wiring structure and a method for forming a wiring layer, and more particularly to a wiring structure and a method for forming a wiring layer that can be suitably applied to a wiring layer of a build-up wiring board.

  Conventionally, a semi-additive method has been widely used as a method for forming a wiring layer of a build-up wiring board. In the semi-additive method, as shown in FIG. 1A, first, the surface of the base resin layer 100 on which the wiring layer is formed is roughened by desmearing. Next, as shown in FIG. 1B, a seed layer 120 made of copper is formed by electroless plating. Subsequently, as shown in FIG. 1C, a resist pattern 140 is formed on the seed layer 120. The resist pattern 140 has an opening 140x in a region where a wiring layer is to be formed.

  Further, as shown in FIG. 1D, a copper layer pattern 160 is formed in the opening 140x of the resist pattern 140 by electrolytic plating using the seed layer 120 as a plating power feeding layer. Next, as shown in FIG. 2A, the resist pattern 140 is removed to expose the seed layer 120. Thereafter, the seed layer 120 is wet etched using the copper layer pattern 160 as a mask.

  As a result, as shown in FIG. 2B, a wiring layer 180 composed of the seed layer 120 and the copper layer pattern 160 is formed on the base resin layer 100. At this time, when the seed layer 120 is wet-etched, the seed layer 120 is easily side-etched from the edge of the copper layer pattern 160 to the inside, thereby forming the wiring layer 180 in a state in which an undercut is generated in the lower portion.

In Patent Document 1, when forming a CSP rewiring layer by a semi-additive method, in order to prevent undercutting of the seed layer, the seed layer is formed with an island-shaped first seed layer and a second seed layer covering the seed layer. It is described that it consists of a seed layer.
JP 2004-71872 A

  In recent years, narrowing of the wiring pitch has been promoted due to demands for higher functionality of build-up wiring boards and higher mounting density. As described above, in the semi-additive method, when the seed layer 120 is etched, it is necessary to perform some over-etching in consideration of the variation in the thickness of the seed layer 120 and the characteristics of wet etching. For this reason, when the wiring pitch is narrowed (wiring width: about 25 μm or less), the adhesion strength between the wiring layer 180 and the underlying resin layer 100 is reduced due to the undercut of the seed layer 120, and the wiring layer 180 is peeled off. Sometimes.

  In the prior art, the surface of the base resin layer is roughened to improve the adhesion of the seed layer to prevent peeling due to undercut. However, there is a limit as a countermeasure against peeling of a wiring layer with a narrower pitch. Although a method for preventing the peeling of the wiring layer by further increasing the surface roughness of the base insulating layer can be considered, if the surface roughness of the base insulating layer is too high, the adhesion of the seed layer is improved, but the resist pattern There is a problem that the adhesion falls and the resist falls down.

  The present invention has been created in view of the above problems, and an object of the present invention is to provide a wiring forming method and a wiring structure capable of sufficiently preventing the wiring layer from being peeled even when the wiring layer has a narrow pitch.

  In order to solve the above problems, the present invention relates to a method for forming a wiring layer, and a step of forming a groove for forming an anchor portion for preventing peeling of the wiring layer inside the wiring arrangement region of the base insulating layer; And the step of forming the wiring layer protruding from the upper surface of the base insulating layer by providing the anchor portion embedded in the groove in the wiring arrangement region of the base insulating layer.

  In one preferred embodiment of the present invention, the step of forming the wiring layer uses a semi-additive method. First, a seed layer is formed on a base insulating layer provided with a groove inside the wiring arrangement region. Next, a resist pattern having openings in the wiring arrangement region on the seed layer is formed. Subsequently, a metal pattern layer is formed in the opening of the resist pattern by electrolytic plating using the seed layer as a plating power feeding layer. Further, after removing the resist pattern, the seed layer is etched using the metal pattern layer as a mask to obtain a wiring layer.

  In the aspect described above, a groove is continuously provided in the central portion of the wiring arrangement region of the base insulating layer, and the anchor portion is formed so that the wiring layer is embedded in the groove and bites into the base insulating layer. For this reason, even when the seed layer is undercut when the seed layer is etched and the width of the seed layer becomes narrow, the wiring layer ensures sufficient adhesion with the base insulating layer by the anchor effect by the groove. . For this reason, even when a wiring layer having a narrow width (for example, 25 μm or less) is formed, peeling of the wiring layer is prevented.

  In another aspect, in the step of forming the wiring layer, a resist pattern is formed on the metal layer formed on the base insulating layer, and the wiring layer is formed by etching the metal layer using the resist pattern as a mask. May be. Also in this embodiment, peeling when forming a fine wiring layer is prevented.

  In addition, when the wiring layer is composed of a densely arranged dense wiring layer and an isolatedly arranged coarse wiring layer, the volume (width and depth) of the groove below the coarse wiring layer where peeling easily occurs. ) May be set larger than the volume of the groove below the dense wiring layer to prevent peeling.

  As described above, according to the present invention, since the groove for forming the anchor portion for preventing the wiring layer from peeling is provided in the wiring arrangement region of the base insulating layer, peeling when forming a fine wiring layer is performed. It is effective for prevention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
3 and 4 are cross-sectional views showing a method for forming a wiring layer according to the first embodiment of the present invention.

  In the wiring layer forming method of the first embodiment, as shown in FIG. 3A, first, a base insulating layer 10 on which a wiring layer is formed is prepared. The base insulating layer 10 is, for example, an insulating core substrate used when manufacturing a build-up wiring board, or an interlayer insulating layer made of resin formed thereon. Alternatively, the base insulating layer 10 may be an insulating layer formed on a silicon substrate or the like. On the base insulating layer 10, a plurality of wiring arrangement regions A in which wiring layers are arranged are defined.

  Thereafter, as shown in FIG. 3B, the base insulating layer 10 is processed with a laser, thereby forming the grooves 10x in the central portion inside each wiring arrangement region A. The width and depth of the grooves 10x. Is set to 30% to 70% (preferably 50%) of the width of the wiring arrangement area A (wiring layer), and is continuously formed corresponding to the area where the wiring layer is arranged. For example, when the width of the wiring layer is 25 μm, the width and depth of the groove 10 x are preferably set to 10 to 15 μm. The groove 10x of the base insulating layer 10 is provided to prevent the wiring layer from being peeled off by an anchor effect when the wiring layer is formed on the base insulating layer 10.

  In particular, when a lower wiring layer is provided under the base insulating layer 10, the depth depends on the depth of the groove 10 x so that the groove 10 x is formed halfway through the base insulating layer 10 without passing through the base insulating layer 10. Thus, the thickness of the base insulating layer 10 is adjusted.

  Instead of using a laser, a resist pattern having an opening corresponding to the groove 10x is formed on the base insulating layer 10, and the base insulating layer 10 is etched through the opening to form the groove 10x. May be. The shape of the groove 10x may be a V shape as illustrated in FIG. 3B, or may be a semicircular shape or a rectangular shape.

  Next, as shown in FIG. 3B, the surface of the base insulating layer 10 including the inner surface of the groove 10x is obtained by applying a desmear process such as a permanganate method to the base insulating layer 10 in which the groove 10x is formed. Roughen.

  Further, as shown in FIG. 3C, a seed layer 12 made of copper or the like is formed on the base insulating layer 10 and the inner surface of the groove 10x by electroless plating or sputtering. The film thickness of the seed layer 12 is set to 0.3 to 1 μm, for example.

  Next, as shown in FIG. 3D, a resist pattern 14 having an opening 14 x in a portion corresponding to the wiring arrangement region A is formed on the seed layer 12. The resist pattern 14 is formed by performing exposure and development after a dry film resist is stuck on the seed layer 12. Alternatively, exposure and development may be performed after applying a liquid resist. Or you may stick the dry film resist provided with the opening part 14x.

  Subsequently, as shown in FIG. 4A, a metal pattern layer 16 made of copper or the like is formed in the opening 14x of the resist pattern 14 by electrolytic plating using the seed layer 12 as a plating power feeding layer. The film thickness of the metal pattern layer 16 is set to 10 to 40 μm, for example. The metal pattern layer 16 is formed so as to fill the groove 10x, and is formed in a state where the upper surface thereof is flat.

  Thereafter, as shown in FIG. 4B, the resist pattern 14 is removed to expose the seed layer 12. Further, the seed layer 12 is wet etched using the metal pattern layer 16 as a mask. When the seed layer 12 is made of copper, a mixed solution of sulfuric acid and hydrogen peroxide is used as an etching solution.

  Thereby, as shown in FIG. 4C, the wiring layer 20 composed of the seed layer 12 and the metal pattern layer 16 is formed on the base insulating layer 10, and the wiring structure of this embodiment is obtained.

  As shown in FIG. 4C, in the wiring structure of this embodiment, a continuous groove 10 x for preventing the wiring layer 20 from peeling off is provided inside the wiring arrangement region A of the base insulating layer 10. A wiring layer 20 that protrudes from the upper surface of the base insulating layer 10 is formed in the wiring arrangement region A of the base insulating layer 10 with the anchor portion 20x embedded in the groove 10x.

  The wiring layer 20 includes a seed layer 12 and a metal pattern layer 16, and has an undercut shape in which the seed layer 12 recedes inward from the edge of the metal pattern layer 16. Further, the surface of the base insulating layer 10 on which the wiring layer 20 is formed is roughened.

  In the wiring layer forming method of the present embodiment, since the relatively deep anchor portion 20x is selectively provided under the wiring layer 20, the wiring layer is formed more than the method of roughening the entire underlying insulating layer as in the prior art. Adhesiveness with 20 base insulating layers 10 can be remarkably improved. Therefore, as shown in FIG. 4C, when the wiring layer 20 is formed by the semi-additive method, the wiring layer 20 is peeled off by the anchor effect even if the seed layer 12 is undercut and its width is narrowed. Is prevented. In addition, since the groove 10x is formed only in a portion of the base insulating layer 10 below the wiring layer 20 and the other region has a normal roughened surface, the resist pattern 14 is formed when the resist pattern 14 is formed. There is no risk of falling.

  As described above, in the method for forming a wiring layer according to the present embodiment, even when a wiring layer having a narrow pitch (for example, line: space = 25: 25 μm or less) is formed, the wiring layer is formed with high yield by preventing peeling. Can be formed.

(Second Embodiment)
FIG. 5 is a cross-sectional view showing a method of forming a wiring layer according to the second embodiment of the present invention. In the second embodiment, the technical idea of the present invention is applied when a wiring layer is formed by patterning a metal layer by photolithography and etching. In the second embodiment, detailed description of the same steps as those in the first embodiment is omitted.

  As shown in FIG. 5A, first, as in the first embodiment, after forming the groove 10x in the central portion of the wiring arrangement region A of the base insulating layer 10, the surface is roughened by applying a desmear process. To do. Next, as shown in FIG. 5B, a metal layer 30 a made of copper or the like is formed on the base insulating layer 10. The metal layer 30a is formed by electroless plating, electrolytic plating, sputtering, or the like. When employing electroplating, the metal layer 30a is formed on a seed layer (not shown).

  Subsequently, as shown in FIG. 5C, a resist pattern 32 for forming a wiring layer is formed on the metal layer 30a. Further, after etching the metal layer 30a using the resist pattern 32 as a mask, the resist pattern 32 is removed. Thereby, as shown in FIG. 5D, the metal layer 30a is patterned, and the wiring layer 30 including the anchor portion 30x embedded in the groove 10x is obtained. As the etching of the metal layer 30a, wet etching or dry etching is employed.

  Also in the second embodiment, since the wiring layer 30 includes the anchor portion 30x embedded in the groove 10x and is formed on the base insulating layer 10, sufficient adhesion between the wiring layer 30 and the base insulating layer 10 due to the anchor effect. Sex is secured. Therefore, even when the fine wiring layer 30 with a narrow pitch is formed, the peeling of the wiring layer 30 is prevented, and the wiring layer 30 can be formed with a high yield.

  Further, even when a finer wiring layer is formed using anisotropic etching, the wiring layer 30 can be stably formed without causing peeling.

(Third embodiment)
6 and 7 are cross-sectional views illustrating a method for forming a wiring layer according to a third embodiment of the present invention. In the third embodiment, the width and depth of the groove are adjusted by the density of the wiring layer.

  As shown in FIG. 6A, first, as in the first embodiment, the base insulating layer 10 in which the wiring arrangement region A is defined is prepared. In the third embodiment, a dense wiring formation region B (line / space region) in which a large number of wiring layers are arranged side by side and a rough wiring layer in which wiring layers are sparsely isolated are disposed on the base insulating layer 10. A wiring formation region C is defined. In particular, when the wiring layer is formed by the semi-additive method, the wiring layer in the rough wiring forming region C tends to be peeled off more easily than the wiring layer in the dense wiring forming region B. This is because wet etching has a relatively large pattern dependency, and the wiring layer in the coarse wiring formation region C tends to have a larger undercut amount in the seed layer than the wiring layer in the dense wiring formation region B. .

  For this reason, in this embodiment, as shown in FIG. 6B, when forming the groove in the base insulating layer 10, the groove 10z in the coarse wiring formation region C is more than the groove 10y in the dense wiring formation region B. The grooves 10y and 10z are formed so as to have a large width and a deep depth. Adjustment of the width and depth of the grooves 10y and 10z in the base insulating layer 10 can be easily performed by adjusting the beam diameter and output of the laser. Further, as in the first embodiment, the surface of the base insulating layer 10 provided with the grooves 10y and 10z is roughened by desmearing.

  Next, as shown in FIG. 6C, the seed layer 12 is formed on the inner surfaces of the grooves 10 y and 10 z and the base insulating layer 10 as in the first embodiment. Further, as shown in FIG. 6D, a resist pattern 14 having an opening 14x in the wiring arrangement region A is formed on the seed layer 12 as in the first embodiment.

  Subsequently, as shown in FIG. 7A, a metal pattern layer 16 is formed in the opening 14x of the resist pattern 14 by electrolytic plating. Further, as shown in FIG. 7B, the resist pattern 14 is removed to expose the seed layer 12. Thereafter, the seed layer 12 is etched using the metal pattern layer 16 as a mask.

  As a result, as shown in FIG. 7C, the dense wiring formation region B (FIG. 6A) includes the anchor portion 20x that is configured by the seed layer 12 and the metal pattern layer 16 and is embedded in the groove 10y. A dense wiring layer 20a is formed. At the same time, in the coarse wiring region C (FIG. 6A), the coarse wiring layer 20b including the anchor portion 20y that is formed of the seed layer 12 and the metal pattern layer 16 and is embedded in the groove 10z is formed.

  The volume (width and depth) of the groove 10z formed under the rough wiring layer 20b is set larger than the volume of the groove 10y formed under the dense wiring layer 20a. As a result, the anchor portion 20y of the coarse wiring layer 20b has a larger volume (contact area) than the anchor portion 20x of the dense wiring 20a, so that a larger anchor effect can be obtained in the coarse wiring layer 20b.

  Therefore, even if undercut occurs more in the seed layer 12 of the coarse wiring layer 20b than in the seed layer 12 of the dense wiring 20a, the anchor portion 20y that can sufficiently prevent peeling is provided under the coarse wiring layer 20b. Therefore, sufficient adhesion is obtained and peeling is prevented.

  As described above, in the third embodiment, the volume (width and depth) of the groove is optimally adjusted depending on the density of the wiring layer, so that the wiring layer can be peeled regardless of the density of the wiring layer. Can be prevented. When adjusting the volume of the groove, both the width and the depth may be adjusted, or either the width or the depth may be adjusted.

  Further, when a wiring layer having a plurality of different widths is formed on the base insulating layer 10, peeling tends to occur as the width becomes thinner. In this case, the volume (depth or width) of the groove provided under the thin wiring layer may be set larger than the volume of the groove formed under the thick wiring layer to prevent peeling. . In addition, a groove may be formed only below a wiring layer having a predetermined width or less (for example, 30 μm or less) in which peeling is likely to occur among a plurality of wiring layers having different widths.

1A to 1D are sectional views (No. 1) showing a method for forming a wiring layer by a semi-additive method of the prior art. 2A and 2B are cross-sectional views (part 2) showing a method of forming a wiring layer by a semi-additive method of the prior art. 3A to 3D are cross-sectional views (part 1) showing the method for forming a wiring layer according to the first embodiment of the present invention. 4A to 4C are sectional views (No. 2) showing the method for forming the wiring layer according to the first embodiment of the present invention. 5A to 5D are cross-sectional views illustrating a method for forming a wiring layer according to the second embodiment of the present invention. 6A to 6D are cross-sectional views (part 1) showing the method for forming a wiring layer according to the third embodiment of the present invention. 7A to 7C are cross-sectional views (part 2) showing the method for forming a wiring layer according to the third embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Base insulating layer, 10x, 10y, 10z ... Groove, 12 ... Seed layer, 14, 32 ... Resist pattern, 14x ... Opening, 16 ... Metal pattern layer, 20, 30 ... Wiring layer, 20x, 20y, 30x ... Anchor part, 20a ... dense wiring layer, 20b ... coarse wiring layer, 30a ... metal layer, A ... wiring arrangement area, B ... dense wiring forming area, C ... coarse wiring forming area.

Claims (10)

Forming a groove for forming an anchor portion for preventing the peeling of the wiring layer inside the wiring arrangement region of the base insulating layer;
A wiring layer comprising the anchor portion embedded in the groove in the wiring arrangement region of the base insulating layer and forming the wiring layer protruding from the upper surface of the base insulating layer. Forming method. The step of forming the wiring layer includes:
Forming a seed layer on the base insulating layer provided with the groove;
Forming a resist pattern in which an opening is provided in the wiring arrangement region on the seed layer;
Forming a metal pattern layer in an opening of the resist pattern by electrolytic plating using the seed layer as a plating power supply layer;
Removing the resist pattern;
The method for forming a wiring layer according to claim 1, further comprising: etching the seed layer using the metal pattern layer as a mask to obtain the wiring layer. The step of forming the wiring layer includes:
Forming a metal layer on the base insulating layer provided with the groove;
Forming a resist pattern on the metal layer;
The method for forming a wiring layer according to claim 1, further comprising: obtaining the wiring layer by etching the metal layer using the resist pattern as a mask. After the step of forming a groove in the base insulating layer,
4. The method for forming a wiring layer according to claim 1, further comprising a step of roughening the entire surface of the base insulating layer.   4. The method according to claim 1, wherein in the step of forming a groove in the base insulating layer, the groove is continuously formed in a central portion of the wiring arrangement region where the wiring layer is formed. A method for forming a wiring layer. In the step of forming the wiring layer, a dense wiring layer arranged densely and a rough wiring layer arranged isolated are formed,
In the step of forming the groove, the volume of the groove formed in the region where the coarse wiring layer is disposed is set larger than the volume of the groove formed in the region where the dense wiring layer is disposed. The method for manufacturing a wiring layer according to any one of claims 1 to 3, wherein A wiring structure of a wiring layer formed on a base insulating layer,
A groove for preventing peeling of the wiring layer is provided inside the wiring arrangement region of the base insulating layer,
The wiring structure, wherein the wiring layer protruding from the upper surface of the base insulating layer is provided in the wiring arrangement region of the base insulating layer with an anchor portion embedded in the groove.   The wiring layer includes a seed layer and a metal pattern layer in order from the bottom, and the seed layer has an undercut shape that recedes inward from an edge of the metal pattern layer. The wiring structure described.   9. The wiring structure according to claim 7, wherein a surface of the base insulating layer on which the wiring layer is formed is roughened over the entire surface.   The wiring layer is composed of densely arranged dense wiring and isolated coarsely arranged wiring, and the volume of the groove formed under the coarsed wiring is formed under the densely wired line. The wiring structure according to claim 7 or 8, wherein the wiring structure is set to be larger than the volume of the groove.

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