JP2008130932A - Semiconductor chip with side electrode, manufacturing method therefor, and three-dimensional mount module with the semiconductor chip laminated therein - Google Patents

Semiconductor chip with side electrode, manufacturing method therefor, and three-dimensional mount module with the semiconductor chip laminated therein Download PDF

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Publication number
JP2008130932A
JP2008130932A JP2006316159A JP2006316159A JP2008130932A JP 2008130932 A JP2008130932 A JP 2008130932A JP 2006316159 A JP2006316159 A JP 2006316159A JP 2006316159 A JP2006316159 A JP 2006316159A JP 2008130932 A JP2008130932 A JP 2008130932A
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Prior art keywords
semiconductor chip
electrode
cutting
semiconductor
side electrodes
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JP2006316159A
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Japanese (ja)
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Toru Maeda
前田　　徹
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Shinkawa Ltd
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Shinkawa Ltd
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Priority to JP2006316159A priority Critical patent/JP2008130932A/en
Priority to PCT/JP2007/072412 priority patent/WO2008062767A1/en
Publication of JP2008130932A publication Critical patent/JP2008130932A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To form a semiconductor chip with a side electrode while securing quality thereof through an inspection by probing in a wafer level. <P>SOLUTION: A metal-filled electrode 27 is formed so that it is disposed to extend over adjacent each circuit region 14 and electrically connected to each circuit region 14. After the metal-filled electrode 27 is formed, a semiconductor wafer is cut along cutting lines 21 present between adjacent each circuit region 14, and a side electrode 31 is formed to the semiconductor chip. After the semiconductor wafer is cut, each semiconductor chip 11 is inspected by probing, thus the semiconductor chip with a side electrode being manufactured. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、側面電極付半導体チップの構造及びその製造方法並びに側面電極付半導体チップを積層した３次元実装モジュールの構造に関する。   The present invention relates to a structure of a semiconductor chip with side electrodes, a manufacturing method thereof, and a structure of a three-dimensional mounting module in which semiconductor chips with side electrodes are stacked.

近年、半導体装置の分野においては、半導体装置の小型化、軽量化を目的として単一のパッケージ内に複数の半導体チップを設け、各半導体チップを３次元に積層するものが多く開発されてきた。このような半導体装置は、マルチチップパッケージ（ＭＣＰ）、またはマルチチップモジュール（ＭＣＭ）と呼ばれ、インターポーザと呼ばれる配線基板に半導体チップを実装し、インターポーザ同士を相互に接続するとともに、積層して１つのモジュールとするものが用いられている（例えば、特許文献１参照）。   In recent years, in the field of semiconductor devices, many devices have been developed in which a plurality of semiconductor chips are provided in a single package and each semiconductor chip is stacked three-dimensionally for the purpose of reducing the size and weight of the semiconductor device. Such a semiconductor device is called a multi-chip package (MCP) or a multi-chip module (MCM). A semiconductor chip is mounted on a wiring board called an interposer, and the interposers are connected to each other and stacked. One module is used (for example, see Patent Document 1).

しかし、特許文献１に記載された従来技術では、略同一の大きさの半導体チップを積層して単一の半導体装置とすることは容易にできるが、各半導体チップをインターポーザに実装し、さらにインターポーザ間の電気的接続を確保するために、複雑な製造工程を要することになる。   However, in the conventional technique described in Patent Document 1, it is easy to stack semiconductor chips having substantially the same size to form a single semiconductor device. However, each semiconductor chip is mounted on an interposer, and further, the interposer In order to secure the electrical connection between them, a complicated manufacturing process is required.

そこで、インターポーザ等の補助的手段を用いることなく半導体チップを３次元に積層して単一モジュールとするいろいろな方法が提案されている。例えば、特許文献２に示されている方法では、次のように半導体チップの３次元実装を行うことが開示されている。   Therefore, various methods have been proposed in which semiconductor chips are three-dimensionally stacked to form a single module without using auxiliary means such as an interposer. For example, the method disclosed in Patent Document 2 discloses performing three-dimensional mounting of a semiconductor chip as follows.

半導体チップに切り出す前のウエハの段階で、チップ毎の端子用電極の外側となる絶縁層の位置に垂直な穴を開け、この穴に溶融メッキ法等により金属を充填した後に、半導体チップを切断、研磨して半導体チップの両面に充填した金属を露出させ、半導体チップの表面と裏面とを貫通する貫通電極を形成させる。次に、この半導体チップの表面（素子形成面）に露出している金属充填部と半導体チップの電極パッドとを配線で接続し、裏面の金属充填部露出面にも電極を形成する。そして、これらの半導体チップ同士を重ね合わせて配線と電極を金属接合することにより、積層された半導体チップの全ての電極パッド相互を接続する。   At the stage of the wafer before cutting into the semiconductor chip, a hole perpendicular to the position of the insulating layer on the outside of the terminal electrode for each chip is made, and after filling the hole with a metal by a hot dipping method etc., the semiconductor chip is cut Then, the metal filled on both sides of the semiconductor chip is polished to expose a through electrode penetrating the front and back surfaces of the semiconductor chip. Next, the metal filling portion exposed on the surface (element formation surface) of the semiconductor chip and the electrode pad of the semiconductor chip are connected by wiring, and an electrode is also formed on the metal filling portion exposed surface on the back surface. Then, by overlapping these semiconductor chips and metal-connecting the wiring and the electrodes, all the electrode pads of the stacked semiconductor chips are connected to each other.

しかし、この特許文献２に記載されている従来技術では、ウエハを研磨して薄くする工程やウエハを切断した後に半導体チップの電極パッドと貫通電極とを接続する配線を取り付ける等の煩雑な工程を有するため、製造工程が複雑となるという問題があった。   However, in the prior art described in Patent Document 2, a process for polishing and thinning the wafer and a complicated process such as attaching a wiring for connecting the electrode pad of the semiconductor chip and the through electrode after cutting the wafer are performed. Therefore, there is a problem that the manufacturing process becomes complicated.

また、特許文献３には、積層する各半導体チップの表面の配線用電極パッドの端面を半導体チップ側面に露出させて接続部とし、これらのパッド端面相互の間にインクジェット方式によって導電性金属ペーストの配線パターンの描画形成を行って接続することが開示されている。この方法によれば、積層された半導体チップの接続を半導体チップの側面を用いて行うため、特許文献２に記載された従来技術よりも短い配線で多様な接続を行うことが可能となる。また、製造工程も特許文献２に記載された従来技術よりも簡単にできる。   Further, in Patent Document 3, the end surface of the wiring electrode pad on the surface of each semiconductor chip to be laminated is exposed on the side surface of the semiconductor chip to form a connection portion, and a conductive metal paste is formed between these pad end surfaces by an ink jet method. It is disclosed that a wiring pattern is drawn and connected. According to this method, since the stacked semiconductor chips are connected using the side surfaces of the semiconductor chips, various connections can be made with a shorter wiring than the conventional technique described in Patent Document 2. Also, the manufacturing process can be made simpler than the conventional technique described in Patent Document 2.

しかし、特許文献３に記載された従来技術は、半導体チップの表面に形成されたパッドの端面を接続していることから、導電面積が少なくなり電気的な接続を確保しにくいという問題があった。また、特許文献３には上記の半導体チップの側面に端面を露出させて側面電極とする方法については開示がされていない。   However, the prior art described in Patent Document 3 has a problem in that it is difficult to ensure electrical connection because the conductive area is reduced because the end faces of the pads formed on the surface of the semiconductor chip are connected. . Further, Patent Document 3 does not disclose a method for exposing the end surface to the side surface of the semiconductor chip to form a side electrode.

また、特許文献２には、半導体チップ表面の電極パッドからチップ周縁部に向かってインクジェット法によって導電性微粒子を含む液体を連続的に滴下し、半導体チップ表面の電極パッドからチップ側面まで連続する端子を形成する方法が開示されている。そして、この方法によって、半導体チップの側面にはシリコン基板と絶縁層との境界位置あるいは、それより上側まで端子が形成され、側面電極が形成される。   Further, in Patent Document 2, a liquid containing conductive fine particles is continuously dropped from an electrode pad on the surface of a semiconductor chip toward the peripheral edge of the chip by an ink jet method, and a terminal that continues from the electrode pad on the surface of the semiconductor chip to the side surface of the chip. A method of forming is disclosed. By this method, the terminal is formed on the side surface of the semiconductor chip up to the boundary position between the silicon substrate and the insulating layer or the upper side thereof, and the side electrode is formed.

しかし、この特許文献２に記載された側面電極は、ウエハから切り離して完成された半導体チップの表面のそれぞれの電極から側面電極を再配線によって形成するものであることから、半導体製造のいわゆる後工程での工数が多くなってしまうという問題があった。   However, since the side electrodes described in Patent Document 2 are formed by rewiring the side electrodes from the respective electrodes on the surface of the semiconductor chip completed by separating from the wafer, a so-called post-process of semiconductor manufacturing is performed. There was a problem that the number of man-hours would increase.

一方、ウエハの状態で各半導体チップに側面電極を形成する方法が特許文献４に記載されている。これは、ウエハの半導体チップ切断用ライン上に電極形成用の穴を形成し、この穴の中に電極部を形成した後、電極部の形成された切断用ラインを切断して半導体チップを形成する方法である。ここで、電極形成用の穴はウエットエッチング等のウエットプロセス又は、ドライエッチング等のドライプロセス等により形成される、電極形成予定領域に収まる大きさの穴よりも小さな穴である。そして、この穴の内表面にスパッタ蒸着や真空蒸着、エッチング等によって電極材を付着させた後、ウエハ切断ラインに従って切断し、半導体チップの側面に電極を形成するものである。   On the other hand, Patent Document 4 discloses a method of forming side electrodes on each semiconductor chip in a wafer state. This is because a hole for forming an electrode is formed on a semiconductor chip cutting line of a wafer, an electrode part is formed in the hole, and then a cutting line in which the electrode part is formed is cut to form a semiconductor chip. It is a method to do. Here, the hole for forming an electrode is a hole smaller than a hole having a size that can be accommodated in a region where an electrode is to be formed, formed by a wet process such as wet etching or a dry process such as dry etching. Then, an electrode material is attached to the inner surface of the hole by sputtering deposition, vacuum deposition, etching, or the like, and then cut according to a wafer cutting line to form an electrode on the side surface of the semiconductor chip.

しかし、特許文献４に記載された側面電極の形成方法は、ウエハの状態で側面電極を形成することができるものの、ウエハ上で隣り合う各半導体チップに跨って共通の電極を形成して、その共通電極を切断し、各半導体チップに側面電極を形成していることから、ウエハの状態で各半導体チップのプロービングによる検査を行うことができず、完成した半導体チップの品質を維持することが難しいという問題があった。   However, although the method for forming side electrodes described in Patent Document 4 can form side electrodes in the state of a wafer, a common electrode is formed across adjacent semiconductor chips on the wafer. Since the common electrode is cut and the side electrodes are formed on each semiconductor chip, it is difficult to inspect each semiconductor chip by probing in the wafer state, and it is difficult to maintain the quality of the completed semiconductor chip. There was a problem.

半導体チップの製造においては、品質を確保するためにウエハから各半導体チップを切断して形成する前に、ウエハ上でプロービングによる検査を実施することが一般的に行われている（例えば、特許文献５参照）。近年は、ウエハの切断ライン上の切断領域に隣あう半導体チップに跨った共通電極を設けて、この共通電極にプロービングピンを当ててプロービング検査を行う技術が提案されているが（例えば、特許文献５参照）、隣り合う半導体チップの隣り合う電極パッドは、例えば、一方が信号電極で他方が電源電極となっている等のように、異なる端子となっている場合が多い。このため、共通電極によってプロービング検査が実施できるのは、ウエハ上の隣り合う半導体チップの電極パッドが同一の端子として形成されるようにウエハの設計が出来るような比較的簡単な回路パターンの場合に限られる。   In the manufacture of semiconductor chips, it is common practice to perform inspection by probing on a wafer before cutting and forming each semiconductor chip from the wafer in order to ensure quality (for example, patent documents). 5). In recent years, a technique has been proposed in which a common electrode straddling a semiconductor chip adjacent to a cutting region on a wafer cutting line is provided, and a probing pin is applied to the common electrode to perform a probing inspection (for example, Patent Documents). 5), adjacent electrode pads of adjacent semiconductor chips are often different terminals, for example, one is a signal electrode and the other is a power supply electrode. For this reason, the probing inspection can be performed with the common electrode in the case of a relatively simple circuit pattern in which the wafer can be designed so that the electrode pads of adjacent semiconductor chips on the wafer are formed as the same terminal. Limited.

従って、特許文献４に記載された半導体チップの側面電極の形成方法では、ウエハの状態で各半導体チップのプロービングによる検査を十分に行うことができず、半導体チップの品質を確保することが難しいという問題があった。   Therefore, in the method for forming the side electrodes of the semiconductor chip described in Patent Document 4, it is difficult to sufficiently inspect each semiconductor chip by probing in the wafer state, and it is difficult to ensure the quality of the semiconductor chip. There was a problem.

特開平１１−１３５７１１号公報Japanese Patent Laid-Open No. 11-135711 特開２００４−３０３８８４号公報Japanese Patent Laid-Open No. 2004-303884 特開２００１−２５０９０６号公報JP 2001-250906 A 特開平６−５６６５号公報JP-A-6-5665 特開平６−１５１５３５号公報JP-A-6-151535

以上述べたように、特許文献１に記載された従来技術では、各半導体チップをインターポーザに実装してから３次元実装するために複雑な製造工程を要し、特許文献２に記載の従来技術では、ウエハを研磨して薄くする工程やウエハを切断した後に半導体チップの電極パッドと貫通電極とを接続する配線を取り付ける等の煩雑な工程を有するため、製造工程が複雑となるという問題があり、特許文献２に記載の他の方法でも、ウエハから切り離して完成された半導体チップの表面のそれぞれの電極から側面電極を再配線によって形成するものであることから、半導体製造のいわゆる後工程での工数が多くなってしまうという問題があり、特許文献４に記載された半導体チップの側面電極の形成方法では、ウエハの状態で各半導体チップのプロービングによる検査を十分に行うことができず、半導体チップの品質を確保することが難しいという問題があった。   As described above, in the conventional technique described in Patent Document 1, a complicated manufacturing process is required to mount each semiconductor chip on an interposer and then three-dimensionally. In the conventional technique described in Patent Document 2, There is a problem that the manufacturing process becomes complicated because it has a complicated process such as attaching a wiring connecting the electrode pad of the semiconductor chip and the through electrode after cutting the wafer and thinning the wafer and cutting the wafer. Even in the other method described in Patent Document 2, the side electrodes are formed by rewiring from the respective electrodes on the surface of the semiconductor chip completed by separating from the wafer. In the method for forming side electrodes of a semiconductor chip described in Patent Document 4, the process of each semiconductor chip is performed in a wafer state. Can not be inspected by Bing sufficiently, it is difficult to ensure the quality of the semiconductor chip.

このように、従来技術では、ウエハの状態においてプロービング検査による半導体チップの品質を確保しつつ側面電極を形成することができないという問題があった。   As described above, the conventional technique has a problem that the side electrodes cannot be formed while ensuring the quality of the semiconductor chip by the probing inspection in the wafer state.

本発明は、ウエハの状態においてプロービング検査による品質を確保しつつ側面電極が形成された半導体チップを提供することを目的とする。   An object of the present invention is to provide a semiconductor chip in which side electrodes are formed while ensuring quality by probing inspection in a wafer state.

本発明の側面電極付半導体チップは、複数の回路領域が形成されている半導体ウエハを切断して製造する側面電極付半導体チップであって、隣接する前記各回路領域に跨って配置され、前記各回路領域に電気的に接続される電極を形成し、前記電極形成の後に隣接する前記各回路領域の間にある切断線に沿って前記半導体ウエハを切断して前記半導体チップに側面電極を形成し、前記切断の後に各半導体チップをプロービングによって検査して製造することを特徴とする。また、本発明の側面電極付半導体チップにおいて、前記電極は貫通電極であること、としても好適であるし、前記電極は回路領域に配置されたバンプであること、としても好適である。   The semiconductor chip with a side electrode of the present invention is a semiconductor chip with a side electrode manufactured by cutting a semiconductor wafer on which a plurality of circuit regions are formed, and is disposed across the adjacent circuit regions. Forming an electrode electrically connected to the circuit region, cutting the semiconductor wafer along a cutting line between adjacent circuit regions after forming the electrode, and forming a side electrode on the semiconductor chip; The semiconductor chip is manufactured by inspecting each semiconductor chip by probing after the cutting. In the semiconductor chip with a side electrode of the present invention, the electrode is preferably a through electrode, and the electrode is preferably a bump disposed in a circuit region.

本発明の３次元実装モジュールは、複数の回路領域が形成されている半導体ウエハの隣接する前記各回路領域に跨って配置され、前記各回路領域に電気的に接続される電極を形成し、前記電極形成の後に隣接する前記回路領域の間にある切断線に沿って前記半導体ウエハを切断して側面電極を形成し、前記切断の後にプロービングによって検査して製造する側面電極付半導体チップの前記各側面電極相互を電気的に接続して積層したこと、を特徴とする。また、前記各側面電極相互をワイヤボンディング装置によって接続すること、としても好適である。   The three-dimensional mounting module of the present invention is disposed across each circuit region adjacent to a semiconductor wafer on which a plurality of circuit regions are formed, and forms an electrode electrically connected to each circuit region, Each of the semiconductor chips with side electrodes manufactured by cutting the semiconductor wafer along a cutting line between adjacent circuit regions after electrode formation to form side electrodes, and inspecting and manufacturing by probing after the cutting The side electrodes are stacked by being electrically connected to each other. It is also preferable that the side electrodes are connected to each other by a wire bonding apparatus.

本発明の側面電極付半導体チップの製造方法は、複数の回路領域が形成されている半導体ウエハを切断して製造する側面電極付半導体チップの製造方法であって、隣接する前記各回路領域に跨って配置され、前記各回路領域と電気的に接続される電極を形成する電極形成工程と、前記電極形成工程の後に隣接する前記回路領域の間にある切断線に沿って前記半導体ウエハを切断して前記半導体チップに側面電極を形成する切断工程と、前記切断工程の後に各半導体チップをプロービングによって検査する検査工程と、を有することを特徴とする。また、本発明の側面電極付半導体チップの製造方法において、前記電極は貫通電極であること、としても好適であるし、前記電極は回路領域に配置されたバンプであること、としても好適である。   The method for manufacturing a semiconductor chip with side electrodes according to the present invention is a method for manufacturing a semiconductor chip with side electrodes, which is manufactured by cutting a semiconductor wafer on which a plurality of circuit regions are formed, and straddles the adjacent circuit regions. Forming an electrode electrically connected to each of the circuit regions, and cutting the semiconductor wafer along a cutting line between the adjacent circuit regions after the electrode forming step. A cutting step of forming side electrodes on the semiconductor chip, and an inspection step of inspecting each semiconductor chip by probing after the cutting step. In the method of manufacturing a semiconductor chip with a side electrode according to the present invention, the electrode is preferably a through electrode, and the electrode is a bump disposed in a circuit region. .

本発明の３次元実装モジュールの製造方法は、複数の回路領域が形成されている半導体ウエハの隣接する前記各回路領域に跨って配置され、前記各回路領域に電気的に接続される電極を形成し、前記電極形成の後に隣接する前記回路領域の間にある切断線に沿って前記半導体ウエハを切断して側面電極を形成し、前記切断の後にプロービングによって検査して製造する複数の側面電極付半導体チップを積層する積層工程と、前記積層工程の後、前記各側面電極相互をワイヤボンディング装置によって電気的に接続するワイヤボンディング工程と、を有することを特徴とする。また、本発明の３次元実装モジュールの製造方法において、前記ワイヤボンディング装置は、積層された前記半導体チップを積層方向に押圧してボンディングを行うこと、としても好適であるし、積層された前記半導体チップの側面角部を前記側面電極に対するボンディングツールの接離方向に保持してボンディングを行うこと、としても好適である。   The method for manufacturing a three-dimensional mounting module according to the present invention forms electrodes that are arranged across the circuit regions adjacent to each other in the semiconductor wafer on which a plurality of circuit regions are formed, and are electrically connected to the circuit regions. And forming a side electrode by cutting the semiconductor wafer along a cutting line between adjacent circuit regions after forming the electrode, and inspecting and manufacturing by probing after the cutting. It is characterized by comprising a laminating step of laminating semiconductor chips, and a wire bonding step of electrically connecting the side electrodes to each other by a wire bonding apparatus after the laminating step. In the method of manufacturing a three-dimensional mounting module according to the present invention, the wire bonding apparatus may be suitable for bonding by pressing the stacked semiconductor chips in a stacking direction, and the stacked semiconductors It is also preferable to perform bonding while holding the side corners of the chip in the contact / separation direction of the bonding tool with respect to the side electrodes.

本発明は、ウエハの状態においてプロービング検査による品質を確保しつつ側面電極が形成された半導体チップを提供することができるという効果を奏する。   The present invention can provide a semiconductor chip in which side electrodes are formed while ensuring quality by probing inspection in the state of a wafer.

図面を参照しながら、本発明の好適な実施形態について説明する。図１及び図２を参照しながら側面電極付半導体チップの製造工程と構造について説明する。図１は、ウエハの断面からみた半導体チップの製造工程と構造を示し、図２はウエハの平面方向から見た半導体チップの製造工程と構造を示している。   A preferred embodiment of the present invention will be described with reference to the drawings. The manufacturing process and structure of the semiconductor chip with side electrodes will be described with reference to FIGS. FIG. 1 shows the manufacturing process and structure of a semiconductor chip as seen from the cross section of the wafer, and FIG. 2 shows the manufacturing process and structure of the semiconductor chip as seen from the plane direction of the wafer.

図１（ａ）、図２（ａ）に示すように、ウエハには複数の半導体チップ１１が形成されている。各半導体チップ１１のウエハの基板１３表面側には、電子回路が形成された回路部１５と回路部１５の周縁に形成された絶縁部に、回路部１５への信号の入出力あるいは電源の供給などを行う電極パッド１７が形成されている。図１、図２に示すように、回路部１５及びその周縁の電極パッド１７を含む絶縁部は幅Ａの回路領域１４を形成する。また、各回路部１５の間には、ウエハを切断してそれぞれの半導体チップ１１を分割する切断線２１が配置されている。ウエハの切断は有限の刃幅を有するダイヤモンドカッター等で行われるので、ウエハを切断する際にはダイヤモンドカッターの刃幅だけウエハは削り取られる。それぞれの半導体チップ１１の外延を形成している切断線２１の間の幅Ｂの領域は、この切断によって削り取られる切断領域２３となる。上記の電極パッド１７はその一部が回路領域１４から切断領域２３に延出して形成されている。また、ウエハの基板１３の回路部１５と反対側の面には絶縁性のテープ１９が貼り付けられている。テープ１９はウエハの基板１３を各半導体チップ１１に切断した際に、各半導体チップ１１が分離しないようにするものである。   As shown in FIGS. 1A and 2A, a plurality of semiconductor chips 11 are formed on the wafer. On the surface side of the substrate 13 of the wafer of each semiconductor chip 11, input / output of signals to the circuit unit 15 or supply of power to the circuit unit 15 in which electronic circuits are formed and an insulating unit formed at the periphery of the circuit unit 15. An electrode pad 17 for performing the above is formed. As shown in FIGS. 1 and 2, the insulating portion including the circuit portion 15 and the electrode pad 17 at the periphery thereof forms a circuit region 14 having a width A. Further, a cutting line 21 for cutting the wafer and dividing each semiconductor chip 11 is disposed between the circuit portions 15. Since the wafer is cut by a diamond cutter having a finite blade width, the wafer is cut by the blade width of the diamond cutter when the wafer is cut. A region having a width B between the cutting lines 21 forming the extension of each semiconductor chip 11 becomes a cutting region 23 that is scraped off by this cutting. A part of the electrode pad 17 extends from the circuit region 14 to the cutting region 23. An insulating tape 19 is attached to the surface of the wafer substrate 13 opposite to the circuit portion 15. The tape 19 prevents the semiconductor chips 11 from being separated when the wafer substrate 13 is cut into the semiconductor chips 11.

図１（ｂ）に示すように、回路部１５と電極パッド１７とが形成されたウエハの切断領域２３にエッチング加工、レーザ加工、プラズマ加工又はドリル等によって穴２５を形成する。穴２５は、各半導体チップ１１の間の切断領域２３の中心線と各電極パッド１７の切断線２１に直角方向の中心線との交点を中心とする位置に設けられ、その直径が切断領域２３よりも大きな直径を有している。したがって、穴２５がウエハに形成されると、穴２５の内表面には回路領域１４から切断領域２３に延出している電極パッド１７の端面が露出する。また、本実施形態では、穴２５の深さは表面から基板１３までの深さで、テープ１９には達しない深さである。これは、穴の深さは側面に形成される電極の高さとなるため、この側面電極の高さがワイヤボンディング等の方法によって接続できる高さであればよいためである。   As shown in FIG. 1B, a hole 25 is formed in the cutting region 23 of the wafer on which the circuit portion 15 and the electrode pad 17 are formed by etching processing, laser processing, plasma processing, drilling, or the like. The hole 25 is provided at a position centering on the intersection of the center line of the cutting region 23 between the semiconductor chips 11 and the center line perpendicular to the cutting line 21 of each electrode pad 17, and the diameter thereof is the cutting region 23. Has a larger diameter. Therefore, when the hole 25 is formed in the wafer, the end surface of the electrode pad 17 extending from the circuit region 14 to the cutting region 23 is exposed on the inner surface of the hole 25. Further, in the present embodiment, the depth of the hole 25 is a depth from the surface to the substrate 13 and does not reach the tape 19. This is because the depth of the hole is the height of the electrode formed on the side surface, so that the height of the side electrode only needs to be a height that can be connected by a method such as wire bonding.

図１（ｃ）に示すように、穴開けの後、穴２５の内部にメッキ、プラズマ等による化学蒸着法（ＣＶＤ）や、抵抗加熱、電子ビーム、高周波誘導、レーザなどの方法で加熱蒸着する物理蒸着法（ＰＶＤ）等によって金属を埋め込む。金属は銅や銀等導電性に優れた金属を用いる。円柱状に穴に埋め込まれた金属は穴２５の内面に露出している電極パッド１７の端面に密着して金属充填電極２７を形成し、電極パッド１７と電気的に接続される。この際、金属充填電極２７は隣り合っている半導体チップ１１に設けられているそれぞれ対向する位置にある電極パッド１７相互も電気的に接続する。この状態をウエハの平面から見ると、図２（ｂ）に示すように、金属充填電極２７は、隣接する半導体チップ１１に設けられた電極パッド１７を含む各回路領域１４に跨って設けられ、各電極パッド１７と接続されている状態となっている。   As shown in FIG. 1C, after the hole is formed, the inside of the hole 25 is heated and evaporated by a chemical vapor deposition method (CVD) such as plating, plasma, resistance heating, electron beam, high frequency induction, or laser. Metal is embedded by physical vapor deposition (PVD) or the like. As the metal, a metal having excellent conductivity such as copper or silver is used. The metal embedded in the hole in a cylindrical shape is in close contact with the end face of the electrode pad 17 exposed on the inner surface of the hole 25 to form a metal-filled electrode 27 and is electrically connected to the electrode pad 17. At this time, the metal-filled electrode 27 is also electrically connected to the electrode pads 17 that are provided on the adjacent semiconductor chips 11 and that are located at opposing positions. When this state is viewed from the plane of the wafer, as shown in FIG. 2B, the metal-filled electrode 27 is provided across each circuit region 14 including the electrode pad 17 provided on the adjacent semiconductor chip 11, It is in a state of being connected to each electrode pad 17.

次に、図１（ｄ）に示すように、ダイヤモンドカッター等の切断手段によって、切断線２１に沿ってウエハを切断する。切断によって削り取られる切断領域２３の幅Ｂは穴２５に埋め込まれた金属充填電極２７の直径よりも狭くなっていることから、切断によって、各切断線２１に沿って各電極パッド１７に電気的に接続された側面電極３１が露出する。この切断においては、各半導体チップ１１が分離しないように、半導体チップ１１の構成されている基板１３の部分のみを切断し、テープ１９の部分までは切断しない。このようにすることによって、ウエハ上の半導体チップ１１を一体の状態に保つことができると共に、隣り合う電極パッド１７相互を接続している金属充填電極２７を切断領域２３によって各半導体チップ１１に属する部分に分けることができる。テープ１９は絶縁性であることから、上記の切断によって、隣り合う半導体チップ１１の電極パッド１７同士は電気的に分離されることとなる。この状態をウエハの平面から見ると、図２（ｃ）のようになる。   Next, as shown in FIG. 1D, the wafer is cut along the cutting line 21 by a cutting means such as a diamond cutter. Since the width B of the cutting region 23 scraped off by cutting is narrower than the diameter of the metal-filled electrode 27 embedded in the hole 25, each electrode pad 17 is electrically connected along the cutting line 21 by cutting. The connected side electrode 31 is exposed. In this cutting, only the portion of the substrate 13 on which the semiconductor chip 11 is configured is cut and the tape 19 is not cut so that the semiconductor chips 11 are not separated. By doing so, the semiconductor chips 11 on the wafer can be kept in an integrated state, and the metal-filled electrodes 27 connecting the adjacent electrode pads 17 belong to each semiconductor chip 11 by the cutting region 23. Can be divided into parts. Since the tape 19 is insulative, the electrode pads 17 of the adjacent semiconductor chips 11 are electrically separated by the above cutting. When this state is viewed from the plane of the wafer, it is as shown in FIG.

この状態では、各半導体チップ１１はテープ１９によって一体となっており、且つ、隣り合う半導体チップ１１の対向する各電極パッド１７は互いに電気的に分離された状態となっている。この状態でプロービングによって各半導体の機能検査を行う。機能検査は検査用のプローブを各半導体チップ１１の電極パッド１７又は側面電極３１に接触させて信号を入力してその機能を確認する検査を行う（ＫＧＤ）。隣り合う半導体チップ１１は電気的に分離されていることから、互いに干渉することなく各半導体チップ１１の検査を良好に行うことができるという効果を奏する。そして、検査の結果不良となった半導体チップ１１にはマーキングなどを行う。   In this state, the semiconductor chips 11 are integrated with the tape 19, and the opposing electrode pads 17 of the adjacent semiconductor chips 11 are electrically separated from each other. In this state, functional inspection of each semiconductor is performed by probing. In the function inspection, an inspection probe is brought into contact with the electrode pad 17 or the side electrode 31 of each semiconductor chip 11 and a signal is input to check the function (KGD). Since the adjacent semiconductor chips 11 are electrically separated, there is an effect that each semiconductor chip 11 can be inspected satisfactorily without interfering with each other. Then, marking or the like is performed on the semiconductor chip 11 that has become defective as a result of the inspection.

機能検査が終了したら、図１（ｅ）に示すように、テープ１９から各半導体チップ１１が分離され、側面電極３１が各半導体チップ１１の側面に形成された側面電極付半導体チップ１１０となる。図３に示すように、この製造された側面電極付半導体チップ１１０はチップの各側面に部分円筒状の貫通電極が形成されており、その貫通電極の切断面が側面電極３１となっている。各側面電極３１は各半導体チップ１１の回路部１５の周縁にある絶縁部に形成されているので、それぞれ電気的に分離された電極として機能する。   When the functional inspection is completed, as shown in FIG. 1E, each semiconductor chip 11 is separated from the tape 19, and the side electrode 31 becomes the semiconductor chip 110 with side electrode formed on the side surface of each semiconductor chip 11. As shown in FIG. 3, the manufactured semiconductor chip with side electrode 110 has a partial cylindrical through electrode formed on each side surface of the chip, and a cut surface of the through electrode serves as a side electrode 31. Since each side electrode 31 is formed in the insulating part in the periphery of the circuit part 15 of each semiconductor chip 11, it functions as an electrically isolated electrode.

以上述べた、本実施形態では、ウエハの状態で側面電極３１を形成することができるので側面電極３１を半導体製造工程のいわゆる前工程において形成することができ、半導体チップの実装工程である後工程を簡略にすることができるという効果を奏する。また、側面電極３１はウエハの状態でプロービング機能検査によって品質を確保してから後工程において半導体の実装をすることができることから、半導体製品の品質及び歩留まりを向上させることができるという効果を奏する。   In the present embodiment described above, since the side electrode 31 can be formed in a wafer state, the side electrode 31 can be formed in a so-called pre-process of the semiconductor manufacturing process, and a post-process that is a semiconductor chip mounting process. There is an effect that can be simplified. In addition, since the side electrode 31 can be mounted in a subsequent process after ensuring the quality by probing function inspection in the state of the wafer, it is possible to improve the quality and yield of the semiconductor product.

本実施形態では、穴２５はウエハの基板１３の厚みと同じ厚みで説明したが、半導体チップ１１の側面に形成される側面電極３１の高さが側面電極３１相互をワイヤボンディング等によって接続することができる高さであれば基板１３厚さと同様の深さではなく、例えば半分程度の深さとして、基板１３の厚みの半分程度の側面電極を形成するようにしてもよい。この場合、基板１３の回路部１５の周縁部には絶縁領域が形成されているので、切断線２１に沿った切断も基板１３の厚みと同等の厚さを切断する必要はなく、穴２５に形成された金属充填電極２７の深さよりも深く切断すればよい。この深さまで切断すれば、隣り合う半導体チップ１１は電気的に分離されるからである。このような半分高さのカット（ハーフカット）によって側面電極３１を形成して隣り合う各半導体チップ１１を電気的に分離した後、先に述べたのと同様の方法によって、各半導体チップ１１の機能検査を実施する。この場合も、検査の際には隣り合う各半導体チップが電気的に分離されているので、検査の際に各半導体チップ１１が相互に干渉することがなく、良好に検査をすることができる。   In the present embodiment, the hole 25 is described as having the same thickness as the substrate 13 of the wafer. However, the side electrodes 31 formed on the side surfaces of the semiconductor chip 11 are connected to each other by wire bonding or the like. However, the side electrode may be formed to have a depth that is about the half of the thickness of the substrate 13 instead of the depth similar to the thickness of the substrate 13. In this case, since the insulating region is formed in the peripheral portion of the circuit portion 15 of the substrate 13, it is not necessary to cut along the cutting line 21 to a thickness equivalent to the thickness of the substrate 13. What is necessary is just to cut | disconnect deeper than the depth of the formed metal filling electrode 27. FIG. This is because the adjacent semiconductor chips 11 are electrically separated by cutting to this depth. After the side electrodes 31 are formed by such a half-height cut (half-cut) and the adjacent semiconductor chips 11 are electrically separated, the semiconductor chips 11 are separated by the same method as described above. Perform functional tests. Also in this case, since the adjacent semiconductor chips are electrically separated at the time of inspection, the semiconductor chips 11 do not interfere with each other at the time of inspection and can be inspected satisfactorily.

一方、ポッティングによって半導体チップ１１を積層していく場合には、半導体チップ１１の電極パッド１７と反対側の面に電極パッド１７と接続できるように電極を貫通、突出させておく必要がある。このような場合には、穴２５はテープ１９まで貫通した穴として貫通した側面電極３１であって、テープ１９の厚み分だけ側面電極３１が突出できるようにすることも好適である。このようにしても上記と同様に、検査の際には隣り合う各半導体チップが電気的に分離されているので、検査の際に各半導体チップ１１が相互に干渉することがなく、良好に検査をすることができる。   On the other hand, when the semiconductor chips 11 are stacked by potting, it is necessary to penetrate and project electrodes so that the electrode pads 17 can be connected to the surface of the semiconductor chip 11 opposite to the electrode pads 17. In such a case, it is also preferable that the hole 25 is a side electrode 31 that penetrates as a hole penetrating to the tape 19, and the side electrode 31 can protrude by the thickness of the tape 19. Even in this way, as described above, since the adjacent semiconductor chips are electrically separated at the time of inspection, the semiconductor chips 11 do not interfere with each other at the time of inspection. Can do.

以上、半導体チップ１１の表面に電極パッド１７が形成される場合の側面電極３１の形成について説明したが、回路部１５への信号の入出力や電源の供給などを行う電極は、半導体チップ１１の表面ではなく、内部にダミー配線として構成される場合もある。このように内部に電極が形成される場合の側面電極３１の形成について図４を参照しながら説明する。図１から図３と同様の部位には同様の符号を付してその説明は省略する。   As described above, the formation of the side electrode 31 when the electrode pad 17 is formed on the surface of the semiconductor chip 11 has been described. However, an electrode for inputting / outputting a signal to the circuit unit 15 or supplying power is provided on the semiconductor chip 11. In some cases, it is configured as a dummy wiring inside rather than on the surface. The formation of the side electrode 31 when the electrode is formed inside will be described with reference to FIG. The same parts as those in FIGS. 1 to 3 are denoted by the same reference numerals, and the description thereof is omitted.

図４（ａ）に示すように、ダミー配線１８は半導体チップ１１の製造工程の中で、半導体チップ１１の内部に形成されている。このため、表面には電極パッド１７は形成されていない。ダミー配線１８は表面に形成された電極パッド１７と同様に、回路部１５から回路部１５の周縁にある絶縁部に延び、更に切断線２１を越えて切断領域２３まで延びている。先に図１で説明したと同様に、切断領域２３の幅Ｂよりも大きな穴２５を開けると、穴２５の内面には、ダミー配線１８の端面が露出する。この穴に上記の実施形態と同様に金属を充填して金属充填電極２７を形成した後、切断線２１に沿って切断する。切断によって切断領域２３が削り取られて、切断線２１に沿って側面電極３１が露出、形成される。各側面電極３１は半導体チップ１１の厚さの中間位置においてダミー配線１８と電気的に接続されている。そして、テープ１９に固定された状態で各半導体チップ１１の機能検査を行う。先の実施形態と同様、検査の際には隣り合う各半導体チップが電気的に分離されているので、検査の際に各半導体チップ１１相互に干渉することがなく、良好に検査をすることができる。   As shown in FIG. 4A, the dummy wiring 18 is formed inside the semiconductor chip 11 during the manufacturing process of the semiconductor chip 11. For this reason, the electrode pad 17 is not formed on the surface. Like the electrode pad 17 formed on the surface, the dummy wiring 18 extends from the circuit portion 15 to the insulating portion at the periphery of the circuit portion 15, and further extends to the cutting region 23 beyond the cutting line 21. As described above with reference to FIG. 1, when the hole 25 larger than the width B of the cutting region 23 is formed, the end surface of the dummy wiring 18 is exposed on the inner surface of the hole 25. This hole is filled with metal in the same manner as in the above embodiment to form the metal-filled electrode 27, and then cut along the cutting line 21. The cutting region 23 is scraped off by cutting, and the side electrode 31 is exposed and formed along the cutting line 21. Each side electrode 31 is electrically connected to the dummy wiring 18 at an intermediate position of the thickness of the semiconductor chip 11. Then, the function test of each semiconductor chip 11 is performed while being fixed to the tape 19. As in the previous embodiment, since the adjacent semiconductor chips are electrically separated during the inspection, the semiconductor chips 11 do not interfere with each other during the inspection and can be inspected satisfactorily. it can.

上記の実施形態においては、穴２５に金属を充填して金属充填電極２７を形成し、その金属充填電極２７を切断によって露出させて側面電極３１としているが、穴２５と金属充填電極２７の形成を行わずに側面電極３１を形成する実施形態について説明する。   In the above embodiment, the hole 25 is filled with metal to form the metal-filled electrode 27, and the metal-filled electrode 27 is exposed by cutting to form the side electrode 31, but the hole 25 and the metal-filled electrode 27 are formed. An embodiment in which the side electrode 31 is formed without performing the steps will be described.

図５に示すように、ウエハ上には先に述べた実施形態と同様に半導体チップ１１の回路部１５が形成され、その表面には電極パッド１７が形成されている。本実施形態では、このように形成されたウエハの各電極バッド１７にバンプ３３を形成する。各電極パッド１７は回路部１５から切断領域２３に延出して形成されており、各バンプ３３もその一端が切断線２１から切断領域２３に延出するような形状に構成する。隣接する電極パッド１７は電気的に分離されているが、各電極パッド１７が接近している場合には形成した隣り合うバンプ３３同士が接触し、この結果、隣り合う電極パッド１７相互が電気的に接続される。   As shown in FIG. 5, the circuit portion 15 of the semiconductor chip 11 is formed on the wafer as in the above-described embodiment, and the electrode pad 17 is formed on the surface thereof. In the present embodiment, bumps 33 are formed on each electrode pad 17 of the wafer thus formed. Each electrode pad 17 is formed so as to extend from the circuit unit 15 to the cutting region 23, and each bump 33 is also configured to have one end extending from the cutting line 21 to the cutting region 23. Adjacent electrode pads 17 are electrically separated. However, when the electrode pads 17 are close to each other, the formed adjacent bumps 33 come into contact with each other. As a result, the adjacent electrode pads 17 are electrically connected to each other. Connected to.

図５（ｂ）に示すように、各切断線２１に沿ってウエハを切断し、切断領域２３を取り除くことによって、隣り合う電極パッド１７相互の電気的接続が分離される。切断によって切断面に電極パッド１７及びバンプ３３の断面が露出する。この露出した各断面は側面電極３５を形成する。そして、バンプ３３又は側面電極３５にプロービング用のプロービングピンを接触させることによって隣り合う電極パッド１７の間の干渉を引き起こさずに半導体チップ１１の機能検査を実施することができる。   As shown in FIG. 5B, the electrical connection between the adjacent electrode pads 17 is separated by cutting the wafer along each cutting line 21 and removing the cutting region 23. By cutting, the cross sections of the electrode pad 17 and the bump 33 are exposed on the cut surface. Each exposed cross section forms a side electrode 35. Then, by bringing a probing pin for probing into contact with the bump 33 or the side electrode 35, the function test of the semiconductor chip 11 can be performed without causing interference between the adjacent electrode pads 17.

プロービングによる各半導体チップ１１の機能検査が終了したら、半導体チップ１１が分離されないように各半導体チップ１１をテープ１９に取り付けられたまま、次のダイボンディングなどの工程に送るように構成してもよい。   After the functional inspection of each semiconductor chip 11 by probing is completed, each semiconductor chip 11 may be sent to the next process such as die bonding while being attached to the tape 19 so that the semiconductor chip 11 is not separated. .

この実施形態は、簡便な工程でウエハの状態で側面電極３５を形成することができると共に、ウエハの状態でプロ-ビングによる機能検査を実施することができ、半導体の品質を確保することができるという効果を奏する。   In this embodiment, the side electrode 35 can be formed in a wafer state by a simple process, and a function inspection by probing can be performed in the wafer state, so that the quality of the semiconductor can be ensured. There is an effect.

以上、側面電極付半導体チップ１１０の形成について説明したが、以下、図面を参照しながら上記の側面電極付半導体チップ１１０を積層した３次元実装モジュールについて説明する。   The formation of the semiconductor chip 110 with side electrodes has been described above. Hereinafter, a three-dimensional mounting module in which the semiconductor chips 110 with side electrodes are stacked will be described with reference to the drawings.

図６に側面電極付半導体チップ１１０を積層した３次元実装モジュールの断面を示す。図６（ａ）は図１において説明した表面に電極パッド１７を持つ側面電極付半導体チップ１１０を積層して構成した３次元実装モジュールである。この３次元実装モジュールでは、各側面電極付半導体チップ１１０の間を絶縁性の接着剤４１によって接着、積層する。各側面電極付半導体チップ１１０を上記の接着剤４１によって接着した後、各側面電極３１の間をワイヤ４３によって接続することによって３次元実装モジュールを形成することができる。   FIG. 6 shows a cross section of a three-dimensional mounting module in which semiconductor chips 110 with side electrodes are stacked. FIG. 6A shows a three-dimensional mounting module in which the semiconductor chip 110 with side electrodes having the electrode pads 17 on the surface described in FIG. In this three-dimensional mounting module, the semiconductor chips 110 with side electrodes are bonded and laminated with an insulating adhesive 41. A three-dimensional mounting module can be formed by bonding the semiconductor chips 110 with side electrodes with the adhesive 41 and then connecting the side electrodes 31 with wires 43.

各側面電極３１の間をワイヤ４３によって接続しているので、動作時に側面電極付半導体チップ１１０相互に相対的な熱変位が発生しても、その変位差をボンディングされているワイヤ４３の変形によって吸収することができる。これによって、動作中の熱変形に対する耐力の大きな３次元実装モジュールを構成することができるという効果を奏する。   Since the side electrodes 31 are connected by the wires 43, even if relative thermal displacement occurs between the semiconductor chips 110 with side electrodes during operation, the difference in displacement is caused by the deformation of the bonded wires 43. Can be absorbed. As a result, there is an effect that it is possible to configure a three-dimensional mounting module having a high resistance to thermal deformation during operation.

図６（ｂ）は、図５で説明したバンプ３３と電極パッド１７の側面に露出した面を側面電極３５としたタイプの側面電極付半導体チップ１１０を、図６（ａ）と同様に絶縁性の接着剤４１によって接続したものである。図６（ａ）に示した３次元実装モジュールより、側面電極３５の面積が狭い点と、バンプ３３が側面電極付半導体チップ１１０の表面に突出している分だけ、積層モジュール全体の高さが高く、接着剤４１の厚さが厚くなっている以外は、上記の図６（ａ）に示す３次元実装モジュールと同様である。   FIG. 6B shows a semiconductor chip 110 with a side electrode of the type in which the surface exposed on the side surface of the bump 33 and the electrode pad 17 described in FIG. 5 is a side electrode 35, as in FIG. 6A. Are connected by an adhesive 41. Compared with the three-dimensional mounting module shown in FIG. 6A, the overall height of the laminated module is higher because the area of the side electrode 35 is smaller and the bump 33 protrudes from the surface of the semiconductor chip 110 with side electrode. The third embodiment is the same as the three-dimensional mounting module shown in FIG. 6A except that the adhesive 41 is thick.

上記の２種類の３次元実装モジュールの実施形態は各側面電極付半導体チップ１１０のサイズが略同一で、側面電極３１，３５も平面上略同一の位置に配置されているものであるが、複数の側面電極付半導体チップ１１０のサイズが同一で無い場合でも、各側面電極３１をワイヤ４３によって接続することによって、自由に３次元実装モジュールを構成することができる。   In the embodiment of the above two types of three-dimensional mounting modules, the size of each semiconductor chip 110 with side electrodes is substantially the same, and the side electrodes 31 and 35 are also arranged at substantially the same position on the plane. Even when the sizes of the semiconductor chips 110 with side electrodes are not the same, by connecting the side electrodes 31 with the wires 43, a three-dimensional mounting module can be freely configured.

図６（ｃ）は、３層に積層されている３次元実装モジュールの上層と下層の側面電極付半導体チップの大きさが、中間層の側面電極付半導体チップ１１０の大きさよりも小さくなっている例である。このように、各側面電極付半導体チップ１１０の側面電極の平面的な位置にずれがある場合でも、ワイヤボンディング装置はワイヤ４３を自由にボンディングすることができることから簡便に３次元実装モジュールを構成することができるという効果を奏する。特に、複数種類の機能を持ち、形状の異なる側面電極付半導体チップを３次元実装する場合に効果が大きい。図６（ｃ）に示した実施形態は、中間層が小さくなっている３層構造の場合を示したが、更に多層構造で、大きさが多様であってもかまわない。   In FIG. 6C, the size of the upper and lower side semiconductor chips with side electrodes of the three-dimensional mounting module stacked in three layers is smaller than the size of the semiconductor chip with side electrodes 110 in the intermediate layer. It is an example. Thus, even when there is a shift in the planar position of the side electrode of each semiconductor chip 110 with side electrode, the wire bonding apparatus can freely bond the wire 43, so that a three-dimensional mounting module is simply configured. There is an effect that can be. In particular, the effect is great when three-dimensionally mounting semiconductor chips with side electrodes having different types of functions and different shapes. In the embodiment shown in FIG. 6C, the case of a three-layer structure in which the intermediate layer is small is shown. However, the multilayer structure may have various sizes.

以下に、図７を参照しながら、側面電極付半導体チップ１１０を積層した積層体１３０の側面電極３１の間にワイヤボンディングを行うワイヤボンディング装置２００の構造及びボンディング方法について説明する。   Hereinafter, the structure and bonding method of the wire bonding apparatus 200 that performs wire bonding between the side electrodes 31 of the stacked body 130 in which the semiconductor chips with side electrodes 110 are stacked will be described with reference to FIG.

図７は上記のワイヤボンディング装置２００のボンディングステージ周りの構成を示している。図７（ａ）に示すように、ボンディングステージは吸着ステージ５５と押し付けステージ５９とコーナー保持部６７によって構成されている。そして、吸着ステージ５５と押し付けステージ５９との間に側面電極付半導体チップ１１０を積層した積層体１３０を挟み込み、コーナー保持部６７は積層体１３０のボンディング面と反対側の側面の各角部を側面電極に対するボンディングツールの接離方向にサポートする。吸着ステージ５５と押し付けステージ５９は、積層体１３０の積層方向に配置されている。図７に示した構成では、ボンディングツール５１は上下方向に移動し、積層体１３０は、吸着ステージ５５と押し付けステージ５９によって水平方向に保持されている。   FIG. 7 shows a configuration around the bonding stage of the wire bonding apparatus 200 described above. As shown in FIG. 7A, the bonding stage is constituted by a suction stage 55, a pressing stage 59, and a corner holding part 67. And the laminated body 130 which laminated | stacked the semiconductor chip 110 with a side electrode was pinched | interposed between the adsorption | suction stage 55 and the pressing stage 59, and the corner holding part 67 side-faces each corner | angular part of the side surface on the opposite side to the bonding surface of the laminated body 130. Supports the bonding tool in the direction of contact with the electrode. The suction stage 55 and the pressing stage 59 are arranged in the stacking direction of the stacked body 130. In the configuration shown in FIG. 7, the bonding tool 51 moves in the vertical direction, and the stacked body 130 is held in the horizontal direction by the suction stage 55 and the pressing stage 59.

吸着ステージ５５には、通常のボンディングステージと同様に真空吸着用の吸着穴５７が配設されており、積層体１３０をその表面に吸着固定することができるように構成されている。押し付けステージ５９はワイヤボンディング装置のフレームに押し付け方向に押し付けステージ５９を進退移動させる駆動部６１を有している。押し付けステージ５９はこの駆動部６１によって所定の面圧で積層体１３０を積層方向に吸着ステージ５５に押し付けて積層体１３０を押圧保持する。   The suction stage 55 is provided with a suction hole 57 for vacuum suction as in a normal bonding stage, and is configured so that the laminated body 130 can be sucked and fixed to the surface thereof. The pressing stage 59 has a drive unit 61 that moves the pressing stage 59 forward and backward in the pressing direction against the frame of the wire bonding apparatus. The pressing stage 59 presses and holds the stacked body 130 by pressing the stacked body 130 against the suction stage 55 in the stacking direction with a predetermined surface pressure by the driving unit 61.

吸着ステージ５５はワイヤボンディング装置に回転駆動部６３を有している。また、押し付けステージ５９の駆動部６１にも回転駆動機構が組み込まれている。回転駆動部６３は、ボンディングツール５１の接離方向が積層体１３０の側面電極３１の面に対して垂直となるように積層体１３０を回転させる。また、押し付けステージ５９の駆動部６１の回転駆動機構は回転駆動部６３の回転と協調して積層体１３０を回転させる。この回転動作によって、積層体１３０の４つの側面の各側面電極３１は順次ボンディングツール５１の接離方向と垂直となる。   The suction stage 55 has a rotation drive unit 63 in the wire bonding apparatus. In addition, a rotation drive mechanism is also incorporated in the drive unit 61 of the pressing stage 59. The rotation drive unit 63 rotates the stacked body 130 such that the contact / separation direction of the bonding tool 51 is perpendicular to the surface of the side electrode 31 of the stacked body 130. The rotation driving mechanism of the driving unit 61 of the pressing stage 59 rotates the stacked body 130 in cooperation with the rotation of the rotation driving unit 63. By this rotation operation, the side electrodes 31 on the four side surfaces of the stacked body 130 are sequentially perpendicular to the contact / separation direction of the bonding tool 51.

また、コーナー保持部６７はワイヤボンディング装置２００のフレームに設けられた直線駆動部６９によって、ボンディングツール５１の接離方向に移動する。吸着ステージ５５と押し付けステージ５９によって積層体１３０が回転して、そのボンディング対象側面電極の面がボンディングツール５１の接離方向と垂直方向になった後に、コーナー保持部６７は直線駆動部６９によって上昇し、積層体１３０のボンディング面対象側面と反対側の側面の各角部を側面電極に対するボンディングツールの接離方向に保持する。この後、ボンディングツール５１によって順次ワイヤ４３が接続されていく。コーナー保持部６７がなくともボンディングが行えるような場合には、コーナー保持部６７を備えていなくても良い。   Further, the corner holding part 67 is moved in the contact / separation direction of the bonding tool 51 by a linear drive part 69 provided on the frame of the wire bonding apparatus 200. After the stacked body 130 is rotated by the suction stage 55 and the pressing stage 59 and the surface of the side electrode to be bonded is in a direction perpendicular to the contact / separation direction of the bonding tool 51, the corner holding unit 67 is lifted by the linear drive unit 69. And each corner | angular part of the side surface on the opposite side to the bonding surface object side surface of the laminated body 130 is hold | maintained in the contact / separation direction of the bonding tool with respect to a side surface electrode. Thereafter, the wires 43 are sequentially connected by the bonding tool 51. In the case where bonding can be performed without the corner holding portion 67, the corner holding portion 67 may not be provided.

ワイヤボンディング装置２００は図示しないボンディングへッドを水平方向に移動させることによってボンディングツール５１の位置を自在に変更することができる。このため、上記の回転動作とボンディングへッドの水平動作とを協調させることによって、３次元に積層されている積層体１３０の任意の側面電極３１の面をボンディングツール５１の接離方向と垂直となるように移動させてワイヤ４３のボンディングをおこなうことができ、各側面電極付半導体チップ１１０の大きさ、側面電極３１の位置などにかかわらず、自由に配線を行うことができるという効果を奏する。   The wire bonding apparatus 200 can freely change the position of the bonding tool 51 by moving a bonding head (not shown) in the horizontal direction. For this reason, by coordinating the rotational operation and the horizontal operation of the bonding head, the surface of the arbitrary side electrode 31 of the laminated body 130 that is three-dimensionally stacked is perpendicular to the contact / separation direction of the bonding tool 51. The wire 43 can be bonded by being moved so that the wiring can be freely performed regardless of the size of the semiconductor chip 110 with the side electrode, the position of the side electrode 31, and the like. .

図７では、積層体１３０の各側面にワイヤ４３によって配線を行う実施形態を示したが、図８のようにワイヤ４３を３次元的に配線して３次元実装モジュールを形成することもできる。図８は一番上層の側面電極付半導体チップ１１０の側面の側面電極ｐにワイヤボンディングを行い、ボンディングツール５１を上昇させながら積層体１３０を回転させ、側面電極ｑの位置にボンディングツール５１の先端を移動させると共にボンディングツール５１の接離方向と側面電極ｑの面とが垂直となるようにした後、側面電極ｑにボンディングを行いワイヤ４３を接続する。以下、順次ｒ，ｓ，ｔと積層体１３０を回転させながらボンディングを行いワイヤ４３によって配線していく。このように、積層モジュールに３次元のワイヤ配線行って３次元実装モジュールを構成することができる。   Although FIG. 7 illustrates an embodiment in which wiring is performed on each side surface of the stacked body 130 with the wires 43, a three-dimensional mounting module can be formed by three-dimensionally wiring the wires 43 as illustrated in FIG. In FIG. 8, wire bonding is performed on the side electrode p on the side surface of the semiconductor chip 110 with the side electrode on the uppermost layer, and the stacked body 130 is rotated while the bonding tool 51 is raised, and the tip of the bonding tool 51 is positioned at the side electrode q. And the contact / separation direction of the bonding tool 51 and the surface of the side electrode q are perpendicular to each other, and then bonding is performed to the side electrode q to connect the wire 43. Thereafter, bonding is performed by sequentially rotating r, s, t and the laminated body 130 and wiring is performed by the wire 43. In this way, a three-dimensional mounting module can be configured by performing three-dimensional wire wiring on the laminated module.

図９は側面電極付半導体チップ１１０をポッティングによって複数積層して構成した積層体１４０を更に重ねてワイヤボンディング装置によって配線したものである。図９の（ａ）（ｂ）に示すように、各側面電極付半導体チップ１１０の側面電極３１は各半導体チップを上下に貫通する貫通電極として構成されており、この貫通電極相互の間に、例えば、金属フィラー入りの接着剤等を用いて、ポッティングによって各側面電極付半導体チップ１１０の側面電極の貫通部を電気的に接続して積層体１４０を構成する。このようにして構成された複数の積層体１４０を、接着剤４１によって接着積層し、その側面電極３１の間をワイヤ４３によって接続する。更に側面電極３１の接続の後、３次元積層モジュールをリードフレーム４７に接着して最上層の電極パッド１７とリードフレーム４７の電極とをワイヤ４３によって接続する。   FIG. 9 shows a stack 140 in which a plurality of stacked semiconductor chips 110 with side electrodes are stacked by potting and are further stacked and wired by a wire bonding apparatus. As shown in FIGS. 9A and 9B, the side electrode 31 of each semiconductor chip 110 with side electrodes is configured as a through electrode that vertically penetrates each semiconductor chip. Between the through electrodes, For example, the laminated body 140 is configured by electrically connecting the penetrating portions of the side electrodes of the semiconductor chips with side electrodes 110 by potting using an adhesive containing a metal filler. The plurality of laminated bodies 140 configured as described above are bonded and laminated by the adhesive 41, and the side electrodes 31 are connected by the wires 43. Further, after the side electrodes 31 are connected, the three-dimensional laminated module is bonded to the lead frame 47 and the uppermost electrode pad 17 and the electrode of the lead frame 47 are connected by the wire 43.

このようにワイヤボンディング装置２００を用いて側面電極３１にワイヤ４３を接続することによって、各側面電極付半導体チップ１１０の大きさ、側面電極３１の位置などにかかわらず、３次元積層モジュールに自由に配線を行うことができるという効果を奏する。   By connecting the wires 43 to the side electrodes 31 using the wire bonding apparatus 200 as described above, the three-dimensional stacked module can be freely connected regardless of the size of each semiconductor chip 110 with side electrodes, the position of the side electrodes 31, and the like. There is an effect that wiring can be performed.

本発明の実施形態における側面電極付半導体チップの製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the semiconductor chip with a side electrode in embodiment of this invention. 本発明の実施形態における側面電極付半導体チップの製造工程を平面的に示した説明図である。It is explanatory drawing which showed in plan the manufacturing process of the semiconductor chip with a side electrode in embodiment of this invention. 本発明の実施形態における側面電極付半導体チップの斜視図である。It is a perspective view of the semiconductor chip with a side electrode in the embodiment of the present invention. 本発明の他の実施形態における側面電極付半導体チップの製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the semiconductor chip with a side electrode in other embodiment of this invention. 本発明の他の実施形態における側面電極付半導体チップの製造工程を示す説明図である。It is explanatory drawing which shows the manufacturing process of the semiconductor chip with a side electrode in other embodiment of this invention. 本発明の実施形態における３次元積層モジュールの構成を示す説明図である。It is explanatory drawing which shows the structure of the three-dimensional lamination | stacking module in embodiment of this invention. 本発明の実施形態における３次元積層モジュールにワイヤボンディングを行うワイヤボンディング装置を示す図である。It is a figure which shows the wire bonding apparatus which wire-bonds to the three-dimensional lamination | stacking module in embodiment of this invention. 本発明の実施形態における３次元積層モジュールに３次元にワイヤ配線を行った３次元積層モジュールを示す説明図である。It is explanatory drawing which shows the three-dimensional lamination | stacking module which performed wire wiring three-dimensionally to the three-dimensional lamination | stacking module in embodiment of this invention. 本発明の実施形態における他の３次元積層モジュールに３次元にワイヤ配線を行った３次元積層モジュールを示す説明図である。It is explanatory drawing which shows the three-dimensional lamination | stacking module which performed wire wiring three-dimensionally to the other three-dimensional lamination | stacking module in embodiment of this invention.

符号の説明Explanation of symbols

１１ 半導体チップ、１３ 基板、１４ 回路領域、１５ 回路部、１７ 電極パッド、１９ テープ、２１ 切断線、２３ 切断領域、２５ 穴、２７ 金属充填電極、３１，３５ 側面電極、３３ バンプ、４１ 接着剤、４３ ワイヤ、４７ リードフレーム、５１ ボンディングツール、５３ ボンディングアーム、５５ 吸着ステージ、５７ 吸着穴、５９ 押し付けステージ、６１ 駆動部、６３ 回転駆動部、６７ コーナー保持部、６９ 直線駆動部、１１０ 側面電極付半導体チップ、１３０ 積層体、１４０ 積層体、２００ ワイヤボンディング装置、Ａ，Ｂ 幅、ｐ，ｑ，ｒ，ｓ，ｔ 側面電極。   DESCRIPTION OF SYMBOLS 11 Semiconductor chip, 13 Substrate, 14 Circuit area, 15 Circuit part, 17 Electrode pad, 19 Tape, 21 Cutting line, 23 Cutting area, 25 Hole, 27 Metal filling electrode, 31, 35 Side electrode, 33 Bump, 41 Adhesive , 43 Wire, 47 Lead frame, 51 Bonding tool, 53 Bonding arm, 55 Adsorption stage, 57 Adsorption hole, 59 Pressing stage, 61 Drive part, 63 Rotation drive part, 67 Corner holding part, 69 Linear drive part, 110 Side electrode Attached semiconductor chip, 130 laminated body, 140 laminated body, 200 wire bonding apparatus, A, B width, p, q, r, s, t side electrode.

Claims (11)

複数の回路領域が形成されている半導体ウエハを切断して製造する側面電極付半導体チップであって、
隣接する前記各回路領域に跨って配置され、前記各回路領域に電気的に接続される電極を形成し、前記電極形成の後に隣接する前記各回路領域の間にある切断線に沿って前記半導体ウエハを切断して前記半導体チップに側面電極を形成し、前記切断の後に各半導体チップをプロービングによって検査して製造すること
を特徴とする側面電極付半導体チップ。 A semiconductor chip with side electrodes manufactured by cutting a semiconductor wafer on which a plurality of circuit regions are formed,
The semiconductor is disposed across the adjacent circuit areas and electrically connected to the circuit areas, and the semiconductor is formed along a cutting line between the adjacent circuit areas after the electrode formation. A semiconductor chip with side electrodes, wherein the semiconductor chip is manufactured by cutting a wafer to form side electrodes on the semiconductor chip, and inspecting each semiconductor chip by probing after the cutting. 請求項１に記載の側面電極付半導体チップであって、前記電極は貫通電極であること
を特徴とする側面電極付半導体チップ。 The semiconductor chip with a side electrode according to claim 1, wherein the electrode is a through electrode. 請求項１に記載の側面電極付半導体チップであって、前記電極は回路領域に配置されたバンプであること
を特徴とする側面電極付半導体チップ。 2. The semiconductor chip with side electrodes according to claim 1, wherein the electrodes are bumps arranged in a circuit region. 3. 複数の回路領域が形成されている半導体ウエハの隣接する前記各回路領域に跨って配置され、前記各回路領域に電気的に接続される電極を形成し、前記電極形成の後に隣接する前記回路領域の間にある切断線に沿って前記半導体ウエハを切断して側面電極を形成し、前記切断の後にプロービングによって検査して製造する側面電極付半導体チップの前記各側面電極相互を電気的に接続して積層したこと
を特徴とする３次元実装モジュール。 The circuit regions that are arranged across the adjacent circuit regions of the semiconductor wafer on which a plurality of circuit regions are formed, are electrically connected to the circuit regions, and are adjacent after the electrode formation. The semiconductor wafer is cut along a cutting line between them to form side electrodes, and the side electrodes of the semiconductor chip with side electrodes manufactured by probing after the cutting are electrically connected to each other. A three-dimensional mounting module characterized by stacking. 請求項４に記載の３次元実装モジュールであって、
前記各側面電極相互をワイヤボンディング装置によって接続すること
を特徴とする３次元実装モジュール。 The three-dimensional mounting module according to claim 4,
The three-dimensional mounting module, wherein the side electrodes are connected to each other by a wire bonding apparatus. 複数の回路領域が形成されている半導体ウエハを切断して製造する側面電極付半導体チップの製造方法であって、
隣接する前記各回路領域に跨って配置され、前記各回路領域と電気的に接続される電極を形成する電極形成工程と、
前記電極形成工程の後に隣接する前記回路領域の間にある切断線に沿って前記半導体ウエハを切断して前記半導体チップに側面電極を形成する切断工程と、
前記切断工程の後に各半導体チップをプロービングによって検査する検査工程と、
を有することを特徴とする側面電極付半導体チップの製造方法。 A method of manufacturing a semiconductor chip with side electrodes for manufacturing by cutting a semiconductor wafer on which a plurality of circuit regions are formed,
An electrode forming step of forming an electrode that is arranged across the adjacent circuit regions and is electrically connected to the circuit regions;
A cutting step of cutting the semiconductor wafer along a cutting line between adjacent circuit regions after the electrode forming step to form side electrodes on the semiconductor chip;
An inspection step of inspecting each semiconductor chip by probing after the cutting step;
A method of manufacturing a semiconductor chip with a side electrode, comprising: 請求項６に記載の側面電極付半導体チップの製造方法であって、前記電極は貫通電極であること
を特徴とする側面電極付半導体チップの製造方法。 The method for manufacturing a semiconductor chip with side electrode according to claim 6, wherein the electrode is a through electrode. 請求項６に記載の側面電極付半導体チップの製造方法であって、前記電極は回路領域に配置されたバンプであること
を特徴とする側面電極付半導体チップの製造方法。 7. The method of manufacturing a semiconductor chip with side electrodes according to claim 6, wherein the electrodes are bumps arranged in a circuit region. 複数の回路領域が形成されている半導体ウエハの隣接する前記各回路領域に跨って配置され、前記各回路領域に電気的に接続される電極を形成し、前記電極形成の後に隣接する前記回路領域の間にある切断線に沿って前記半導体ウエハを切断して側面電極を形成し、前記切断の後にプロービングによって検査して製造する複数の側面電極付半導体チップを積層する積層工程と、
前記積層工程の後、前記各側面電極相互をワイヤボンディング装置によって電気的に接続するワイヤボンディング工程と、
を有することを特徴とする３次元実装モジュールの製造方法。 The circuit regions that are arranged across the adjacent circuit regions of the semiconductor wafer on which a plurality of circuit regions are formed, are electrically connected to the circuit regions, and are adjacent after the electrode formation. Laminating step of forming a side electrode by cutting the semiconductor wafer along a cutting line between, and laminating a plurality of semiconductor chips with side electrodes manufactured by inspecting and probing after the cutting,
After the lamination step, a wire bonding step of electrically connecting the side electrodes to each other by a wire bonding device;
A method for manufacturing a three-dimensional mounting module, comprising: 請求項９に記載の３次元実装モジュールの製造方法において、
前記ワイヤボンディング装置は、積層された前記半導体チップを積層方向に押圧してボンディングを行うこと、
を特徴とする３次元実装モジュールの製造方法。 In the manufacturing method of the three-dimensional mounting module according to claim 9,
The wire bonding apparatus performs bonding by pressing the stacked semiconductor chips in the stacking direction;
A method for manufacturing a three-dimensional mounting module. 請求項９又は１０に記載の３次元実装モジュールの製造方法において、
前記ワイヤボンディング装置は、積層された前記半導体チップの側面角部を前記側面電極に対するボンディングツールの接離方向に保持してボンディングを行うこと、
を特徴とする３次元実装モジュールの製造方法。 In the manufacturing method of the three-dimensional mounting module according to claim 9 or 10,
The wire bonding apparatus performs bonding by holding the side corners of the stacked semiconductor chips in the contact / separation direction of the bonding tool with respect to the side electrodes,
A method for manufacturing a three-dimensional mounting module.
JP2006316159A 2006-11-22 2006-11-22 Semiconductor chip with side electrode, manufacturing method therefor, and three-dimensional mount module with the semiconductor chip laminated therein Withdrawn JP2008130932A (en)

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