WO2008062767A1 - Semiconductor chip provided with side surface electrode, method for manufacturing the semiconductor chip, and three-dimensional mounting module wherein the semiconductor chip is laminated - Google Patents

Semiconductor chip provided with side surface electrode, method for manufacturing the semiconductor chip, and three-dimensional mounting module wherein the semiconductor chip is laminated

Info

Publication number
WO2008062767A1
WO2008062767A1 PCT/JP2007/072412 JP2007072412W WO2008062767A1 WO 2008062767 A1 WO2008062767 A1 WO 2008062767A1 JP 2007072412 W JP2007072412 W JP 2007072412W WO 2008062767 A1 WO2008062767 A1 WO 2008062767A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
semiconductor chip
electrode
side
cutting
manufacturing
Prior art date
Application number
PCT/JP2007/072412
Other languages
French (fr)
Japanese (ja)
Inventor
Toru Maeda
Original Assignee
Shinkawa Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02371Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06506Wire or wire-like electrical connections between devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06551Conductive connections on the side of the device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor

Abstract

A side surface electrode of a semiconductor chip having the side surface electrode is formed while ensuring qualities of the semiconductor chip by probing inspection in a wafer status. A metal filled electrode (27) is arranged over the adjacent circuit regions (14) and electrically connected to the circuit regions (14), a semiconductor wafer is cut along a cutting line (21) between the adjacent circuit regions (14) after forming the metal filled electrode (27) to form a side surface electrode (31) on a semiconductor chip. After the cutting, each semiconductor chip (11) is inspected by probing and the semiconductor chip having the side surface electrode is manufactured.

Description

Specification

Semiconductor chip and a manufacturing method thereof with the side electrodes and three-dimensional mounting module art formed by stacking the semiconductor chips

[0001] The present invention relates to a structure and the structure of its preparation and three-dimensional mounting module formed by stacking semiconductor chips with the side electrodes of the semiconductor chip with the side electrode.

BACKGROUND

In recent years, our! /, Te is the field of semiconductor devices, miniaturization of the semiconductor device, a plurality of semiconductor chips in a single package for the purpose of weight reduction, stacking the semiconductor chips in a three-dimensional things have been much development. Such a semiconductor device is, for example, JP-A-11- 135

As described in 711 JP, multi-chip package (MCP), or called multi-chip module (MCM), with mounting a semiconductor chip on a wiring board called interposer to connect the interposer to each other mutually, that the one character Yule laminated is used is, Ru.

[0003] However, in the conventional technique described in JP-A-11 135 711, but can easily be stacked substantially the same size of the semiconductor chip into a single semiconductor device, the semiconductive material chip was mounted on the interposer, further in order to ensure electrical connection between the interposer, it takes complicated manufacturing process.

[0004] Therefore, various methods for a single module to a product layer of the semiconductor chip in a three-dimensional without the use of auxiliary means of an interposer or the like has been proposed. For example, JP 2004 - In the 303 884 No. methods shown in Japanese, by performing three-dimensional mounting of the semiconductor chip is disclosed as follows.

[0005] In stage before the wafer is cut out to the semiconductor chip, drilled vertical holes to a position outside and name Ru insulating layer of the terminal electrodes of each chip, after filling the metal by molten plated method in the hole , cutting the semiconductor chip, polished to expose the metal filled in both sides of the semiconductor chip, thereby forming a through electrode penetrating the front surface and the back surface of the semiconductor chip. Next, this is exposed to the semiconductor chip surface (device forming surface)! /, Ru connects the electrode pad of the metal-filled portion and the semiconductor chip with the wiring, also to form an electrode on the back surface of the metal filled portions exposed surface . Then, the wiring and electrodes by superimposing these semiconductor chips by metal bonding, to connect all of the electrode pads mutually of the stacked semiconductor chips.

[0006] and forces, and, in this Patent 2004- 303884 Patent prior art described in Japanese, and a semiconductor chip electrode pad after cutting step and wafer thinning by polishing the wafer and through electrodes because having a complicated step such as attaching wires to be connected, there is a problem that the manufacturing process becomes complicated.

[0007] Further, JP-A-2001- 250906 discloses an end surface of the wiring electrode pads of the surface of the semiconductor chip to be stacked by exposing the semiconductor chip side and the connecting portion, between the pads end faces each other it is disclosed that connects performing drawing formation of the wiring pattern of the conductive metal paste by an inkjet method. According to this method, performed using the side of the semiconductor chip connection of the stacked semiconductor chips, be used for various connections in less wiring than the prior art described in JP 2004- 303884 Patent Gazette It can become. Furthermore, manufacturing process can be made simpler than the prior art described in JP-A-2004- 303884.

[0008] However, by the conventional technique described in JP 2001- 250906, since it connects the end faces of the pads formed on the front surface of the semiconductor chip, the conductive area is reduced electrical connection there has been a problem that it is difficult to ensure. Further, JP 2001- to 250,906 publication is about how the sides to expose the end surface side electrodes of the semiconductor chip is not the disclosure.

[0009] Further, JP-A-2004- 303884, JP-Kochikara from the electrode pads of the semiconductor chip surface on chip periphery, continuously dropped a liquid containing conductive fine particles by the connexion inkjet method, the semiconductor chip surface how to form a terminal for continuously until the chip side surface is disclosed from the electrode pad. Then, by this method, the boundary position or between the silicon emission substrate and the insulating layer on the side surfaces of the semiconductor chip, the terminal is formed than to the upper, the side electrodes are formed.

[0010] and power, and, the JP 2004- side electrodes described in 303884 discloses the formation depending on rewiring side electrodes from respective electrode surfaces of the semiconductor chips has been completed disconnect from the wafer since it is intended to, semiconductor manufacturing Les, there is a problem that the number of steps in the so-called post-process would one of many.

[0011] On the other hand, a method of forming a side electrode in the semiconductor chip in the wafer state is described in JP-A-6-5 665 JP. This forms a hole for the electrode formed on the line for the semiconductor chip cutting of the wafer, after forming the electrode portions in the hole, forming a semiconductor chip by cutting the cutting line formed in the electrode portions it is a method of. Here, holes for electrode formation wet process or the like wet etching, is more formed dry process such as dry etching, a small hole than the size hole in which fits in the electrode formation region. Then, sputter or vacuum deposition on the inner surface of the hole, after depositing an electrode material by etching or the like, and cut according to the wafer cutting line is also to form an electrode on the side surfaces of the semiconductor chip.

[0012] However, the method of forming the side electrodes described in Japanese Patent Laid-Open No. 6 5665, although it is possible to form the side electrodes in the state of the wafer, common across each semiconductor chip adjacent on the wafer and the electrode forming, cutting the common electrode, since the forming side electrodes on the semiconductor chip can not be inspected by a professional one Bing of each semiconductor chip in a state of the wafer, and completed there has been a problem that it is difficult to maintain the quality of the semiconductor chip.

[0013] For example, as described in JP-A-6 151 535, in the production of semiconductor chips, prior to forming by cutting each semiconductor chip from the wafer in order to ensure quality, on the wafer performing the inspection by a professional one Bing is generally performed. In recent years, as described in JP-A-6- one hundred fifty-one thousand five hundred and thirty-five, provided a common electrode extending over the semiconductor chip meet adjacent to the cutting region on the cutting line of the wafer, against the pro one Bingupin to the common electrode force technique for professional one Bing inspection have been proposed S, the electrode pads adjacent the semi conductor chip adjacent, for example, as such one of the other in the signal electrode is one Do a power electrode, and the different terminal If the going on in many cases. Therefore, can be carried out pro one Bing inspection Te cowpea to the common electrode is relatively simple as it is designed for a wafer so that the semiconductor chip electrode pads of adjacent on the wafer is formed as the same terminal limited to the case of such circuits pattern.

[0014] Accordingly, in the form how the side electrodes of the semiconductor chip described in Japanese Patent Laid-Open No. 6 5665, can not be sufficiently inspected by a professional one Bing of each semiconductor chip in a state of the wafer, the semiconductor there has been a problem that it is difficult to ensure the quality of the chip.

[0015] As described above, in the conventional technique described in JP-A-11 135 711, each half conductor chip requires a complicated manufacturing process in order to three-dimensional packaging from and mounted on the interposer, JP 2004- the 303,884 No. prior art described in Japanese because it has a complicated step such as attaching the wiring to connect the electrode pads of the semiconductor chip and the through electrodes after cutting the process or wafer thinning by polishing the wafer , there is a problem that the manufacturing process becomes complicated, formed by rewiring in other methods described in JP-a-2004- 303884, the side electrodes from respective electrode surfaces of the semiconductor chips has been completed separately from the wafer since it is intended to, semiconductor manufacturing Les, there is a problem that connexion man-hours are many in the so-called post-process Mau, side electrodes of the semiconductor chip described in Japanese Patent Laid-Open No. 6- 5665 In the formation method, it is difficult to perform the sufficient inspection by a professional one Bing of each semiconductor chip in a state of the wafer, a problem that it is difficult to ensure the quality of the semiconductor chip has been made.

[0016] Thus, in the prior art, there is a problem that it is impossible to form the side electrodes while ensuring the quality of the semiconductor chip by a professional one probing test in a wafer state.

[0017] The present invention aims to provide a semiconductor chip which has a side electrode is formed while maintaining the quality of professional one probing test in a wafer state.

Disclosure of the Invention

[0018] The semiconductor chip with the side electrode of the present invention is a semiconductor chip with the side electrode be manufactured by cutting the semiconductor wafer in which a plurality of circuit regions are formed, it is disposed across the respective circuit areas adjacent the electrodes are electrically connected is formed in each circuit area, the semiconductor chip along the cutting line to cut the semiconductor © E c located between the respective circuit regions adjacent after the electrode formation forming a side electrode, characterized in that to produce examines each semiconductor chip by professional one Bing after the cutting. Further, the side surface electrode semiconductor chip with the present invention, the electrode is to be a through-electrode, even to Ru suitable der as, the electrode is to be a bump that is disposed in the circuit region, it is also preferable.

[0019] 3-dimensional mounting module of the present invention, electrode to which the adjacent semiconductor © E c in which a plurality of circuit regions are formed arranged across each circuit region is electrically connected to the respective circuit areas forming a said adjacent after electrode formation along the cutting line located between the circuit region cutting the semiconductor wafer to form the side electrodes, prepared were checked by a professional one Bing after the cutting surface the stacked and electrically connects the respective side electrodes cross the semiconductor chip with the electrode, characterized by. Also, by connecting the by the respective side electrodes cross the wire catcher bonding apparatus, it is also preferable.

[0020] The method for producing a semiconductor chip with the side electrode of the present invention is a manufacturing method of a side electrode with a semiconductor chip prepared by cutting the semiconductor wafer in which a plurality of circuit regions are formed

Is arranged across the respective circuit region adjacent an electrode forming step of forming the respective circuit region electrically connected to the Ru electrode is between the circuit area adjacent after the electrode forming step cutting and characterized in that it comprises a cutting step of forming a side surface electrode on the semiconductor chip by cutting the semiconductor wafer along a line, and an inspection step of inspecting a semiconductor chips by professional one Bing after the cutting step to. In the method for manufacturing a semiconductor chip with the side electrode of the present invention, the electrode is to be a through-electrode, also to be suitable as, in that the electrode is a bump disposed on the circuit region, is also suitable as .

[0021] The method for producing a three-dimensional mounting module of the present invention, the adjacent semiconductor wafer in which a plurality of circuit regions are formed arranged across each circuit region, the being in electrical connecting each circuit region that the electrode is formed, the adjacent following electrode formed along the cutting line located between the circuit area by cutting the semiconductor wafer to form the side electrodes, produced examined by professional one Bing after the cutting a laminating step of laminating a plurality of side semiconductor chip with electrodes, after the lamination step, and having a wire bonding step of electrically connecting by the respective side electrodes cross wire bonding equipment. Further, in the three-dimensional mounting module manufacturing method of the present invention, the wire bonding apparatus, to perform the bonding by pressing the stacked semiconductor chip in the stacking direction, also to be suitable as, stacked above the semiconductor performing the bonding holds the contact and separation direction of the bonding tool against a side corner of the chip to the side electrodes, it is also good suitable as.

[0022] The present invention has an effect that it is possible to provide a semiconductor chip which has a side electrode is formed while maintaining the quality of professional one probing test in a wafer state.

BRIEF DESCRIPTION OF THE DRAWINGS

[1] is an explanatory view showing a manufacturing step of the semiconductor chip with the side electrodes in the embodiment of the present invention.

FIG. 2 is an explanatory view showing in plan the manufacturing process of the semiconductor chip with the side electrodes in the embodiment of the present invention.

3 is a perspective view of a semiconductor chip with a side electrode in the embodiment of the present invention.

FIG. 4 is an explanatory view showing a manufacturing step of the semiconductor chip with the side electrodes according to another embodiment of the present invention.

FIG. 5 is an explanatory view showing a manufacturing step of the semiconductor chip with the side electrodes according to another embodiment of the present invention.

[Figure 6A] explanatory view showing a configuration of a three-dimensional stack module in the embodiment of the present invention

[Figure 6B] explanatory view showing a configuration of a three-dimensional stack module in the embodiment of the present invention

[Figure 6C] explanatory view showing a configuration of a three-dimensional stack module in the embodiment of the present invention

[FIG 7A] is a diagram showing a wire bonding apparatus for performing wire bonding to the three-dimensional stack module in the embodiment of the present invention.

It is a [FIG 7B] explanatory diagram showing a side of the wire bonding apparatus for performing Waiyabon Deingu the three-dimensional stack module in the embodiment of the present invention shown in Figure 7A.

[FIG 8A] is an explanatory diagram of the three-dimensional wire wiring three-dimensional stack module in the embodiment shown a row ivy three-dimensional stack module of the present invention.

Is a [FIG 8B] explanatory diagram showing a three-dimensional side surface of the stacked module was Wa I catcher wiring to the three-dimensional three-dimensional stack module in the embodiment of the present invention shown in Figure 8A.

9 is an explanatory view showing a three-dimensional stack module performing the wire wiring 3D to other three-dimensional stack module in the embodiment of the present invention.

With reference to the best mode [0024] drawings for carrying out the invention will be described the preferred embodiments of the present invention. With reference to FIGS. 1 and 2 will be described a manufacturing process and structure of the semiconductor chip with the side electrode. 1 shows a manufacturing process and structure of the semiconductor chip as seen from the cross section of the wafer, FIG. 2 shows a manufacturing process and structure of the semiconductor chip as seen from the direction of the plane of the wafer.

[0025] FIG. 1 (a), as shown in FIG. 2 (a), that has been formed a plurality of semiconductor chips 11 in the wafer. The substrate 13 surface side of the wafer of the semiconductor chip 11, the insulating portion formed in the peripheral circuit portion 15 and the circuit portion 15 electronic circuits are formed, the input-output there have signal to the circuit portion 15 power supply electrode pads 17 for such a supply is formed. As shown in FIGS. 1 and 2, the insulating portion including the electrode pads 17 of the circuit section 15 and its periphery to form a circuit region 14 having a width A. Further, between the circuit parts 15, the cutting line 21 divides each of the semiconductor chips 11 by cutting the wafer is placed. Since cleavage of the wafer is performed by diamond cutter or the like having a finite blade width, wafer only blade width of the diamond cutter when cutting the wafer is cut away. Region of width B between the cutting lines 21 which form the extension of each of the semiconductor chip 11, a cutting area 23 scraped by the cutting. It said electrode pad 17 partially that is formed to extend in the cutting region 23 from the circuit region 14. Further, the surface opposite to the circuit portion 15 of the substrate 13 of the wafer is adhered tape 19 of insulating! /, Ru. Tape 19 upon cutting the substrate 13 of the wafer to the semiconductor chip 11, in which the semiconductor chip 11 is to separate Shinare, as.

[0026] As shown in FIG. 1 (b), to form the circuit section 15 and the etching in the cutting area 23 of the wafer and the electrode pads 17 are formed, the laser processing, the hole 25 by plasma processing or drill or the like. Hole 25 is provided at a position around the intersection of the center line and the center line of the perpendicular to the cutting line 21 of each electrode pad 17 of the cutting area 23 between the semiconductor chip 11, the diameter of the cutting region 23 It has a larger diameter than. Therefore, when the hole 25 is formed on the wafer, the inner surface of the hole 25 to expose the end surfaces of the electrode pads 17 extend to the cutting region 23 from the circuit region 14. Further, in the present embodiment, the depth of the hole 25 in the depth from the surface to the substrate 13, a depth not reaching the tape 19. This is the depth of the holes for the height of the electrode formed on a side surface, Arebayore height of the side electrode at the height that can be connected by a method such as wire bonding, because. [0027] As shown in FIG. 1 (c), after drilling, plated in the interior of the bore 25, and a chemical vapor fusing method (CVD) by plasma or the like, resistance heating, electron beam, high frequency induction method such as a laser in embedding a metal by heating vapor deposition physical vapor deposition (PVD) and the like. Metals used superior metallic copper or silver conductive. Metal buried in a hole in a cylindrical shape in close contact with the end face of the electrode pads 17 exposed on the inner surface of the hole 25 to form a metal-filled electrode 27 is electrically connected to the electrode pads 17. At this time, the electrode pads 17 mutually in a position respectively opposite has been found provided on the semiconductor chip 11 metal-filled electrode 27 is next Gotsu also electrically connected. Looking at this state of the plane of the wafer, as shown in FIG. 2 (b), a metal-filled electrode 27 et provided across the circuit region 14 including the electrode pads 17 provided on the semiconductor chip 11 you adjacent It is, is connected to each of the electrode pads 17! /, Ru state and made me! /, Ru.

[0028] Next, as shown in FIG. 1 (d), by cutting means such as a diamond cutter, to cut the wafer along the cutting fountain 2 1. Since being narrower summer than the diameter of the width B of the metal-filled electrode 27 embedded in the hole 25 of the cutting area 23 scraped by the cutting by the cutting, electrically to each electrode pad 17 along each cutting line 21 side electrode 31 connected are exposed. In this cutting, so that each semiconductor chip 11 is not separated, only the cut portion of the substrate 13 that is configured of the semiconductor chip 11, to the portion of the tape 19 is not cut. By doing so, it is possible to keep the semiconductor chip 11 on the wafer together state, by a metal-filled electrode 27 which connects the electrode pads 17 mutually adjacent cutting area 23 to the semiconductor chip 11 it can be divided into parts to which they belong. Tape 19 from being a insulation resistance, by cleavage of the electrode pads 17 of the adjacent semiconductor chip 11 is to be electrically isolated. Looking at this state of the plane of the wafer is as shown in FIG. 2 (c).

[0029] In this state, the semiconductor chip 11 are together by tape 19, and each electrode pad 17 facing the adjacent Ri fit semiconductor chip 11 is summer on purpose like are electrically isolated from one another . Perform function test of the semiconductor professionally one Bing in this state. Function tests inspected to verify the function to input signal by contacting a probe for inspection to the electrode pad 17 or the side electrode 31 of the semiconductor chip 11 (KGD). Adjacent semiconductor chip 11 from being electrically isolated, an effect that can be performed well inspection of the semiconductor chip 1 1 without interfering with each other. Then, it intends fi and markings on the semiconductor chip 1 1 becomes defective result of the test.

[0030] When the function test is completed, as shown in FIG. 1 (e), the semiconductor chip 1 1 are separated from the tape 19, the side surface electrode 31 is the semiconductor chip 1 1 aspect the formed side electrode with half the conductors chip 1 10. As shown in FIG. 3, the semiconductor chip 1 1 0 with the side surface electrodes The preparation is formed with part cylindrical through electrodes on each side of the chip, taken off the cross section of the through electrodes and the side electrodes 31 there. Each side electrode 31 is formed on the insulating portion in the peripheral circuit portion 15 of each of the semiconductor chips 1 1, functions as an electrically isolated electrode, respectively.

[0031] described above, in the present embodiment, Ki out to form the so-called pre-process of a semiconductor manufacturing process side electrode 31 because Ru can form side electrodes 31 in the state of the wafer, the semiconductor chip mounting step the addition to the advantage of can be simplified after a process. Moreover, the effect of the side electrode 31 from being able to the semiconductor mounting in a subsequent step the quality by professional one probing function test in the wafer state after securing, it is possible to improve the quality and yield of the semiconductor products achieve the.

[0032] In the present embodiment, the holes 25 Waiyabon the height side electrodes 31 mutually side electrode 31 formed on the side surface of the force semiconductors chips 1 1 described in the same thickness as the thickness of the substrate 13 of the wafer Deingu as a depth of about Nag example half the same depth and the substrate 13 thickness as long as the height that can be connected by such, it may be so that to form a half of the side surface electrodes of the thickness of the substrate 13. In this case, since the peripheral edge portion of the circuit portion 15 of the substrate 13 are formed an insulating region, also cut along the cutting line 21 to cut the equivalent to the thickness the thickness of the substrate 13 必 short Nag hole 25 it may be cut deeper than the depth of the metal-filled electrode 27 formed. If cutting up to this depth, the semiconductor chip 1 1 adjacent is because are electrically isolated. After electrically separating the respective semiconductors chips 1 1 adjacent to each other to form a side electrode 31 by half the height of the cut, such as this (half cut), by the same manner as described above, each half implementing the function test of the conductors chip 1 1. Again, each of the semiconductor switch-up adjacent to the time of inspection since it is electrically isolated, each of the semiconductor chips 1 1 during testing that forces S without interfering with each other, to better inspect leave on the child and force S. [0033] On the other hand, when going by stacking semiconductor chips 11 by potting, necessary to the electrodes through, is projected to be able to connect the electrode pads 17 of the semiconductor chip 11 and the surface opposite to the electrode pad 17 there is. In these cases, the hole 25 is a side electrode 31 that penetrates a hole that penetrates to the tape 19, it is also preferable that the thickness of only the side electrode 31 of the tape 19 to so that can protrude. Like the above in this manner, since the semiconductor chips are electrically isolated adjacent to the time of inspection, Nag that each semiconductor chip 11 from interfering with each other during the inspection the better inspection can do.

[0034] Having described the formation of side electrodes 31 when the electrode pads 17 on the surface of the semiconductor chip 11 is formed, electrodes for performing such signal input and output and power supply to the circuit part 15, when configured as a dummy wiring within the nag on the surface of the semiconductor chip 11 Ru mower. Thus Figure 4 will be described with refer for the formation of the side electrode 31 when internal electrodes are formed. As described with the same reference numerals are given to the same portions as FIGS. 1-3 will be omitted.

[0035] As shown in FIG. 4 (a), the dummy wiring 18 in the manufacturing process of the semiconductor chip 11, it is formed inside the semiconductor chip 11. Therefore, the electrode pads 17 on the surface is not formed. The dummy wire 18, like the electrode pads 17 formed on the surface, extends from the circuit part 15 extending in the insulating portion in the peripheral edge of the circuit portion 15, to the cutting area 23 further beyond the cut line 21. As shown in FIG. 4 (b), in the same manner as described in FIG. 1 above, it opened the large hole 25 than the width B of the cutting area 23, on the inner surface of the hole 25, the end face of the dummy wiring 18 is exposed to. As shown in FIG. 4 (c), after filling the metal as in the above embodiment to form a metal-filled electrode 2 7 into the hole, as shown in FIG. 4 (d), along the section line 21 to cut Te. Is shaved off disconnect area 23 by the cutting, the side electrode 31 exposed, is formed along the cutting line 21. Each side electrode 31 is dummy wire 18 and electrically connected at the intermediate position of the thickness of the semiconductor chip 11. Then, the function test of the semiconductor chip 11 in a state of being fixed to the tape 19. As in the previous embodiment, since each semiconductor chip adjacent to the time of inspection are electrically separated, it is possible to interfere with the semiconductor chips 11 to each other during the inspection the better inspection Nag .

[0036] above in the embodiment, by filling a metal into the hole 25 to form a metal-filled electrode 27, the metal filling force hole 25 which the electrode 27 is exposed by the cleavage has a side surface electrode 31 and the metal-filled electrode 27 It will be described embodiments for forming the side electrode 31 without the formation of.

[0037] As shown in FIG. 5 (a), is on a wafer similar to the embodiment previously described circuit portion 15 of the semiconductor chip 11 is formed, the electrode pad 17 is formed on the surface thereof. In this embodiment shaped condition, to form the bumps 33 on the electrodes Bad 17 thus formed wafer. Each electrodes pads 17 are formed to extend in the cutting region 23 from the circuit portion 15, the bump 33 is also configured in a shape such that one end extends to the cutting region 23 from the cutting line 21. Power electrode pads 17 adjacent are electrically isolated S, and approaching the electrode pads 17 when the bumps 33 contact each other adjacent the formation to have, as a result, the electrode pads 17 mutually adjacent electric They are connected to each other.

[0038] As shown in FIG. 5 (b), cutting the wafer along each cutting line 21, by dividing Kukoto take cutting region 23, the electrical connection between adjacent electrode pads 17 mutually are separated. Section of the electrode pads 17 and the bumps 33 are exposed on the cut surface by the cutting. Each cross section the exposed forms the side surface electrode 35. Then, it is possible to implement the function test of the semiconductor chip 11 without causing interference between the electrode pads 17 adjacent by contacting the pro one Bingupin for professional one Bing bump 33 or the side electrode 35.

[0039] When the function test of the semiconductor chip 11 by a professional one Bing is completed, each semiconductor chip 11 as a semiconductor chip 11 are not separated remain attached to the tape 19, to send the process such as following die bonding configuration may be.

[0040] This embodiment makes it possible to form the side electrodes 35 in the state of the wafer by a simple process, a professional in the state of the wafer - can be performed function test by Bing, ensure the quality of semi-conductor an effect that can be.

[0041] Having described the formation of the side electrodes with the semiconductor chip 110, or less, while refer to the drawings describes the three-dimensional mounting module formed by stacking semiconductor chips 110 with the above aspects electrode.

[0042] indicates a 3-dimensional mounting module section formed by laminating the side electrodes with the semiconductor chip 110 in Figure 6C from Figure 6A. Figure 6A is a three-dimensional mounting module formed by laminating the side electrodes with the semiconductor chip 110 with the electrode pads 17 on the surface described in FIG. In the three-dimensional implementation module, by between the semiconductor chip 110 with the side electrodes to the adhesive 41 of insulating connexion adhesive, laminated. After the semiconductor chip 110 with each side electrode is contacting applied by adhesive 41 described above, can be between the side electrodes 31 to form a three-dimensional mounting module by connecting the wire 43.

[0043] This three-dimensional mounting module, since between the respective side electrodes 31 are connected by wires 43, even if the relative thermal displacement occurs in the semiconductor chip 110 cross with the side electrode during operation, the displacement difference can be absorbed by the bonding has been that the deformation of the wire 43. Yotsute thereto and able force S constitute a large three-dimensional mounting module resistance to thermal deformation during operation! / It achieves the cormorants effect.

[0044] Figure 6B, a bump 33 and the type of side electrodes with semiconductor chip 110 and the exposed surface was the side surface electrode 35 on the side surfaces of the electrode pads 17 described in FIG. 5, as in FIG. 6A insulating adhesive 4 which are connected by one. From three-dimensional mounting module shown in FIG. 6A, a point narrow area of ​​the side electrodes 35, bumps 33 min that protrude to the surface side electrode with the semiconductor chip 110 only, high instrument adhesion height of the entire stacked modules except the thickness of the material 41 is thick summer is the same as the three-dimensional mounting module shown in the above FIG. 6A.

[0045] Embodiments of the above two kinds of three-dimensional mounting module is substantially the same size of the semiconductor chip 1 10 with each side electrodes, the side electrodes 31, 35 is also one that is located in a plane first paragraphs omitted same position even if the size of a force S, the semiconductor chip 110 with a plurality of side electrodes is not identical, each side electrode 31 by connecting the wires 43, can be configured freely three-dimensional mounting module.

[0046] FIG. 6C, the size of the semiconductor chip with the upper layer and the lower layer side electrode of the three-dimensional mounting module are stacked in three layers, smaller than the size of the side electrodes with the semiconductor chip 110 of the intermediate layer Kunatsute it is an example you are. Thus, even if there is a shift in the flat surface position of the side electrodes of the semiconductor chip 110 with the side electrodes, a simple three-dimensional mounting module since the wire bonding apparatus capable of freely Bonn Deingu the wire 43 an effect that Ru can be configured. In particular, having a plurality of types of functions, a large effect in the case of three-dimensional implement different with side electrodes semiconductors tip shapes. The embodiment shown in FIG. 6C, the force shows the case of a three-layer structure intermediate layer is summer small S, further a multilayer structure, it may be varied sizes.

[0047] Hereinafter, with reference to FIGS. 7A and 7B, the structure and bonding method of a wire bonding device 200 performs a wire bonding between the side electrode 31 of the laminated body 130 formed by laminating a semiconductor chip 110 with the side electrode explain.

[0048] Figures 7A and 7B show the structure around the bonding stage of the wire bonding device 200. As shown in FIG. 7A, a bonding stage is constituted by the stage 59 and the corner holding portion 67 pressed against the suction stage 55. Then, the side surface of the semiconductor chip 110 sandwich the product Sotai 130 laminated with electrodes, corner holding portions 67 each corner of the side surface opposite to the bonding surface of the laminate 130 between the stage 59 pressing the suction stearyl over di 55 part of the support to the contact and separation direction of the bonding tool with respect to the side electrode. Stage 59 pressing the suction stage 55, that are arranged in the stacking direction of the stacked body 130. In the configuration shown in FIGS. 7A and 7B, the bonding tool 51 is moved in the vertical direction, the laminated body 130 is held horizontally by the stage 59 pressing the suction stage 55.

The [0049] adsorption stage 55 is suction holes 57 for vacuum suction as with conventional bonding stage is arranged, and is configured to adsorb fixing the laminate 130 on the surface thereof. Pressing stage 59 has a driving portion 61 for advancing and retracting the stage 59 pressed against the pressing way towards the frame of the wire bonding apparatus. Pressing stage 59 presses holds a stack 130 against the suction stage 55 the laminate 130 at a predetermined surface pressure by the drive unit 61 in the stacking direction.

[0050] suction stage 55 has a rotary drive unit 63 to the wire bonding apparatus. In addition, the press and with stage 59 the rotation drive mechanism to the driving section 61 of is incorporated! /, Ru. Rotation driving unit 63, contact and separation direction of the bonding tool 51 rotates the stack 130 so as to be perpendicular to the plane of the side electrode 31 of the stack 130. The rotation driving mechanism of the driving unit 61 of the pressing stage 59 rotates the stack 130 in coordination with the rotation of the rotary drive unit 63. This rotation operation, each side electrode 31 of the four sides of the laminated body 130 is sequentially separable and vertical bonding tool 51. [0051] Moreover, by the corner holding portion 67 is a straight line driving section 69 provided on the frame of the wire bonding apparatus 200, it is moved to the contact and separation direction of the bonding tool 51. Rotates and laminate 130 by a stage 59 pressing the suction stage 55, after the surface of the bonding object side surface electrode becomes separable and vertical directions of the bonding tool 51, the corner holding portion 67 linear drives 69 elevated, to hold the corners of the opposite side to the bonding surface object side surface of the stacked body 130 in the contact and separation direction of the bonding tool with respect to the side electrode. Thereafter, it is sequentially wire 43 is connected by the bonding tool 51. Even without co over Na one holding portion 67 in the case that can be performed bonding may not be provided with the corner holding portion 67.

[0052] wire bonding apparatus 200 can be freely changed the position of the bonding tool 51 by moving the bonding head (not shown) in the horizontal direction. For this reason, by coordinating the horizontal operation of the rotary operation and bonding head, any surface of the bonding tool 5 the first contact and separation direction perpendicular side electrode 31 of the laminated body 130 are stacked in three dimensions it is moved so that it is possible to perform the bonding wire 43 brings the size of the semiconductor chip 110 with the side electrodes, regardless of such a position of the side electrode 31, an effect that can be performed freely wiring .

[0053] In Figure 7A and 7B, there is shown an implementation type condition for performing wired by wires 43 on each side of the laminated body 130, and connecting wires 43 three-dimensionally as shown in FIGS. 8A and 8B it is also possible to form a three-dimensional implementation module. 8A and 8B rotate the stack 130 while increasing the line! / ,, bonding tool 51 to the wire bonding to the side electrode p of the side surface of the most upper side electrode with semiconductors chip 110, the side surface electrode q after the position moves the tip of the bonding Tsu Lumpur 51 and the plane of the contact and separation direction and the side electrode q of the bonding tool 51 was set to be perpendicular to connect the wire 43 performs the bonding to the side electrode q. Hereinafter, sequential r, s, continue to by connexion to wire 43 performs bonding while rotating the stacked body 130 and t. Thus, it is possible to construct a three-dimensional mounting module performs three-dimensional wire wiring in the multilayer module.

[0054] FIG. 9 is obtained by the wiring by further overlaid wire bonder laminate 140 constituted by stacking a plurality of side electrodes with the semiconductor chip 110 by potting, (c) in FIG. 9 shows a side view of the whole , shown in FIG. 9 (a) and (b) illustrates an enlarged portion of the side electrode 31 of the stack 140 shown in (c) of FIG. As shown in (a) (b) of FIG. 9, the side electrode 31 of the semiconductor chip 110 with each side electrode is configured as a through electrode penetrating the semiconductor chips vertically, between the through electrodes mutually , for example, a metal filler-containing adhesive or the like, and forms an electrical connection to the laminate 140 through portions of the side electrodes of the semiconductor chip 110 with each side electrodes by potting. The thus more product Sotai 140 that is configured to adhesively laminated with an adhesive 41, a connection between the side surface electrode 31 Te wire 43 Niyotsu. After a further connection of the side surface electrode 31, a by bonding a three-dimensional stack module to the lead frame 4 7 and the uppermost electrode pad 17 and the electrode of the lead frame 47 are connected by wires 43.

By connecting the wire 43 to the side electrode 31 in this manner using the wire bonding apparatus 200, the size of the semiconductor chip 110 with the side electrodes, regardless of such a position of the side electrode 31, free to three-dimensional stack module Sosu the effect that the wiring can be carried out

Claims

The scope of the claims
[1] a plurality of circuit regions are formed!, A semiconductor chip with the side electrode be manufactured by cutting the semiconductor wafer Ru,
Is disposed across the respective circuit regions adjacent said forming an electrode electrically connected to the circuit region, along said cutting lines located between each circuit region adjacent after the electrode forming semiconductor the semiconductor chip side electrodes formed on the front SL cutting the semiconductor chip with the side electrodes, characterized in that to produce examines each semiconductor chip by professional one Bing after cutting the wafer.
[2] A side semiconductor chip with electrode according to claim 1, said electrode is a through electrode
The semiconductor chip with the side electrodes, characterized in.
[3] It is a side semiconductor chip with electrode according to claim 1, wherein the electrode is a bump that is placed on the circuit region
The semiconductor chip with the side electrodes, characterized in.
[4] a plurality of circuit regions are formed! /, Is connexion arranged straddled on each circuit region adjacent the semiconductor wafer Ru, wherein forming an electrode that is electrically connected to the circuit region, the electrode forming and cutting the semiconductor wafer to form a side electrode along the cutting line located between the circuit regions adjacent later, each of the cutting side surface electrode with the semiconductor chip to produce inspected by professional one Bing after three-dimensional mounting module, wherein the laminated side electrodes mutually electrically connected.
[5] A three-dimensional mounting module according to claim 4,
Connecting the respective side electrodes each other by wire bonding apparatus
Three-dimensional mounting module according to claim.
[6] a plurality of circuit regions are formed! /, A manufacturing method of a side semiconductor chip with electrodes prepared by cutting the semiconductor wafer Ru,
Is disposed across each circuit region adjacent an electrode forming step of forming the respective circuit region electrically connected to the Ru electrode,
Pro and cutting step, each semiconductor chip after the cutting step of forming a side electrode on the semiconductor chip by cutting the semiconductor wafer along cutting lines located between the circuit regions adjacent after the electrode forming step the method of manufacturing a semiconductor chip with a side electrode, characterized in that it comprises an inspection step of inspecting by a Bing.
[7] The method of manufacturing a semiconductor chip with a side electrode according to claim 6, said electrode is penetrations electrode
The method of manufacturing a semiconductor chip with a side electrode, characterized in.
[8] A method of manufacturing a semiconductor chip with a side electrode according to claim 6, said electrode is a bump disposed on circuitry region
The method of manufacturing a semiconductor chip with a side electrode, characterized in.
[9] a plurality of circuit regions are formed! /, Is connexion arranged straddled on each circuit region adjacent the semiconductor wafer Ru, wherein forming an electrode that is electrically connected to the circuit region, the electrode forming after cutting the said semiconductor wafer to form a side electrode along the cutting line located between the circuit region adjacent the multiple side electrodes semiconductor chip with the manufacture and testing by professional one Bing after the cutting a lamination step of laminating,
After the laminating step, the wire bonding step of electrically connecting the respective side electrodes each other by wire bonding apparatus,
Three-dimensional mounting module manufacturing method characterized in that it comprises a.
[10] The method of manufacturing a three-dimensional mounting module according to claim 9,
The wire bonding apparatus, three-dimensional mounting module manufacturing method characterized by pressing said a stacked semiconductor chip in the stacking direction.
[11] The method of manufacturing a three-dimensional mounting module according to claim 9,
The wire bonding apparatus, a manufacturing method of three-dimensional mounting module, wherein the side corners of the stacked semiconductor chip to perform the bonding holds the contact and separation direction of the bonding tool with respect to the side surface electrode.
[12] The method of manufacturing a three-dimensional mounting module according to claim 10, wherein the wire bonding device holds the side corners of the stacked semiconductor chip in the contact and separation direction of the bonding tool with respect to the side surface electrode bonding three-dimensional mounting module manufacturing method which is characterized in that a.
PCT/JP2007/072412 2006-11-22 2007-11-19 Semiconductor chip provided with side surface electrode, method for manufacturing the semiconductor chip, and three-dimensional mounting module wherein the semiconductor chip is laminated WO2008062767A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006316159A JP2008130932A (en) 2006-11-22 2006-11-22 Semiconductor chip with side electrode, manufacturing method therefor, and three-dimensional mount module with the semiconductor chip laminated therein
JP2006-316159 2006-11-22

Publications (1)

Publication Number Publication Date
WO2008062767A1 true true WO2008062767A1 (en) 2008-05-29

Family

ID=39429697

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/072412 WO2008062767A1 (en) 2006-11-22 2007-11-19 Semiconductor chip provided with side surface electrode, method for manufacturing the semiconductor chip, and three-dimensional mounting module wherein the semiconductor chip is laminated

Country Status (2)

Country Link
JP (1) JP2008130932A (en)
WO (1) WO2008062767A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013137049A1 (en) * 2012-03-16 2013-09-19 ソニー株式会社 Semiconductor device, semiconductor-device manufacturing method, semiconductor wafer, and electronic apparatus
JP2014197654A (en) * 2013-03-07 2014-10-16 株式会社東芝 Semiconductor device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101013549B1 (en) 2008-06-30 2011-02-14 주식회사 하이닉스반도체 Stacked semiconductor package and method of manufacturing the same
WO2011111300A1 (en) 2010-03-09 2011-09-15 パナソニック株式会社 Semiconductor package having electrode on side surface, and semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000100882A (en) * 1998-09-18 2000-04-07 Hitachi Ltd Manufacture of semiconductor device, test method, and jig used therefor
JP2001210782A (en) * 2000-01-27 2001-08-03 Seiko Epson Corp Semiconductor chip, multi-chip package, semiconductor device, and electronic equipment using it
JP2002270721A (en) * 2001-03-12 2002-09-20 Fujitsu Ltd Semiconductor device and its manufacturing method
JP2004221372A (en) * 2003-01-16 2004-08-05 Seiko Epson Corp Semiconductor device, semiconductor module, method of manufacturing both the same and electronic apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000100882A (en) * 1998-09-18 2000-04-07 Hitachi Ltd Manufacture of semiconductor device, test method, and jig used therefor
JP2001210782A (en) * 2000-01-27 2001-08-03 Seiko Epson Corp Semiconductor chip, multi-chip package, semiconductor device, and electronic equipment using it
JP2002270721A (en) * 2001-03-12 2002-09-20 Fujitsu Ltd Semiconductor device and its manufacturing method
JP2004221372A (en) * 2003-01-16 2004-08-05 Seiko Epson Corp Semiconductor device, semiconductor module, method of manufacturing both the same and electronic apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013137049A1 (en) * 2012-03-16 2013-09-19 ソニー株式会社 Semiconductor device, semiconductor-device manufacturing method, semiconductor wafer, and electronic apparatus
US9263488B2 (en) 2012-03-16 2016-02-16 Sony Corporation Semiconductor device, manufacturing method of semiconductor device, semiconductor wafer, and electronic equipment
JP2014197654A (en) * 2013-03-07 2014-10-16 株式会社東芝 Semiconductor device

Also Published As

Publication number Publication date Type
JP2008130932A (en) 2008-06-05 application

Similar Documents

Publication Publication Date Title
US7754531B2 (en) Method for packaging microelectronic devices
US6548391B1 (en) Method of vertically integrating electric components by means of back contacting
US5998859A (en) Packaging and interconnect system for integrated circuits
US6765228B2 (en) Bonding pad with separate bonding and probing areas
US7537959B2 (en) Chip stack package and manufacturing method thereof
US6441476B1 (en) Flexible tape carrier with external terminals formed on interposers
US20110248410A1 (en) Stack packages using reconstituted wafers
US6818977B2 (en) Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assemblies and packages including such semiconductor devices or packages
US20100007001A1 (en) Semiconductor package structure and method for manufacturing the same
US6124149A (en) Method of making stackable semiconductor chips to build a stacked chip module
US6506633B1 (en) Method of fabricating a multi-chip module package
US8421193B2 (en) Integrated circuit device having through via and method for preparing the same
US20030062631A1 (en) Semiconductor device and method of fabricating the same
US20090189256A1 (en) Manufacturing process of semiconductor device and semiconductor device
US20080044944A1 (en) Semiconductor device including semiconductor element surrounded by an insulating member and wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof
US7291929B2 (en) Semiconductor device and method of manufacturing thereof
US20040173901A1 (en) Thermally enhanced electronic flip-chip packaging with external-connector side die and method
US20040262735A1 (en) Semiconductor device and production method thereof
US20040124513A1 (en) High-density multichip module package
US6849945B2 (en) Multi-layered semiconductor device and method for producing the same
WO2009017758A2 (en) Reconstituted wafer stack packaging with after-applied pad extensions
US20060008944A1 (en) Substrate having built-in semiconductor apparatus and manufacturing method thereof
JPH08306853A (en) Semiconductor device, manufacture thereof and manufacture of lead frame
US6022758A (en) Process for manufacturing solder leads on a semiconductor device package
US20070105272A1 (en) Microelectronic devices and microelectronic support devices, and associated assemblies and methods

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07832142

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase in:

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07832142

Country of ref document: EP

Kind code of ref document: A1