JP2008124226A - Pin diode, method of manufacturing same, circuit including same, and method of applying resist material - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a PIN diode having a comparatively large height relative to the surface of a substrate with a good yield. <P>SOLUTION: In a method of manufacturing a PIN diode 100 having a PIN structure 120 and lower and upper electrodes 140 and 160, the PIN structure 120 includes a lower semiconductor layer 112, an intrinsic semiconductor layer 122 and an upper semiconductor layer 124 sequentially, laminated on a semiconductor substrate 110. The method includes steps of forming the PIN structure 120 on the surface of the semiconductor substrate 110, coating the surface of the semiconductor substrate 110 with a resist material to form a resist layer 150 having such a thickness that the surface of the resist layer is higher than the PIN structure 120 for the surface of the semiconductor 110, removing part of the resist layer 150, and depositing a conductive material on a region exposed from the resist layer 150. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a PIN diode, a method of manufacturing a PIN diode, a circuit including the PIN diode, and a method of applying a resist material. More specifically, a method of manufacturing a PIN diode manufactured by sequentially laminating various materials on a semiconductor substrate such as a compound semiconductor, a method of applying a resist material used therefor, and a PIN diode manufactured by these methods, And a circuit including the PIN diode.

  A monolithic microwave integrated circuit (MMIC) is manufactured by combining microwave circuit technology and semiconductor integrated circuit manufacturing technology, and an MMIC corresponding to a band up to about 100 GHz has already been announced. However, compared with digital integrated circuits, Si integrated circuits, and the like that have already been widely used, the current integration scale is still small, and higher-density mounting has been attempted.

  One of the elements forming the MMIC is a PIN diode. The PIN diode is formed by sequentially joining a P layer formed of a p-type semiconductor having a high impurity concentration, an I layer formed of an intrinsic semiconductor to which no impurity is added, and an N layer formed of an n-type semiconductor having a high impurity concentration. A PIN structure formed. Further, when a PIN diode is mounted on an integrated circuit in an MMIC, a vertical structure in which a P layer, an I layer, and an N layer are sequentially stacked from the substrate surface is preferable. The order of stacking may be P-I-N or N-I-P from the substrate side. In addition, it is preferable in terms of wiring technology that the electrode for connecting the PIN diode to the peripheral circuit is formed on the substrate surface in the vicinity of the PIN structure. However, the upper electrode of the PIN structure is connected to a circuit on the substrate by a three-dimensional conductor structure such as an air bridge.

  The following Patent Document 1 describes that a vertical PIN structure is formed by forming a P-type layer on the front surface of a semiconductor substrate and an N-type layer on the back surface, and making the substrate itself an I-type layer. The Patent Document 2 below describes a structure in which a p-type layer, a high resistance layer, and an n-type layer are sequentially stacked on a substrate.

  In the PIN diode, the minority carrier lifetime τ can be increased by sufficiently increasing the thickness T of the I layer that coincides with the direction of current flow. As a result, it is known that when used in microwave band and millimeter wave band circuits, the recombination time can be extended to reduce high-frequency signal distortion. For this purpose, the PIN diode used in the high-frequency circuit may have an I layer thickness exceeding 5 μm.

The PIN diode may be formed by injecting impurities into the substrate itself as the lowermost layer. In this case, the element region on the substrate has a mesa structure, so that the dark current and the junction capacitance can be reduced, and the junction area can be limited to prevent local breakdown due to the nonuniformity of the junction end. However, in the above-described PIN diode having a thick I layer, when the height difference between the surface of the substrate formed by the mesa structure and the height of the PIN structure itself is matched, the height from the epitaxial surface of the substrate to the top surface of the PIN structure is The difference reaches 10 μm or more.
JP-A-63-202958 JP 09-232234 A

  In the manufacture of a semiconductor integrated circuit, the formation of a PIN structure and a mesa structure is not necessarily the final stage of the manufacturing process. That is, after the PIN structure is formed and the mesa structure is formed, a process of forming electrodes, wirings, air bridges, and the like is performed. In this type of process, a photolithography technique using a resist film is frequently used.

  However, when an electrode is further formed on a PIN structure having a thick I layer and a PIN structure formed on a mesa structure having a step, a large step is formed around the element. For this reason, when a resist is applied in the photolithography process, a portion where the resist layer does not continue occurs in the stepped portion, and a resist mask having a desired pattern may not be formed after exposure. This is one of the causes of decreasing the yield of products in industrial production of PIN diodes having a thick I layer and operating in a wide band or semiconductor integrated circuits having the PIN diodes.

  Therefore, for the purpose of solving the above problems, a semiconductor substrate and a lower semiconductor layer, an intrinsic semiconductor layer, and an impurity which are sequentially stacked on the semiconductor substrate and implanted with an impurity and having one conductivity type are implanted. Manufacturing method for manufacturing a PIN diode having a PIN structure including an upper semiconductor layer having another conductivity type, a lower electrode adjacent to the lower semiconductor layer, and a pair of electrodes of the upper electrode adjacent to the upper semiconductor layer And a step of forming a PIN structure on the surface of the semiconductor substrate, and applying a resist material to the surface of the semiconductor substrate, and having a thickness that makes the surface of the substrate higher than the PIN structure. There is provided a manufacturing method including a step of forming a layer, a step of removing a part of the resist layer, and a step of depositing a conductor material in a region exposed from the resist layer.

  According to a second aspect of the present invention, there is provided a coating method in which a resist material for forming a resist layer is applied to the surface of a semiconductor substrate including a step having an upstanding surface that stands up with respect to the substrate surface. The resist material is sprayed toward the surface of the semiconductor substrate to attach the resist material to the rising surface, and the resist material attached to the semiconductor substrate including the step is irradiated with infrared rays to heat the resist material. A coating method is provided.

  Furthermore, as a third embodiment of the present invention, an upper semiconductor layer, which is manufactured by including the above manufacturing method or the above coating method, and is sequentially stacked on a semiconductor substrate and having one conductivity type implanted with impurities, an intrinsic semiconductor A pair of electrodes, a PIN structure having a lower semiconductor layer having another conductivity type implanted with impurities, a lower electrode adjacent to the lower semiconductor layer, and an upper electrode adjacent to the upper semiconductor layer A PIN diode is provided. Furthermore, as a fourth embodiment of the present invention, a circuit including the above PIN diode is provided.

  The above summary of the present invention does not enumerate all necessary features of the present invention. Therefore, a sub-combination of these feature groups can also be an invention.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a cross-sectional view illustrating a stage in a process of manufacturing a PIN diode 100 including a vertical PIN structure 120. As shown in the figure, at this stage, an n-type impurity such as S, Se, Si, or Sn is implanted, and the surface is made of a compound semiconductor such as GaAs in which the lower semiconductor layer 112 having the N-type conductivity is formed in the vicinity of the surface. A compound semiconductor substrate 110 and an intrinsic semiconductor layer 122 formed by injecting a p-type impurity such as Zn into the upper surface and forming an upper semiconductor layer 124 having a P-type conductivity in the vicinity of the upper end are stacked.

  The intrinsic semiconductor layer 122 is, for example, It is formed by depositing a semiconductor material on the semiconductor substrate 110 by MOCVD. Further, patterning is performed by dry etching by ICP type reactive ion etching (RIE), and a region which finally becomes an element is left. Therefore, the PIN structure 120 is already formed by the lower semiconductor layer 112, the intrinsic semiconductor layer 122, and the upper semiconductor layer 124. In this embodiment, the intrinsic semiconductor layer 122 has a thickness of 5 μm for the purpose of improving the operating characteristics of the finally obtained element in a signal band of 100 MHz or higher. Accordingly, the step formed by the intrinsic semiconductor layer 122 standing on the semiconductor substrate 110 has a height exceeding 5 μm.

  Hereinafter, a process of forming the lower electrode 140 and the upper electrode 160 on the lower semiconductor layer 112 and the upper semiconductor layer 124 of the PIN structure 120 will be described with reference to FIGS. 2 and 5 to 12. 2 and FIGS. 5 to 8 show the process of forming the lower electrode 140, and FIGS. 9 to 12 show the process of forming the upper electrode 160, respectively.

  FIG. 2 is a diagram illustrating one stage of the process of forming the lower electrode 140 in the manufacture of the PIN diode 100. As shown in the figure, at this stage, a resist layer 132 is formed on the entire surface of the semiconductor substrate 110 on which the PIN structure 120 is formed. The resist layer 132 is applied by, for example, a spin coat method. The applied resist layer 132 is further volatilized in the dispersion medium by heat treatment, and is fixed to the surface of the semiconductor substrate 110.

  Prior to the formation of the resist layer 132, the semiconductor substrate 110 is subjected to pre-baking treatment at 200 ° C. for about 1 minute to remove moisture, and then the surface is hydrophobized by HMDS (hexamethyldisilazane) treatment. Then, a pre-baking treatment was further performed at 200 ° C. for about 2 minutes to completely remove moisture. The resist layer 132 was formed by setting the semiconductor substrate 110 on a coater 200 described later. First, a commercially available positive photoresist material having a viscosity of 50 to 70 Cp was dropped and applied while rotating at a rotational speed of 500 to 2000 rpm. Next, a dispersion medium of a resist material was scattered by a post baking process at 120 ° C. for about 2 minutes to form a resist layer 132. The resist layer 132 thus formed was formed almost conformally following the steps of the semiconductor substrate 110 and the PIN structure 120.

  FIG. 3 is a diagram schematically showing the structure of the coater 200 used for forming the resist layer 132 when the above steps are performed. As shown in the figure, the coater 200 includes a chamber 216 that accommodates a semiconductor substrate 110 to be processed in a casing 214.

  Inside the chamber 216 are housed a turntable 222 that holds the semiconductor substrate 110 and a transmission mechanism 224 that transmits rotation driving force to the turntable 222. The transmission mechanism 224 is coupled to a drive motor 226 disposed outside the chamber 216, and rotates the turntable 222 by a rotational driving force obtained from the drive motor 226.

  Further, a spray nozzle 246 that discharges a resist material applied to the surface of the semiconductor substrate 110 held on the turntable 222 and an upper surface of the chamber 216 on the surface of the semiconductor substrate 110 that is also held on the turntable 222. An infrared heater 262 facing each other is provided. Further, one end of a duct fan 252 opens into the chamber 216 on the side opposite to the spray nozzle 246 around the semiconductor substrate 110 held on the turntable 222. The other end of the duct fan 252 is connected to an exhaust treatment facility outside the coater 200 via an exhaust duct 254.

  On the other hand, the spray nozzle 246 is connected to a pressure source via a regulator 242 and a valve 244. Spray nozzle 246 is also connected to a pressure source via regulator 232, valve 234, syringe 236 and mass flow controller 238. The syringe 236 is filled with a resist material and is pressurized from behind by opening the valve 234. As a result, the resist material is supplied to the spray nozzle 246 while the amount thereof is controlled via the mass flow controller 238.

  In the coater 200 having the above-described structure, when the valve 234 attached to the system including the syringe 236 is opened, the resist material pushed out from the syringe 236 according to the opening degree is discharged from the spray nozzle 246. Further, when the valve 244 directly connected to the spray nozzle 246 is opened, air is also discharged at a flow rate corresponding to the opening degree. Therefore, when the valve 244 is opened, the discharge speed of the resist material is increased, and the resist material is transported to the air in a fine particle state and blown toward the semiconductor substrate 110 placed on the turntable 222. In other words, when the valve 244 is closed, the resist material is dropped from the spray nozzle 246 in a liquid state.

  In the chamber 216, the resist material attached to the semiconductor substrate 110 can be heated from the surface thereof by operating the infrared heater 262. Therefore, in this coater 200, the resist material adhering to the surface of the semiconductor substrate 110 can be immediately heated by the infrared heater 262.

  Therefore, in this coater 200, after the resist material is dropped on the center of the semiconductor substrate 110, the turntable 222 is rotated to rotate the resist material attached to the semiconductor substrate 110 by applying a centrifugal force to the resist material. The resist material can be applied to the surface with a uniform thickness. In addition, after the resist material is applied once, it is heated by the infrared heater 262, dried and solidified, and then a process of laminating the resist layer 134 thereon can be continuously executed. Further, the resist material is sprayed and heated by the infrared heater 262 at the same time to simultaneously apply, dry and solidify the resist material, and the resist material is continuously applied until a resist layer 130 having a desired thickness is formed. It can also be deposited.

  FIG. 4 is a diagram showing another structure of the coater 200. As shown in the figure, the coater 200 includes a resistance heater 264 for heating the semiconductor substrate 110 on the turntable 222 from the lower surface in addition to the structure shown in FIG. Thereby, the temperature drop of the semiconductor substrate 110 can be prevented even during the spraying of the resist material. Therefore, the continuous spraying of the resist material can be performed efficiently.

  Further, by using the coater 200 having the above structure, the operation of heating the semiconductor substrate 110 from the back surface can be performed in the procedure of heating the resist material. This increases the amount of heat input, so that the resist layer 132 can be quickly dried or cured. In addition, even when the same amount of heat is input, since the local temperature rise is avoided by dividing the heat source into the front and back, the quality of the resist layer 132 is not deteriorated.

  The heating by the infrared heater 262 and the resistance heater 264 may be started prior to the procedure for attaching the resist material. Thereby, drying or hardening is started from the time when the resist material adheres to the semiconductor substrate 110, and the resist layer 132 can be formed more rapidly.

  As described above, by using the coater 200, a coating method for applying a resist material for forming the resist layer 132 on the surface of the semiconductor substrate 110 including a step having an upstanding surface rising with respect to the surface. A procedure in which a resist material is sprayed toward the surface of the semiconductor substrate 110 including the resist material and the resist material is attached to the rising surface, and the resist material is irradiated with infrared rays on the surface of the resist material attached to the semiconductor substrate 110 including the step. A coating method comprising heating the material.

  Thereby, since the continuous resist layer 130 can be reliably formed on the surface of the semiconductor substrate 110 including the step due to the PIN structure 120, a semiconductor circuit can be manufactured with a high yield. Further, since heating is performed from the surface of the resist layer 132, the resist layer 132 is quickly dried or cured, and the time required for forming the resist layer 132 is shortened.

  FIG. 5 is a diagram illustrating a next stage in the process of forming the lower electrode 140 in the manufacture of the PIN diode 100. As described above, in the semiconductor substrate 110 on which the PIN structure 120 having the thick intrinsic semiconductor layer 122 is formed, a large step is formed on the surface thereof. For this reason, as shown in FIG. 2, the resist layer 132 may not be completely continuous at the stage where the single resist layer 132 is formed, and a break may occur at the stepped portion.

  Therefore, the application and heating of the resist material described above are repeated so that the resist layer 132 is filled and the continuous resist layer 130 is formed. In the example shown in FIG. 5, the resist layer 130 in which the three resist layers 132, 134, and 136 are overlaid is formed by repeating application and heating of the resist material three times.

  In this manner, a process of applying the resist material to the semiconductor substrate 110 again can be performed by alternately repeating the process of attaching the resist material and the process of heating the resist material, overlapping the heated resist material. Thereby, the adhered resist material can be reliably dried or solidified irrespective of its thickness. Note that the stacked resist layers 134 and 136 can be formed under substantially the same conditions as the resist layer 132 described with reference to FIG.

  In addition, a process of repeating a series of procedures including a procedure of attaching a resist material and a procedure of heating the resist material until the surface of the semiconductor substrate 110 is covered with the continuous resist layer 130 can be performed. Thereby, a continuous resist layer 130 that can reliably protect the surface of the semiconductor substrate 110 or the semiconductor circuit can be formed. In other words, since the resist layer 130 having a uniform thickness can be formed on the surface of the semiconductor substrate 110 or the semiconductor circuit that is uneven due to a step, the accuracy of patterning in lithography can be improved.

  FIG. 6 is a diagram showing a further next stage of the process of forming the lower electrode 140. As shown in the figure, at this stage, a part of the resist layer 130 is removed around the intrinsic semiconductor layer 122 to form a hole pattern 131. As a result, the lower semiconductor layer 112 formed on the surface of the semiconductor substrate 110 is exposed inside the hole pattern 131. Such a step can be performed by a photolithographic method using a mask having an appropriate pattern.

  FIG. 7 is a diagram illustrating the next stage of the process of forming the lower electrode 140. As shown in the figure, a conductor material is deposited inside the hole pattern 131 of the resist layer 130. The conductor material deposited in the hole pattern 131 is ohmically coupled to the lower semiconductor layer 112 to form the lower electrode 140. In addition, AuGe / Ni etc. can be illustrated preferably as a conductor material.

  FIG. 8 is a diagram illustrating the next stage of the process of forming the lower electrode 140. At this stage, the remaining resist layer 130 is removed. As a result, a lower electrode 140 ohmically coupled to the lower semiconductor layer 112 is formed around the intrinsic semiconductor layer 122 on the semiconductor substrate 110.

  Thus, the lower electrode 140 is formed by the process of depositing the conductor material. As described above, since the resist layer 130 covers the surface of the semiconductor substrate 110 in a region other than the hole pattern 131, the lower portion of the resist layer 130 is surely disposed in the vicinity of the PIN structure 120 having a relatively large height. Electrode 140 can be formed. Therefore, the yield of manufacturing a semiconductor circuit including the PIN structure 120 is not lowered at this stage.

  FIG. 9 is a diagram illustrating one stage of the process of forming the upper electrode 160 formed in the upper semiconductor layer 124 in the manufacture of the PIN diode 100. As shown in the figure, at this stage, the surface of the semiconductor substrate 110 including the PIN structure 120 is thickly covered with a resist material, and this is heated and solidified to form a resist layer 150.

  Here, the resist layer 150 has a thickness approximately 2 μm larger than the height of the PIN structure 120 including the upper electrode 160. Thereby, all elements on the semiconductor substrate 110 are embedded in the resist layer 150, and the surface of the resist layer 150 becomes substantially flat. Such a resist layer 150 can be formed by a single application by thickly applying a resist material having a high viscosity by a spin coating method.

  As described above, the step of forming the resist layers 132, 134, and 136 can be a step of applying a resist material by a spin coating method. Accordingly, the resist layer 130, 150, 170 having a uniform thickness can be formed by applying the resist material easily and at high speed.

  Further, by using the coater 200 shown in FIG. 3 or FIG. 4, the procedure of attaching the resist material and the procedure of heating the resist material can be performed simultaneously or alternately continuously. As a result, a continuous resist layer 150 having a desired thickness can be formed, and the surface of the semiconductor substrate 110 including a step can be reliably covered with the resist layer 150.

  FIG. 10 is a diagram illustrating the next stage of the process of forming the upper electrode 160. As shown in the figure, at this stage, a part of the resist layer 150 is removed above the upper semiconductor layer 124 to form a hole pattern 151. As a result, a part of the top surface of the upper semiconductor layer 124 is exposed inside the hole pattern 151. Such a step can be performed by a photolithographic method using a mask having an appropriate pattern.

  FIG. 11 is a diagram showing a further next stage in the process of forming the upper electrode 160 in the manufacture of the PIN diode 100. As shown in the figure, a conductor material is deposited inside the hole pattern 151 of the resist layer 150. The conductor material deposited in the hole pattern 151 is ohmically coupled to the upper semiconductor layer 124 to form the upper electrode 160. As the conductive material, the same material as the lower electrode 140 can be used.

  FIG. 12 is a diagram illustrating the next stage of the process of forming the upper electrode 160. As shown in the figure, at this stage, the remaining resist layer 150 is removed. As a result, the upper electrode 160 is formed on the upper surface of the upper semiconductor layer 124.

  Thus, the upper electrode 160 is formed by the process of depositing the conductor material. Thereby, since the upper electrode 160 can be reliably formed on the top surface of the PIN structure 120 having a relatively large height, a semiconductor circuit including the PIN structure 120 can be manufactured with a high yield. Next, the process of forming the mesa structure 172 including the PIN structure 120 will be described step by step with reference to FIGS.

  FIG. 13 is a diagram illustrating one stage in the process of forming the mesa structure 172 in the manufacture of the PIN diode 100. As shown in the figure, at this stage, first, the surface of the semiconductor substrate 110 is covered with a resist material thickly, and this is heated and solidified to form a resist layer 170.

  Here, the resist layer 170 has a thickness larger than the height of the PIN structure 120 including the upper electrode 160. Thereby, all elements on the semiconductor substrate 110 are embedded in the resist layer 170, and the surface of the resist layer 170 becomes substantially flat.

  Such a resist layer 170 can be formed using the coater 200 shown in FIG. 3 or FIG. That is, a procedure for applying a resist material to the semiconductor substrate 110 by a spin coating method or a spray method, and the resist material applied to the semiconductor substrate 110 are heated by an infrared heater 262 to volatilize the dispersion medium. The resist layer 170 shown in FIG. 13 is formed by alternately executing the procedure of making the resist layer 170 fixed to 110 until the surface of the resist layer 170 becomes flat.

  When the coater 200 shown in FIG. 4 is used, it is also preferable to operate the resistance heater 264 disposed below the turntable 222 to keep the temperature of the semiconductor substrate 110 high. Thereby, the interval of the procedure of applying the resist material to the substrate can be narrowed, and the resist layer 170 can be formed quickly.

  As described above, a series of procedures including the procedure of attaching the resist material and the procedure of heating the resist material can be repeated until the surface of the semiconductor substrate 110 is covered with the continuous resist layer 170. Thereby, a continuous resist layer 170 that can reliably protect the surface of the semiconductor substrate 110 or the semiconductor circuit can be formed. Further, the resist layer 170 having a desired thickness can be formed regardless of the level difference of the surface of the semiconductor substrate 110 and regardless of the viscosity of the resist material used.

  FIG. 14 is a diagram illustrating the next stage in the process of forming the mesa structure 172 in the manufacture of the PIN diode 100. As shown in the figure, at this stage, the resist layer 170 is removed outside the PIN structure 120 including the lower electrode 140. In the region where the resist layer 170 is removed, the surface of the semiconductor substrate 110 is exposed, while in the region surrounded by the side end surface 171 of the resist layer 170, the lower electrode 140, the intrinsic semiconductor layer 122, the upper semiconductor layer 124, and the upper electrode 160 is embedded in the resist layer 170.

  FIG. 15 is a diagram showing a further next stage in the process of forming the mesa structure 172. As shown in the figure, at this stage, the surface of the semiconductor substrate 110 including the lower semiconductor layer 112 is etched using the patterned resist layer 170 as a mask. The semiconductor substrate 110 is etched until the epitaxial layer 114 is exposed. As a result, the lower semiconductor layer 112 is removed outside the lower electrode 140 and isolation is formed. Such etching can be preferably performed by dry etching such as IPC type reactive ion etching.

  FIG. 16 is a diagram showing the next stage of the process of forming the mesa structure 172. As shown in the figure, at this stage, the resist layer 170 used as a mask is removed. Thus, the mesa structure 172 including the PIN structure 120 including the lower semiconductor layer 112 that is shielded from the surroundings is formed on the semiconductor substrate 110.

  Through such a series of steps, the semiconductor substrate 110 and the lower semiconductor layer 112, the intrinsic semiconductor layer 122, and the impurity which are sequentially stacked on the semiconductor substrate 110 and are implanted with one conductivity type are implanted. A PIN structure 120 including an upper semiconductor layer 124 having another conductivity type, a lower electrode 140 adjacent to the lower semiconductor layer 112, and a pair of electrodes of an upper electrode 160 adjacent to the upper semiconductor layer 124. A manufacturing method for manufacturing the diode 100, the step of forming the PIN structure 120 on the surface of the semiconductor substrate 110, a resist material applied to the surface of the semiconductor substrate 110, Forming a resist layer 150 having a thickness higher than that of the PIN structure 120, and a part of the resist layer 150 Removing method comprising a step of depositing a conductive material on the exposed region of the resist layer 150 is performed. Thus, a continuous resist mask can be reliably formed without interruption on the surface of the semiconductor substrate 110 on which the PIN structure 120 is formed, so that a semiconductor circuit including the PIN structure 120 can be manufactured with high yield.

Here, for example, in the PIN diode 100 formed of a GaAs compound and capable of being made monolithic, the carrier lifetime τ required when the lower limit frequency f _min of the operation band is set to 100 MHz can be obtained from the following equation 1. .

f _min = 10 / 2π · τ = 1.6 / τ

  On the other hand, the carrier lifetime τ of the manufactured PIN diode 100 is obtained from the reverse recovery time characteristic using the following equation.

  Trf = τ · log (1 + If / Ir)

  On the other hand, FIG. 17 is a graph showing the relationship between the thickness of the intrinsic semiconductor layer 122 and the reverse recovery time characteristic in the PIN diode 100 as measured values and calculated values. In the figure, curves A, B, and D indicate the relationship between the current and reverse recovery time in the PIN diode 100 having the intrinsic semiconductor layer 122 having a thickness of 0.5 μm, 2 μm, and 5 μm, respectively, as measured values. A curve C shows a calculated value when the intrinsic semiconductor layer 122 is 5 μm. As can be seen from the figure, if the thickness of the intrinsic semiconductor layer 122 is 5 μm or more, the carrier lifetime τ can be 15 nsec or more. As can be seen from FIG. 17 and the above formula, the PIN diode 100 having the intrinsic semiconductor layer 122 having a thickness of 5 μm or more operates well at an operating frequency with a lower limit of 100 MHz.

  As described above, using the above-described coating method, the upper semiconductor layer 124, the intrinsic semiconductor layer 122, and the impurity which are sequentially stacked on the semiconductor substrate 110 and implanted with one conductivity type are implanted. A PIN structure 120 having a lower semiconductor layer 112 having another conductivity type, a lower electrode 140 adjacent to the lower semiconductor layer 112, and a pair of electrodes of an upper electrode 160 adjacent to the upper semiconductor layer 124 A PIN diode 100 is manufactured. This provides a low-cost PIN diode 100 manufactured with a high yield.

  Next, a process of further forming a pair of air bridges 190 on the PIN diode 100 formed by the series of procedures up to FIG. 16 will be described with reference to FIGS. The air bridge 190 formed here couples the lower electrode 140 and the upper electrode 160 to other circuits, elements, wirings, and the like disposed outside the mesa structure 172, respectively. However, illustration of wirings outside the mesa structure 172 is omitted.

  FIG. 18 is a diagram showing one stage in the process of forming a pair of air bridges 190 in the PIN diode 100. FIG. As shown in the figure, at this stage, first, a thick resist layer 180 is formed on the entire surface of the semiconductor substrate 110 including the intrinsic semiconductor layer 122 including the upper semiconductor layer 124, the lower electrode 140, the upper electrode 160, and the lower semiconductor layer 112. Form.

  At this time, there is a step having a large height difference approaching 10 μm between the surface of the epitaxial layer 114 exposed outside the mesa structure 172 and the top surface of the PIN structure 120 including the upper electrode 160. Therefore, the resist layer 180 is formed by a method in which spraying of the resist material and heating by the infrared heater 262 are simultaneously performed using the coater 200 shown in FIG. Further, spraying and heating of the resist material were continuously performed until the resist layer 180 had a desired thickness. Further, prior to the formation of the resist material, the resistance heater 264 was operated, and the formation of the resist layer 180 was started in a state where the temperature of the semiconductor substrate 110 was raised to some extent in advance. By these series of methods, the entire surface of the semiconductor substrate 110 including the intrinsic semiconductor layer 122 including the upper semiconductor layer 124, the lower electrode 140, the upper electrode 160, and the lower semiconductor layer 112 is covered with the continuous resist layer 180. Further, the surface of the resist layer 180 becomes substantially flat.

  FIG. 19 is a diagram illustrating a next stage in the process of forming the air bridge 190. As shown in the figure, at this stage, four hole patterns 181, 182, 183, and 184 are formed in the resist layer 180 by photolithography. Of the four hole patterns 181, 182, 183, and 184, the hole pattern 181 reaches the upper electrode 160 and exposes the surface of the upper electrode 160. The hole pattern 184 reaches the lower electrode 140 to expose the surface of the lower electrode 140. Further, the hole patterns 183 and 184 reach the outside of the mesa structure 172 of the semiconductor substrate 110 to expose the surface of the epitaxial layer 114.

  FIG. 20 is a diagram showing the next stage of the process of forming the air bridge 190. As shown in the drawing, at this stage, the vapor deposition metal layer 191 is formed on the entire surface of the semiconductor substrate 110 in the state shown in FIG. 9 including the inside of the hole patterns 181, 182, 183 and 184. In this embodiment, Ti and Au are sequentially laminated by sputtering to form the deposited metal layer 191, but other deposition methods can also be selected. Also, the material of the deposited metal layer 191 is arbitrarily selected as long as it has good adhesion to the plated metal layer 193 described later and has low contact resistance to the lower electrode 140, the upper electrode 160 and the epitaxial layer 114. it can.

  FIG. 21 is a diagram showing the next stage of the process of forming the air bridge 190. As shown in the figure, at this stage, another resist layer 185 is formed on the entire surface of the semiconductor substrate 110 on which the deposited metal layer 191 is formed. The resist layer 185 is filled up to the inside of the hole patterns 181, 182, 183, and 184, and the surface thereof becomes substantially flat.

  FIG. 22 is a diagram showing the next stage of the process of forming the air bridge 190. As shown in the figure, at this stage, a part of the resist layer 185 is removed by a photolithographic method to form a pair of hole patterns 186 and 187. One hole pattern 186 is formed in a region including the hole patterns 182 and 184 of the resist layer 180. The other hole pattern 186 is formed in a region including the hole patterns 181 and 183 of the resist layer 180. The resist layer 185 is removed to the inside of the lower hole patterns 181, 182, 183, and 184, and the lower electrode 140, the upper electrode 160, or the epitaxial layer 114 is exposed inside the hole patterns 186 and 187. .

  FIG. 23 is a diagram showing the next stage of the process of forming the air bridge 190. As shown in the figure, at this stage, a plated metal layer 193 is formed inside the hole patterns 186 and 187. The plated metal layer 193 can be selectively formed inside the hole patterns 186 and 187 by electroplating using the deposited metal layer 191 as one electrode. In addition, although Au can be illustrated preferably as a material of the plating metal layer 193, it is not necessarily limited to this.

  FIG. 24 is a diagram showing the next stage of the process of forming the air bridge 190. As shown in the figure, at this stage, the upper resist layer 185 is removed. However, since the lower resist layer 180 is covered with the vapor deposition metal layer 191, it is not removed at this stage.

  FIG. 25 is a diagram showing the next stage of the process of forming the air bridge 190. As shown in the figure, at this stage, the surfaces of the deposited metal layer 191 and the plated metal layer 193 are removed entirely by ion milling. The removal amount is an amount by which the deposited metal layer 191 exposed on the surface is removed. Thereby, the resist layer 180 is exposed between the plated metal layers 193.

  In the above treatment, the surface of the plated metal layer 193 is also removed. Therefore, in the step of forming the plated metal layer 193, it is preferable to form a film with a thickness that allows for the thickness of the plated metal layer 193 to be removed in this step.

  FIG. 26 is a diagram illustrating a structure of the PIN diode 100 including the air bridge 190. As shown in the figure, by removing the lower resist layer 180 from the state shown in FIG. 25, a pair of air bridges 190 connecting the lower electrode 140 and the upper electrode 160 to the surface of the epitaxial layer 114 are formed. Is done.

  Thus, the air bridge 190 which connects the PIN structure 120 to another element or circuit through the lower electrode 140 and the upper electrode 160 is formed by the process of depositing the conductive material. Thereby, since the air bridge 190 that connects the upper electrode 160 of the PIN structure 120 and other elements or circuits can be reliably formed, a complicated semiconductor circuit including the PIN structure 120 can be manufactured with high yield.

  In addition, by using the air bridge 190 formed as described above, a circuit including the PIN diode 100 can be manufactured. Thereby, a circuit including the PIN diode 100 manufactured at a low cost with a high yield is provided.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. Further, it is apparent from the description of the scope of claims that the embodiment added with such changes or improvements can be included in the technical scope of the present invention.

FIG. 5 is a diagram showing one stage in the formation of the lower electrode 140. FIG. 5 is a diagram showing a next stage in the formation of the lower electrode 140. It is a schematic diagram which shows the structure of the coater 200 used for application | coating of a resist material. It is a schematic diagram which shows the other structure of the coater. FIG. 10 is a diagram showing a further next stage in the formation of the lower electrode 140. FIG. 6 is a diagram showing a next stage in the formation of the lower electrode 140. FIG. 6 is a diagram showing a next stage in the formation of the lower electrode 140. FIG. 6 is a diagram showing a next stage in the formation of the lower electrode 140. FIG. 6 is a diagram showing one stage in the formation of an upper electrode 160. FIG. 5 is a diagram showing a next stage in the formation of the upper electrode 160. FIG. 5 is a diagram showing a further next stage in the formation of the upper electrode 160. FIG. 5 is a diagram showing a next stage in the formation of the upper electrode 160. FIG. 6 shows a stage in the formation of a mesa structure 172. FIG. 5 shows the next stage in the formation of the mesa structure 172. FIG. 10 is a diagram showing a further next stage in the formation of the mesa structure 172. FIG. 6 shows the next stage in the formation of the mesa structure 172. It is a graph which shows the relationship between the thickness of the intrinsic semiconductor layer 122, and a reverse recovery time characteristic. FIG. 4 is a diagram showing one stage in the formation of an air bridge 190. FIG. 6 is a diagram showing a next stage in the formation of the air bridge 190. FIG. 6 is a diagram showing a next stage in the formation of the air bridge 190. FIG. 6 is a diagram showing a next stage in the formation of the air bridge 190. FIG. 6 is a diagram showing a next stage in the formation of the air bridge 190. FIG. 6 is a diagram showing a next stage in the formation of the air bridge 190. FIG. 6 is a diagram showing a next stage in the formation of the air bridge 190. FIG. 6 is a diagram showing a next stage in the formation of the air bridge 190. It is a figure which shows the state which the air bridge 190 was completed.

Explanation of symbols

100 PIN diode, 110 semiconductor substrate, 112 lower semiconductor layer, 114 epitaxial layer, 120 PIN structure, 122 intrinsic semiconductor layer, 124 upper semiconductor layer, 130, 132, 134, 136, 150, 170, 180, 185 resist layer, 131, 151, 181, 182, 183, 184, 186, 187 Hole pattern, 140 Lower electrode, 160 Upper electrode, 171 Side end surface, 172 Mesa structure, 190 Air bridge, 191 Evaporated metal layer, 193 Plated metal layer, 200 Coater , 214 housing, 216 chamber, 222 turntable, 224 transmission mechanism, 226 drive motor, 232, 242 regulator, 234, 244 valve, 236 syringe, 238 mass flow controller, 246 spray nose , 252 Duct, 254 exhaust duct, 262 infrared heater, 264 a resistance heater

Claims (13)

A semiconductor substrate;
A lower semiconductor layer having one conductivity type implanted with impurities, an intrinsic semiconductor layer having a low impurity concentration, and an upper semiconductor having another conductivity type implanted with impurities, which are sequentially stacked on the surface of the semiconductor substrate. A PIN structure including a layer;
A manufacturing method of manufacturing a PIN diode having a lower electrode adjacent to the lower semiconductor layer and a pair of electrodes of the upper electrode adjacent to the upper semiconductor layer,
Forming the PIN structure on a surface of the semiconductor substrate;
Applying a resist material to the surface of the semiconductor substrate, and forming a resist layer having a thickness higher than that of the PIN structure on the surface of the substrate;
Removing a part of the resist layer;
And a step of depositing a conductive material on a region exposed from the resist layer.   The manufacturing method according to claim 1, wherein the lower electrode is formed by the step of depositing the conductive material.   The manufacturing method according to claim 1, wherein the upper electrode is formed by the step of depositing the conductive material.   2. The manufacturing method according to claim 1, wherein the step of depositing the conductive material forms an air bridge that connects the PIN structure to another element or circuit via the upper electrode.   The manufacturing method according to claim 1, wherein the step of forming the resist layer includes a step of applying the resist material by a spin coating method. An application method for applying a resist material for forming a resist layer on a surface of a semiconductor substrate including a step having an upstanding surface rising from a substrate surface,
A procedure of spraying a resist material toward the surface of the semiconductor substrate including the step to attach the resist material to the standing surface;
A method of heating the resist material by irradiating the surface of the resist material attached to the semiconductor substrate including the step with infrared rays.   The coating method according to claim 6, wherein the procedure of attaching the resist material and the procedure of heating the resist material are simultaneously performed.   The step of depositing the resist material and the step of heating the resist material are alternately repeated, superposed on the resist material after heating, and the step of spraying the resist material again toward the semiconductor substrate. 6. The coating method according to 6.   The series of steps including a step of attaching the resist material and a step of heating the resist material are repeated until the surface of the semiconductor substrate including the rising surface is covered with the continuous resist layer. The coating method as described.   The coating method according to claim 6, wherein the step of heating the resist material includes an operation of heating the semiconductor substrate also from the back surface.   The coating method according to claim 10, wherein the operation of heating the semiconductor substrate from the back surface is started prior to the procedure of attaching the resist material.   An upper semiconductor layer manufactured by the method according to any one of claims 1 to 11 and sequentially stacked on the semiconductor substrate and having one conductivity type by being implanted with impurities, an intrinsic semiconductor layer, And a pair of electrodes of a PIN structure having a lower semiconductor layer having another conductivity type implanted with impurities, a lower electrode adjacent to the lower semiconductor layer, and an upper electrode adjacent to the upper semiconductor layer A PIN diode.   A circuit comprising the PIN diode according to claim 12.

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