JP2008124143A - Solid state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high sensitivity solid state imaging device wherein the transfer efficiency for signal charge is improved while realizing low voltage drive. <P>SOLUTION: The solid state imaging device according to one embodiment of this invention comprises a semiconductor substrate provided with an n-type semiconductor layer on the main surface thereof, an element isolation region including an insulating film and a p-type semiconductor layer provided in the n-type semiconductor layer for electrically isolating adjacent pixel regions, a gate electrode provided on the surface of the n-type semiconductor layer via a gate insulating film, a charge storage layer of an n-type semiconductor provided in the n-type semiconductor layer on one side of the gate electrode and spaced apart from the surface, a surface shield layer of a p-type semiconductor layer provided in the n-type semiconductor layer above the charge storage layer and spaced apart from the charge storage layer and provided not spaced apart from the gate electrode in the plan view, and an impurity layer of an n-type semiconductor provided in a part of the region between the charge storage layer and the surface shield layer and so provided that it includes the upper end of the charge storage layer on the gate electrode side and it overlaps a part of the charge storage layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a pixel structure of a metal-oxide-semiconductor (MOS) type solid-state imaging device.

  MOS type solid-state imaging devices have been used in place of conventional CCD (charge coupled device) type solid-state imaging devices (hereinafter referred to as CCD image sensors), particularly for low voltage drive and low power consumption applications.

  Since a MOS type solid-state imaging device is basically manufactured by a CMOS process, it can be easily integrated with other CMOS circuits. A photoelectric conversion element (also called a photodiode) and a MOS transistor are provided on the same semiconductor wafer. Is done. In a CMOS (complementary MOS) type amplification type solid-state imaging device (hereinafter referred to as a CMOS image sensor), an optical signal is detected by a photoelectric conversion element, and the generated signal charge is stored in a charge storage layer to modulate this potential. The pixel cell itself has an amplification function by modulating the amplification transistor inside the pixel cell by the potential of the charge storage layer. This CMOS image sensor is driven by, for example, a low voltage of 3 V and a single power source, and has a low power consumption of 50 mW.

  Conventionally, in a solid-state imaging device, a surface shield layer made of a p-type semiconductor layer is formed on the surface of a charge storage layer made of an n-type semiconductor layer that constitutes a photoelectric conversion element in order to reduce white scratches and dark current. A surface shield structure is adopted. The signal charge stored in the charge storage layer is transferred to the detection unit via a channel formed under the readout gate electrode.

  In the CCD image sensor, since a high voltage, for example, 10 V is applied to the readout gate electrode, all signal charges in the charge storage layer are read out to the detection unit. However, in the CMOS image sensor, since the voltage that can be applied to the readout gate electrode is low, for example, 3.3 V, all signal charges in the charge storage layer are transferred to the detection unit due to the potential barrier by the surface shield layer. I can't do that.

  Patent Document 1 discloses a solid-state imaging device that improves the signal charge transfer efficiency in a CMOS image sensor. In the conventional CMOS image sensor, an active region is formed in a p-type well. In the CMOS image sensor of Patent Document 1, an n-type charge storage layer is formed in the p-type well, a protrusion is provided on the read gate electrode, and a part of the protrusion is projected above the charge storage layer. Thus, the signal charge transfer efficiency is improved. Further, the same n-type impurity layer as that of the charge storage layer is provided between the protrusion of the gate electrode and the charge storage layer to further improve the signal charge transfer efficiency.

Further, the solid-state imaging device disclosed in Patent Document 2 has an n-type first covering the entire surface of the charge storage layer between the n-type charge storage layer formed in the p-type well and the p-type surface shield layer. Two diffusion layers are provided. By extending the second diffusion layer to below the gate electrode, the signal charge transfer efficiency is improved.
JP 2003-188367 A JP 2005-72236 A

  The present invention provides a high-sensitivity solid-state imaging device that improves signal charge transfer efficiency while realizing low-voltage driving.

  A solid-state imaging device according to an aspect of the present invention includes a semiconductor substrate including an n-type semiconductor layer on a main surface, an insulating film and a p-type semiconductor layer provided in the n-type semiconductor layer, and includes adjacent pixel regions. Device isolation for electrical isolation, a gate electrode provided on the surface of the n-type semiconductor layer via a gate insulating film, and the n-type semiconductor layer on one side of the gate electrode spaced apart from the surface The n-type semiconductor charge storage layer provided above and the n-type semiconductor layer above the charge storage layer are provided apart from the charge storage layer, and provided in a plane without being separated from the gate electrode. A p-type semiconductor surface shield layer and a part of a region between the charge storage layer and the surface shield layer, and including an upper end of the charge storage layer on the gate electrode side. Impurities of n-type semiconductors that overlap with a part Comprising the door.

  The present invention provides a high-sensitivity solid-state imaging device that realizes low-voltage driving and improves signal charge transfer efficiency.

  In the embodiment of the present invention, high sensitivity is obtained by forming an active element of a pixel in an n-type semiconductor layer, and low readout is achieved by providing an n-type impurity layer on a part of the n-type charge storage layer on the gate electrode side. Provided is a solid-state imaging device in which the transfer efficiency of signal charges is increased even with a voltage. This solid-state imaging device realizes low voltage driving by a single power supply of 3.3V, for example.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the figure, corresponding parts are indicated by corresponding reference numerals. The following embodiment is shown as an example, and various modifications can be made without departing from the spirit of the present invention.

(Embodiment)
An example of a MOS type solid-state imaging device (CMOS image sensor) according to an embodiment of the present invention is shown in FIGS. FIG. 1 is a plan view of a part of one pixel, and FIG. 2 is a cross-sectional view taken along the line AA in FIG.

  The pixel of the CMOS image sensor 100 according to the present embodiment includes a gate electrode 24, an n-type semiconductor charge storage layer 26 provided in the n-type semiconductor layer 14, an n-type semiconductor impurity layer 28, and a p-type semiconductor surface shield layer. 30 and an n-type semiconductor detector 32. The charge storage layer 26 and the surface shield layer 30 are provided in a self-aligned manner with the gate electrode 22, and both are provided apart in the depth direction. The impurity layer 28 is provided at a depth between the charge storage layer 26 and the surface shield layer 30, and is provided so as to overlap a part of the charge storage layer 26. The impurity layer 28 is further provided below the gate electrode 24.

  By forming the photoelectric conversion portion including the charge storage layer 26 of the CMOS image sensor in the n-type semiconductor layer 14, the sensitivity can be increased compared to the case where the charge storage layer is formed in the conventional p-type semiconductor layer. That is, the n-type semiconductor layer can expand the depletion layer more than the p-type semiconductor layer, so that the efficiency of capturing photoelectrically converted electrons can be increased.

  Further, by providing the impurity layer 28 as described above, it is possible to suppress the generation of a potential barrier formed in the channel region under the gate electrode 24 by the surface shield layer 30. As a result, the signal charge stored in the charge storage layer 26 can be efficiently transferred to the detection unit 32 even at a low gate voltage, for example, 3.3V.

  Leakage current can be reduced by providing the impurity layer 28 apart from the element isolation 16 as shown in FIG. FIG. 3 is a diagram showing the relationship between the distance between the impurity layer 28 and the element isolation 16 and the leakage current from the impurity layer 28. The horizontal axis indicates the distance between the impurity layer 28 and the element isolation 16. The vertical axis represents the ratio of elements having a leakage current equal to or less than a predetermined value (hereinafter referred to as a leakage current index) on an arbitrary scale. That is, the larger the leakage current index, the more preferable characteristics. When the impurity layer 28 is in contact with the element isolation 16, the leakage current index is about 0.8, which is a low value. When the distance between the impurity layer 28 and the element isolation 16 is 0.2 μm, the leakage current index varies between 0.8 and 2.5. When the interval is further increased to 0.4 μm or more, the leakage current index becomes substantially constant between 2 and 2.5. Therefore, in order to reduce the leakage current from the impurity layer 28, the impurity layer 28 is preferably separated from the element isolation 16 by 0.3 μm or more. More preferably, it is separated by 0.4 μm or more.

A cross-sectional structure of the CMOS image sensor 100 according to the present embodiment will be described with reference to FIG. The CMOS image sensor 100 includes an n-type semiconductor layer (hereinafter referred to as an n-epi layer) 14 epitaxially grown on a semiconductor substrate (hereinafter referred to as a p ⁺ substrate) 12 doped with a p-type dopant at a high concentration. A semiconductor wafer (hereinafter referred to as n / p ⁺ wafer) 10 is used. The p ⁺ substrate 12 is, for example, a silicon substrate doped with boron (B) at about 1 to 5 × 10 ¹⁸ cm ⁻³ , and the n-epi layer 14 is, for example, phosphorus (P) with 1 to 5 × 10 ¹⁵ cm. It is a silicon layer having a thickness of 3 to 5 μm doped with about ⁻³ .

In the n-type semiconductor layer 14, an element isolation 16 that electrically isolates adjacent pixels is provided. The element isolation 16 includes an element isolation insulating film 16-1 provided near the surface of the n-type semiconductor layer, and a p-type semiconductor provided so as to connect the element isolation insulating film 16-1 and the p ⁺ substrate 12 thereunder. Element isolation diffusion layer 16-2. The element isolation 16 is provided so as to surround one pixel region, and electrically isolates adjacent pixels.

A gate electrode 24 is provided on the surface of the n-type semiconductor layer 14 via a gate insulating film 22. As the gate insulating film 22, for example, a silicon oxide film (SiO ₂ film) formed by thermal oxidation can be used. As the gate electrode 24, for example, a polysilicon film doped with phosphorus at a high concentration can be used. Although not shown, the gate electrode 24 is generally provided with a sidewall insulating film. Here, the gate electrode 24 may include a sidewall insulating film.

An n-type semiconductor charge storage layer 26 is provided in the n-type semiconductor layer 14 on one side of the gate electrode 24 at a depth spaced from the surface. The charge storage layer 26 is provided in a self-aligned manner without being spaced apart from the gate electrode 24 in a plan view. The charge storage layer 26 is formed, for example, by ion implantation of phosphorus (P) at an acceleration voltage of 250 to 350 KV and a dose of 1 to 5 × 10 ¹² cm ⁻² . Thereby, the peak of phosphorus concentration is located, for example, about 0.2 to 0.3 μm from the surface.

A surface shield layer 30 doped with a high concentration of p-type impurities is provided on the surface of the n-type semiconductor layer 14 above the charge storage layer 26. The surface shield layer 30 prevents the influence of the interface state on the charge storage layer 26 and avoids depletion on the surface of the charge storage layer 26. A p-type impurity such as boron (B) is ion-implanted at an acceleration voltage of 10 KV and a dose of 1 to 5 × 10 ¹³ cm ⁻² . Thereby, for example, the surface shield layer 30 which is a high concentration p-type diffusion layer having a boron concentration of about 1 × 10 ¹⁹ cm ⁻³ is formed at a depth of less than about 0.1 μm from the surface. The surface shield layer 30 is provided in a self-aligned manner without being spaced apart from the gate electrode 24 in a plan view. With such a structure, the n-type semiconductor layer 14 can be present between the charge storage layer 26 and the surface shield layer 30, and the charge storage layer 26 and the surface shield layer 30 are in direct contact with each other in a plane. You can avoid that. For this reason, the leakage current from the charge storage layer 26 can be reduced.

  An n-type semiconductor impurity layer 28 is provided in part of the region between the charge storage layer 26 and the surface shield layer 30. As shown in FIG. 2, the impurity layer 28 is provided so as to overlap a part of the charge storage layer 26 on the gate electrode 24 side in a plan view and further extend below the gate electrode 24. A portion of the impurity layer 28 that overlaps the charge storage layer 26 in plan view partially overlaps the charge storage layer 26 also in the vertical direction. The impurity layer 28 has a dopant concentration higher than that of the charge storage layer 26, suppresses a potential barrier due to the surface shield layer 30, and facilitates transfer of signal charges stored in the charge storage layer 26. As described above, by reducing the contact area between the p-type surface shield layer 30 and the n-type impurity layer 28, leakage of signal charges in the charge storage layer 26 is suppressed.

  An n-type semiconductor detector 32 is provided in the n-type semiconductor layer 14 on the side facing the charge storage layer 26 with the gate electrode 24 interposed therebetween. The detection unit 32 and the impurity layer 28 are provided at a distance that does not punch through. In order to prevent punch-through between the detection unit 32 and the charge storage layer 26 or the impurity layer 28, a p-type impurity layer 34 that functions as a punch-through stopper is provided below the detection unit 32. The signal charge is transferred from the charge storage layer 26 to the detection unit 32 through a channel formed under the gate electrode 24.

  In the CMOS image sensor adopting the surface shield structure as described above, for example, by forming the impurity layer 28 between the charge storage layer 26 and the surface shield layer 30, the signal charge stored in the charge storage layer 26 is changed. Reading can be facilitated.

  FIG. 4 is a potential diagram in the vicinity of the gate electrode for explaining the signal charge transfer of the solid-state imaging device according to the present embodiment. FIG. 4A shows a case of a CMOS image sensor having the impurity layer 28 of the present embodiment. FIG. 4B shows a CMOS image sensor having a conventional structure without the impurity layer 28 shown for reference.

  By providing the impurity layer 28, it is possible to suppress the generation of a potential barrier in the channel portion due to the surface shield layer 30. As a result, as shown in FIG. 4A, even when the read voltage Vg applied to the gate electrode 24 is a low voltage of about 3.3 V, for example, at the end of the gate electrode 24 of the charge storage layer 26. The potential can be made sufficiently low as shown by the broken line. That is, all signal charges stored in the charge storage layer 26 can be reliably read out and transferred to the detection unit 28. On the other hand, when the impurity layer 28 is not provided, due to the potential barrier by the surface shield layer 30, as shown in FIG. 4B, when the read voltage is as low as about 3.3V, the charge storage layer The potential at the end of the gate electrode 24 of 26 is not sufficiently low. For this reason, unread reading of the signal charge occurs.

  Therefore, according to the present embodiment, it is possible to provide a high-sensitivity solid-state imaging device that improves signal charge transfer efficiency while realizing low-voltage driving.

  In the above embodiment, the charge storage layer 26 and the surface shield layer 30 are provided in a self-aligned manner with the gate electrode 24, and the solid-state imaging device provided with the impurity layer 28 extending below the gate electrode 24 has been described as an example. However, the present invention is not limited to the above and can be implemented with various modifications. Some examples are shown below, but are not limited thereto.

(Modification 1)
An example of a cross-sectional structure of a CMOS image sensor according to Modification 1 of the present invention is shown in FIG. In the CMOS image sensor 110 of Modification 1, all of the charge storage layer 26, impurity layer 28, and surface shield layer 30 on the gate electrode 24 side are provided in self-alignment with the gate electrode 24. Even with this structure, generation of a potential barrier by the surface shield layer 30 can be sufficiently suppressed.

(Modification 2)
An example of a cross-sectional structure of a CMOS image sensor according to the second modification of the present invention is shown in FIG. In the CMOS image sensor 120 according to the second modification, the surface shield layer 30 and the impurity layer 28 are provided in a self-aligned manner with the gate electrode 24, but the charge storage layer 26 is separated from the gate electrode 24 in a plan view. Is provided. Such a structure can be created, for example, by forming the charge storage layer 26 after providing the gate sidewall (not shown) on the gate electrode 24. Even with this structure, generation of a potential barrier by the surface shield layer 30 can be sufficiently suppressed.

(Modification 3)
An example of a cross-sectional structure of a CMOS image sensor according to the third modification of the present invention is shown in FIG. In the CMOS image sensor 130 of Modification 3, the surface shield layer 30 is provided in a self-aligned manner with the gate electrode 24, but the charge storage layer 26 and the impurity layer 28 extend below the gate electrode 24. Is provided. The tip portions of the charge storage layer 26 and the impurity layer 28 may be at the same position as shown in FIG. 7, or may be at a position where the impurity layer 28 further protrudes. With this structure, generation of a potential barrier due to the surface shield layer 30 can be effectively suppressed.

(Modification 4)
An example of a cross-sectional structure of a CMOS image sensor according to Modification 3 of the present invention is shown in FIG. In the CMOS image sensor 140 of Modification 4, the surface shield layer 30 is provided in a self-aligned manner with the gate electrode 24, but the charge storage layer 26 and the impurity layer 28 extend below the gate electrode 24. In addition, the impurity layer 28 is provided apart from the surface shield layer 30. The tip portions of the charge storage layer 26 and the impurity layer 28 may be at the same position as shown in FIG. 7, or the impurity layer 28 may protrude as shown in FIG. With this structure, generation of a potential barrier by the surface shield layer 30 can be effectively suppressed, and at the same time, leakage current due to contact between the impurity layer 28 and the surface shield layer 30 can be reduced as described below.

  FIG. 9 is a diagram showing the influence of the leakage current generated by the overlap between the impurity layer 28 and the surface shield layer 30. The horizontal axis indicates the width in which the impurity layer 28 and the surface shield layer 30 overlap, and a negative value indicates that the two are separated from each other. The vertical axis shows the leakage current index (ratio of elements having a leakage current equal to or less than a predetermined value) on an arbitrary scale, as in FIG. That is, the larger the leakage current index, the more preferable characteristics. When there is an overlap between the impurity layer 28 and the surface shield layer 30, the leakage current index is 1 or less. However, when the impurity layer 28 and the surface shield layer 30 are provided apart from each other, the leakage current index becomes 2 or more. That is, it is shown that the structure of the modification 4 is a preferable structure for reducing the leakage current due to the overlap.

(Modification 5)
An example of a plan view of a CMOS image sensor 150 according to Modification 5 of the present invention is shown in FIG. Usually, a semiconductor device such as a solid-state imaging device is manufactured on a semiconductor substrate having a (100) plane as a main surface so that one side of a rectangular or square semiconductor device is parallel to the <011> direction. The CMOS image sensor 150 of Modification 5 is arranged so that one side of the semiconductor device is parallel to this <011> direction and a <010> direction inclined by 45 °. By arranging in this way, for example, when mechanical distortion is applied to the semiconductor chip due to packaging or the like, the characteristic fluctuation of the CMOS image sensor 150 due to the difference in distortion amount between the vertical direction and the horizontal direction can be reduced.

(Modification 6)
An example of a plan view of a CMOS image sensor 160 according to the sixth modification of the present invention is shown in FIG. In the CMOS image sensor 160 of this modification, the gate electrode 24 is disposed so as to be inclined by 45 ° with respect to the photoelectric conversion portion including the charge storage layer 26. By arranging in this way, the CMOS image sensor can be densely arranged, which is suitable for high integration. In this modification, the photoelectric conversion unit and the gate electrode 24 need only be arranged so as to be inclined by 45 °. For example, the direction of one side of the photoelectric conversion unit is the <110> direction as in the above embodiment, and the gate The electrode 24 can be provided in the <010> direction as in the fifth modification. Alternatively, the direction of one side of the photoelectric conversion unit may be the <010> direction as in Modification 5, and the gate electrode 24 may be provided in the <110> direction as in the above embodiment.

  As described above, in a solid-state imaging device employing a surface shield structure, such as a CMOS image sensor, an impurity layer is provided between the charge storage layer and the surface shield layer near the gate electrode. This suppresses the generation of a potential barrier by the surface shield layer between the charge storage layer and the channel for signal charge transfer, and reduces all signal charges stored in the charge storage layer to a low read voltage, that is, The gate voltage can be read sufficiently. As a result, it is possible to transfer the signal charge in the charge storage layer to the detection unit without unreading it. Therefore, the read voltage for reading the signal charge stored in the charge storage layer can be lowered. In particular, it is suitable for a CMOS image sensor that requires low voltage driving with a single power source.

  In addition, according to such a configuration, the surface shield layer is provided in order to suppress surface recombination in the vicinity of the surface of the charge storage layer, and the effect of reducing white scratches and dark current is also provided.

  In the above embodiment, the case where the present invention is applied to a CMOS image sensor has been described as an example. However, the present invention is not limited to this and can be applied to solid-state imaging devices having various structures such as a CCD image sensor.

  As described above, according to the present invention, it is possible to provide a high-sensitivity solid-state imaging device that improves signal charge transfer efficiency while realizing low-voltage driving.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments disclosed herein, and can be applied to other embodiments without departing from the spirit of the present invention and can be applied to a wide range. It is.

FIG. 1 is a plan view of a part of a pixel shown for explaining an example of a solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a view for explaining an example of a cross-sectional structure of the solid-state imaging device according to the embodiment of the present invention, and is a cross-sectional view taken along a cutting line indicated by AA in FIG. FIG. 3 is a diagram showing the relationship between the distance between the impurity layer and the element isolation and the leakage current of the solid-state imaging device according to the embodiment of the present invention. FIG. 4 is a potential diagram in the vicinity of the gate electrode for explaining the signal charge transfer of the solid-state imaging device according to the embodiment of the present invention. FIG. 4A shows the case where the impurity layer of the present embodiment is provided. FIG. 4B shows a conventional structure without an impurity layer. FIG. 5 is a diagram illustrating an example of a cross-sectional structure of a solid-state imaging device according to Modification 1 of the present invention. FIG. 6 is a diagram illustrating an example of a cross-sectional structure of a solid-state imaging device according to the second modification of the present invention. FIG. 7 is a diagram illustrating an example of a cross-sectional structure of a solid-state imaging device according to Modification 3 of the present invention. FIG. 8 is a diagram illustrating an example of a cross-sectional structure of a solid-state imaging device according to Modification 4 of the present invention. FIG. 9 is a diagram illustrating an influence of a leakage current generated by the overlap between the impurity layer and the surface shield layer in the solid-state imaging device according to the embodiment of the present invention. FIG. 10 is a plan view showing a part of a pixel of an example of a solid-state imaging device according to Modification 5 of the present invention. FIG. 11 is a plan view showing a part of a pixel of an example of a solid-state imaging device according to Modification 6 of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor wafer, 12 ... p ⁺ semiconductor substrate, 14 ... N-type semiconductor layer, 16 ... Element isolation, 22 ... Gate insulating film, 24 ... Gate electrode, 26 ... Charge storage layer, 28 ... Impurity layer, 30 ... Surface shield Layer, 32... Detection portion, 34... P-type impurity layer.

Claims (5)

A semiconductor substrate having an n-type semiconductor layer on the main surface;
Element isolation including an insulating film and a p-type semiconductor layer provided in the n-type semiconductor layer, and electrically separating adjacent pixel regions;
A gate electrode provided on the surface of the n-type semiconductor layer via a gate insulating film;
An n-type semiconductor charge storage layer provided in the n-type semiconductor layer on one side of the gate electrode and spaced from the surface;
A surface shield layer of a p-type semiconductor provided in the n-type semiconductor layer above the charge storage layer and spaced apart from the charge storage layer, and provided planarly without being separated from the gate electrode;
An n-type semiconductor provided in a part of a region between the charge storage layer and the surface shield layer and including an upper end of the charge storage layer on the gate electrode side and overlapping with the part of the charge storage layer A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the impurity layer is provided apart from the element isolation.   The solid-state imaging device according to claim 1, wherein the impurity layer is provided apart from the surface shield layer.   4. The solid-state imaging device according to claim 1, wherein the charge storage layer is provided without being spaced apart from the gate electrode in a planar manner. 5.   5. The solid-state imaging device according to claim 1, wherein the impurity layer extends below the gate electrode. 6.

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