JP3880579B2 - MOS imaging device - Google Patents

MOS imaging device Download PDF

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JP3880579B2
JP3880579B2 JP2004029352A JP2004029352A JP3880579B2 JP 3880579 B2 JP3880579 B2 JP 3880579B2 JP 2004029352 A JP2004029352 A JP 2004029352A JP 2004029352 A JP2004029352 A JP 2004029352A JP 3880579 B2 JP3880579 B2 JP 3880579B2
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transfer gate
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哲也 板野
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    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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Description

本発明は、ＭＯＳ型の撮像装置に関するものであって、特に、ウェル内に形成される電荷蓄積領域がウェルと同一導電型の不純物領域で形成される撮像装置に関するものである。   The present invention relates to a MOS type imaging device, and more particularly to an imaging device in which a charge storage region formed in a well is formed of an impurity region having the same conductivity type as the well.

従来のＭＯＳ型の撮像装置の概略を説明する。まず、ＭＯＳ型の撮像装置は複数の単位画素が一次元状或いは二次元状に配列されたものであり、単位画素は半導体基板上に光電変換により発生した信号電荷を蓄積するための電荷蓄積部及び信号電荷を転送するための転送ゲート、信号電荷を電圧に変換する浮遊拡散部、信号増幅用のＭＯＳトランジスタを有している。ＭＯＳ型撮像装置は単一電源駆動、低消費電力という点でＣＣＤに対して優位となっている。   An outline of a conventional MOS imaging device will be described. First, a MOS-type imaging device has a plurality of unit pixels arranged one-dimensionally or two-dimensionally, and the unit pixel is a charge storage unit for storing signal charges generated by photoelectric conversion on a semiconductor substrate. And a transfer gate for transferring the signal charge, a floating diffusion part for converting the signal charge into a voltage, and a signal amplification MOS transistor. MOS imaging devices are superior to CCDs in terms of single power supply drive and low power consumption.

近年、イメージセンサの益々の多画素化、小画素化に伴い、高感度化が要求されている。そこで、ＭＯＳ型の撮像装置に関して概略以下に示すような高感度化に対応した構造が考案されている。即ち、第一導電型の半導体基板内の第二導電型のウェル領域内に形成された第一導電型の光電変換部兼電荷蓄積部によって光信号に対応した信号電荷を発生し、蓄積する。つまり、画素内で第一導電型が形成された領域で発生した電荷のみが信号として寄与する。   In recent years, with the increase in the number of pixels and the size of pixels in image sensors, higher sensitivity is required. In view of this, a structure corresponding to high sensitivity has been devised for MOS-type imaging devices as shown below. That is, a signal charge corresponding to the optical signal is generated and accumulated by the first conductivity type photoelectric conversion unit / charge accumulation unit formed in the second conductivity type well region in the first conductivity type semiconductor substrate. That is, only the charges generated in the region where the first conductivity type is formed in the pixel contribute as a signal.

一方、後述する本発明の対象となる構造は、第一導電型の半導体基板内の第一導電型のウェル領域及びウェル領域内に形成された第一導電型の電荷蓄積部によって光信号に対応した信号電荷を発生し、電荷蓄積部に蓄積する。つまり、ウェル領域に入射した光信号によっても信号が得られることによって感度向上を実現する。これは、特に、半導体基板〜デバイス表面までの距離が大きいＭＯＳ型の撮像装置では大きな感度向上が得られる。   On the other hand, the structure which is the subject of the present invention, which will be described later, corresponds to an optical signal by the first conductivity type well region in the first conductivity type semiconductor substrate and the first conductivity type charge storage portion formed in the well region. The generated signal charge is generated and stored in the charge storage section. That is, the sensitivity is improved by obtaining a signal also by the optical signal incident on the well region. In particular, a significant improvement in sensitivity can be obtained in a MOS type imaging apparatus having a large distance from the semiconductor substrate to the device surface.

一般に、ＭＯＳ型撮像装置は第一導電型の電荷蓄積部上に第二導電型の表面シールド層が形成されている。電荷蓄積部は光電変換によって発生した信号電荷を蓄積する必要があるため、その電圧は正電圧に設定する必要がある。特に、画像劣化の原因となる残像を抑えるためには電荷蓄積部として完全空乏化した構造とする構成を用いる必要があり、この場合には、空乏層が表面シールド層方向にも伸びることになるが、基板表面に達するとリーク電流が増加し、画像劣化の原因となる。   In general, in a MOS type imaging device, a second conductivity type surface shield layer is formed on a first conductivity type charge storage section. Since the charge storage unit needs to store signal charges generated by photoelectric conversion, the voltage needs to be set to a positive voltage. In particular, in order to suppress an afterimage that causes image deterioration, it is necessary to use a structure having a fully depleted structure as a charge storage unit. In this case, the depletion layer extends in the direction of the surface shield layer. However, when it reaches the substrate surface, the leakage current increases, causing image degradation.

このため、表面シールド層の部分での不純物濃度は最も高く設計する必要がある。電荷蓄積部からの信号電荷の読み出し時には転送ゲートをオン状態にし、ゲート下の電位を高電圧にする必要があるが、高濃度の表面シールド層の製造時における転送ゲート下への熱拡散により、転送ゲートをオン状態にしても図５に破線で示すようにゲート下にポテンシャル障壁ができ、十分な転送を妨げる原因となり得る。図５において、８０１は半導体基板、８０３はウェル領域、８０４は電荷蓄積部、８０５は表面シールド層、８０６はドレイン領域、８０８は転送ゲートを示す。   For this reason, it is necessary to design the highest impurity concentration in the surface shield layer portion. When reading the signal charge from the charge storage unit, it is necessary to turn on the transfer gate and set the potential under the gate to a high voltage, but due to thermal diffusion under the transfer gate when manufacturing a high concentration surface shield layer, Even if the transfer gate is turned on, a potential barrier is formed under the gate as shown by a broken line in FIG. 5, which may cause a sufficient transfer. In FIG. 5, reference numeral 801 denotes a semiconductor substrate, 803 denotes a well region, 804 denotes a charge storage portion, 805 denotes a surface shield layer, 806 denotes a drain region, and 808 denotes a transfer gate.

これを回避するための手段として、従来、例えば、特開２０００−９１５５１号公報に開示されるような手段が採られている（特許文献１参照）。即ち、図６に示すように電荷蓄積部８０４を転送ゲート８０８の下部にまで延在させることにより、十分な転送を可能にしている。なお、図６では図５と同一部分は同一符号を付して説明を省略する。   As means for avoiding this, conventionally, for example, means disclosed in Japanese Patent Application Laid-Open No. 2000-91551 has been adopted (see Patent Document 1). That is, as shown in FIG. 6, the charge storage portion 804 extends to the lower part of the transfer gate 808, thereby enabling sufficient transfer. In FIG. 6, the same parts as those in FIG.

一方、前述の高感度化に対応した構造では、第一導電型の電荷蓄積部が同じく第一導電型のウェル内に形成されるためウェル領域まで空乏層が伸びる、即ち、完全空乏化させるための印加電圧が高くなりがちである。電荷蓄積部からの信号電荷の読み出し時には転送ゲートをオン状態にし、ゲート下の電位を高電圧にする必要があるが、完全転送読み出しを行うためには電荷蓄積部よりもゲート下の電位が高い電圧になる必要がある。   On the other hand, in the structure corresponding to the above-described high sensitivity, the depletion layer extends to the well region because the first conductivity type charge storage portion is also formed in the first conductivity type well, that is, for complete depletion. The applied voltage tends to be high. When reading signal charges from the charge storage unit, the transfer gate must be turned on and the potential under the gate must be set to a high voltage. However, in order to perform complete transfer reading, the potential under the gate is higher than that of the charge storage unit. It needs to be a voltage.

前述の通り、高感度化に対応した構造では完全空乏化させるための印加電圧が高くなりがちであるため、これを抑えるために電荷蓄積部の不純物濃度は低く設定する必要がある。これにより、特に高感度化に対応した構造の場合には、図７に示すように特にゲート下のポテンシャル障壁（破線で示す）の影響が顕著となり転送経路を妨げることとなるため、もはや十分な転送を行うことが不可能となる。なお、図７において、１０１は半導体基板、１０２は第二導電型領域、１０３は型ウェル領域、１０４は電荷蓄積部、１０５は表面シールド層、１０６は型ドレイン領域、１０７はパンチスルーストッパー領域、１０８は転送ゲート、１０９はゲート酸化膜、１１０は型分離層を示す。
特開２０００−９１５５１号公報 As described above, in the structure corresponding to the high sensitivity, the applied voltage for complete depletion tends to be high. Therefore, in order to suppress this, the impurity concentration of the charge storage portion needs to be set low. As a result, particularly in the case of a structure corresponding to high sensitivity, the influence of a potential barrier (shown by a broken line) under the gate is particularly significant as shown in FIG. It becomes impossible to transfer. In FIG. 7, 101 is a semiconductor substrate, 102 is a second conductivity type region, 103 is a type well region, 104 is a charge storage portion, 105 is a surface shield layer, 106 is a type drain region, 107 is a punch-through stopper region, Reference numeral 108 denotes a transfer gate, 109 denotes a gate oxide film, and 110 denotes a mold isolation layer.
JP 2000-91551 A

上述のように、特に、ウェル内に形成される電荷蓄積領域がウェルと同一導電型の不純物領域で形成される撮像装置においては、表面シールド層によるポテンシャル障壁に起因する転送特性劣化が問題となる。ＭＯＳ型撮像装置にあっては、単一電源駆動、低消費電力という利点を保ちつつ高い性能を得るためには上記構造において良好な転送特性を得ることが必須となっていた。   As described above, particularly in an imaging device in which the charge storage region formed in the well is formed of an impurity region of the same conductivity type as the well, transfer characteristic deterioration due to the potential barrier due to the surface shield layer becomes a problem. . In the MOS type imaging device, in order to obtain high performance while maintaining the advantages of single power supply driving and low power consumption, it is essential to obtain good transfer characteristics in the above structure.

本発明は、上記従来の事情に鑑みなされたもので、その目的は、高感度且つ良好な転送特性を有するＭＯＳ型撮像装置を提供することにある。   The present invention has been made in view of the above-described conventional circumstances, and an object thereof is to provide a MOS type imaging device having high sensitivity and good transfer characteristics.

本発明は、上記目的を達成するため、特に、ウェル内に形成される電荷蓄積領域がウェルと同一導電型の不純物領域で形成されるＭＯＳ型撮像装置において顕著となる表面シールド層によるポテンシャル障壁に起因する転送特性劣化を抑えるために電荷蓄積部の一部を転送ゲート電極の直下であって、且つ、転送ゲート電極下のシリコン−ゲート酸化膜界面から離れた深さに形成する。また、電荷蓄積部は、複数回のイオン注入により形成する。転送ゲート電極の直下に設けられた電荷蓄積部の一部は、複数回のイオン注入により、一回目のイオン注入で形成されるよりも不純物濃度が高くなるように形成する。 In order to achieve the above object, the present invention provides a potential barrier due to a surface shield layer that becomes prominent particularly in a MOS type imaging device in which a charge storage region formed in a well is formed of an impurity region of the same conductivity type as the well. In order to suppress the transfer characteristic deterioration due to this, a part of the charge storage portion is formed immediately below the transfer gate electrode and at a depth away from the silicon-gate oxide film interface under the transfer gate electrode. The charge storage portion is formed by a plurality of ion implantations. A part of the charge storage portion provided immediately below the transfer gate electrode is formed by a plurality of ion implantations so that the impurity concentration is higher than that formed by the first ion implantation.

本構造の場合、電荷蓄積領域がウェルと同一導電型の不純物領域で形成されているため、電荷蓄積領域がウェルと異なる導電型の不純物領域で形成されている場合と比較して電荷蓄積部の一部を転送ゲート電極の直下にまで延ばすことの転送特性に対する影響は大である。   In the case of this structure, the charge storage region is formed of an impurity region having the same conductivity type as that of the well. Therefore, the charge storage region is formed of an impurity region having a conductivity type different from that of the well. The effect on the transfer characteristics of extending a part of the transfer gate electrode just below the transfer gate electrode is significant.

また、本構造、即ち、転送ゲート下に電荷蓄積部を潜り込ませる手段として（ポリシリコンゲート規定での斜めイオン注入を行わず）ポリシリコンゲート形成前にマスク規定で転送ゲート電極に対して食い込み、逃がしのほとんどない、即ち、半導体基板に対して垂直に近い角度にて注入を行う。   In addition, as a means for causing the charge storage portion to sneak under the transfer gate (without performing oblique ion implantation in accordance with the polysilicon gate definition), the bite into the transfer gate electrode in accordance with the mask specification before forming the polysilicon gate, Implantation is performed with almost no escape, that is, at an angle close to perpendicular to the semiconductor substrate.

これは、次のような理由による。特に、画素サイズの小さなセンサに関して、転送ゲート下に電荷蓄積部を潜り込ませる手段としてポリシリコンゲートに対して自己整合的なイオン注入により斜め注入を行う場合には、図８に示すようにマスクとなるレジストに陰れるために電荷蓄積部となる第一導電型の不純物領域が所望の大きさに形成されない。即ち、実際に形成される電荷蓄積部１０４は本来の所望の電荷蓄積部の大きさに対して小さくなる。   This is due to the following reason. In particular, regarding a sensor having a small pixel size, when oblique implantation is performed by self-aligned ion implantation with respect to a polysilicon gate as a means for causing a charge storage portion to enter under a transfer gate, a mask and a mask as shown in FIG. Therefore, the impurity region of the first conductivity type serving as the charge storage portion is not formed in a desired size. That is, the actually formed charge storage portion 104 is smaller than the original desired charge storage portion.

そこで、図９に示すようにポリシリコンゲート形成前に半導体基板に対して垂直に近い角度でイオン注入を行う。これにより、所望の大きさの電荷蓄積部と実際の電荷蓄積部の大きさが同じとなる。なお、図８、図９において図７と同一部分は同一符号を付している。   Therefore, as shown in FIG. 9, ion implantation is performed at an angle close to perpendicular to the semiconductor substrate before forming the polysilicon gate. As a result, the charge storage unit having a desired size and the actual charge storage unit have the same size. 8 and 9, the same parts as those in FIG. 7 are denoted by the same reference numerals.

本発明によれば、表面シールド層でのポテンシャル障壁の影響を回避し、転送経路を確保することにより良好な転送特性を得ることができる。また、マスク規定での電荷蓄積部のイオン注入を行うことによりシャドーイングの悪影響を受けず、電荷蓄積部の面積を減少させることなく良好な転送特性が得られる。また、転送ゲート酸化膜−シリコン界面で発生する暗電流成分を電荷蓄積部に取り込まないような構成となるため、信号上での暗電流成分を減少させ得る。   According to the present invention, good transfer characteristics can be obtained by avoiding the influence of the potential barrier in the surface shield layer and securing the transfer path. In addition, by performing ion implantation of the charge accumulating portion according to the mask definition, good transfer characteristics can be obtained without being adversely affected by shadowing and without reducing the area of the charge accumulating portion. Further, since the dark current component generated at the transfer gate oxide film-silicon interface is not taken into the charge storage portion, the dark current component on the signal can be reduced.

更に、転送ゲートに対して食い込み、逃がしのない注入条件を用いるため、例えば、浮遊拡散部を共通とする画素構成に関して、電荷蓄積部−転送ゲート−浮遊拡散部の位置関係が対称なレイアウト構成であっても１枚の電荷蓄積部形成用のマスクにて形成することが可能である。   Further, since the implantation conditions that bite into the transfer gate and do not escape are used, for example, in a pixel configuration having a common floating diffusion portion, the layout configuration in which the positional relationship between the charge storage portion, the transfer gate, and the floating diffusion portion is symmetrical. Even in such a case, it can be formed with a single mask for forming the charge storage portion.

次に、発明を実施するための最良の形態について図面を参照して詳細に説明する。   Next, the best mode for carrying out the invention will be described in detail with reference to the drawings.

（第１の実施形態）
図１は本発明による撮像装置の第１の実施形態を示す断面図である。まず、第一導電型の半導体基板２０１内に一様な第二導電型領域２０２、均一な第一導電型ウェル領域２０３が形成されている。この構造は、第二導電型不純物のイオン注入或いは第一導電型のエピタキシャル成長によって形成されている。また、均一な第一導電型ウェル領域２０３内に第一導電型の電荷蓄積部２０４と電荷蓄積部２０４上に形成された第二導電型の表面シールド層２０５が形成されている。なお、２０９はシリコンゲート酸化膜を示す。 (First embodiment)
FIG. 1 is a sectional view showing a first embodiment of an imaging apparatus according to the present invention. First, a uniform second conductivity type region 202 and a uniform first conductivity type well region 203 are formed in a first conductivity type semiconductor substrate 201. This structure is formed by ion implantation of a second conductivity type impurity or epitaxial growth of the first conductivity type. Also, a first conductivity type charge accumulation portion 204 and a second conductivity type surface shield layer 205 formed on the charge accumulation portion 204 are formed in the uniform first conductivity type well region 203. Reference numeral 209 denotes a silicon gate oxide film.

本実施形態では、上述のように顕著となる表面シールド層２０５によるポテンシャル障壁に起因する転送特性劣化を抑えるため、電荷蓄積部２０４の一部が転送ゲート電極２０８の直下であって、且つ、転送ゲート電極２０８下のシリコン−ゲート酸化膜２０９の界面から離れた深さに形成している。   In this embodiment, in order to suppress transfer characteristic deterioration due to the potential barrier due to the surface shield layer 205 as described above, a part of the charge accumulation unit 204 is directly below the transfer gate electrode 208 and the transfer is performed. It is formed at a depth away from the silicon-gate oxide film 209 interface under the gate electrode 208.

また、転送ゲート２０８下に電荷蓄積部２０４を潜り込ませる手段として（ポリシリコンゲート規定での斜めイオン注入を行わず）、図９で説明したようにポリシリコンゲート形成前にマスク規定で転送ゲート電極２０８に対して食い込み、逃がしのほとんどない、即ち、半導体基板に対して垂直に近い角度にて注入を行う。   Further, as a means for letting the charge accumulating portion 204 enter under the transfer gate 208 (without performing oblique ion implantation for defining the polysilicon gate), as described with reference to FIG. The implantation is carried out at an angle that bites into 208 and has almost no escape, that is, an angle close to perpendicular to the semiconductor substrate.

本実施形態の図７との違いは、表面シールド層２０５の部分での不純物濃度は最も高く、電荷蓄積部２０４が完全に空乏化した状態において空乏層は基板表面に達しない。これにより、画像劣化の原因となるリーク電流を蓄積しない構造となっている。本構造において、転送ゲート２０８をオン状態にした場合の電荷蓄積部２０４からの信号電荷の転送経路を矢印で示す。   The difference from FIG. 7 of the present embodiment is that the impurity concentration in the portion of the surface shield layer 205 is the highest, and the depletion layer does not reach the substrate surface in a state where the charge storage portion 204 is completely depleted. As a result, the leak current that causes image degradation is not accumulated. In this structure, a signal charge transfer path from the charge storage unit 204 when the transfer gate 208 is turned on is indicated by an arrow.

このように表面シールド層２０５でのポテンシャル障壁の影響を回避し転送経路を確保することにより良好な転送特性を得ることができる。また、第一導電型の電荷蓄積部と同じく第一導電型のドレイン領域２０６との導通を防ぐための第二導電型で形成されたパンチスルーストッパー領域２０７を有している。   In this way, good transfer characteristics can be obtained by avoiding the influence of the potential barrier in the surface shield layer 205 and securing the transfer path. Further, it has a punch-through stopper region 207 formed of the second conductivity type for preventing conduction with the first conductivity type drain region 206 as well as the first conductivity type charge storage portion.

また、画素間或いは素子間の分離のための第二導電型の分離層２１０を有する。パンチスルーストッパー領域２０７及び画素間、素子間の分離のための第二導電型の分離層２１０は本実施形態では注入エネルギーの異なる３回のイオン注入により形成されているが、本発明は３回に限るものではない。本実施形態では、例えば、１２００ＫｅＶ、５００ＫｅＶ、８０ＫｅＶのエネルギーでイオン注入されている。   In addition, a separation layer 210 of a second conductivity type for separation between pixels or elements is provided. In this embodiment, the punch-through stopper region 207 and the second conductive type separation layer 210 for separation between pixels and elements are formed by three times of ion implantation with different implantation energies. It is not limited to. In this embodiment, for example, ions are implanted with an energy of 1200 KeV, 500 KeV, and 80 KeV.

（第２の実施形態）
図２は本発明の第２の実施形態を示す断面図である。なお、図２では図１と同一部分は同一符号を付している。第１の実施形態との違いは、電荷蓄積領域に追加でイオン注入されている点である（図中２０４′で示す）。この２０４′は電荷蓄積部２０４と同様に行う。これにより、転送ゲート２０８直下の第一導電型の不純物濃度を濃くすることで表面シールド層２０５でのポテンシャル障壁の影響を受けにくくし、更に良好な転送特性が得られる。その他の構造は図１と同様である。 (Second Embodiment)
FIG. 2 is a cross-sectional view showing a second embodiment of the present invention. In FIG. 2, the same parts as those in FIG. The difference from the first embodiment is that ions are additionally implanted into the charge storage region (indicated by 204 'in the figure). This 204 ′ is performed in the same manner as the charge storage unit 204. As a result, by increasing the impurity concentration of the first conductivity type immediately below the transfer gate 208, it is less affected by the potential barrier in the surface shield layer 205, and better transfer characteristics can be obtained. Other structures are the same as those in FIG.

（第３の実施形態）
図３は本発明の第３の実施形態を示す断面図である。図３では図２と同一部部は同一符号を付している。第２の実施形態との違いは、追加でイオン注入する電荷蓄積領域（２０４′で示す）を、図８で説明した方法を用いて転送ゲートに対して自己整合的なイオン注入により形成する点である。これにより、電荷蓄積部の面積を減少させることなく、且つ、アライメントずれに起因する転送不良を回避した良好な転送特性を得ることが可能である。 (Third embodiment)
FIG. 3 is a sectional view showing a third embodiment of the present invention. 3, the same parts as those in FIG. 2 are denoted by the same reference numerals. The difference from the second embodiment is that a charge storage region (indicated by 204 ′) for additional ion implantation is formed by ion implantation that is self-aligned with the transfer gate using the method described in FIG. It is. As a result, it is possible to obtain good transfer characteristics without reducing the area of the charge storage unit and avoiding transfer defects due to misalignment.

（第４の実施形態）
図４は本発明の第４の実施形態を示す断面図である。図４では図１と同一部分は同一符号を付している。第１の実施形態との違いは、電荷蓄積領域２０４は垂直イオン注入であるが、転送ゲート２０８の形成後にイオン注入したものであり、図１〜図３の電荷蓄積部２０４に比べて小さくなっている。また、追加でイオン注入する電荷蓄積領域２０４′は図８で説明した方法を用いて転送ゲート２０８に対して自己整合的なイオン注入により形成した点である。これにより、電荷蓄積部の面積を減少させることなく、且つ、アライメントずれに影響されることのない電荷蓄積部の形成を行うことが可能となる。 (Fourth embodiment)
FIG. 4 is a sectional view showing a fourth embodiment of the present invention. 4, the same parts as those in FIG. 1 are denoted by the same reference numerals. The difference from the first embodiment is that the charge accumulation region 204 is vertical ion implantation, but is ion-implanted after the transfer gate 208 is formed, which is smaller than the charge accumulation unit 204 of FIGS. ing. Further, the additional charge storage region 204 ′ for ion implantation is formed by self-aligned ion implantation with respect to the transfer gate 208 using the method described with reference to FIG. As a result, it is possible to form the charge storage unit without reducing the area of the charge storage unit and without being affected by the misalignment.

本発明の撮像装置の第１の実施形態を示す断面図である。It is sectional drawing which shows 1st Embodiment of the imaging device of this invention. 本発明の第２の実施形態を示す断面図である。It is sectional drawing which shows the 2nd Embodiment of this invention. 本発明の第３の実施形態を示す断面図である。It is sectional drawing which shows the 3rd Embodiment of this invention. 本発明の第４の実施形態を示す断面図である。It is sectional drawing which shows the 4th Embodiment of this invention. 従来のゲート下のポテンシャル障壁による転送を妨げる様子を示す図である。It is a figure which shows a mode that the transfer by the potential barrier under the conventional gate is prevented. 図５の課題を解決する従来方法を説明する図である。It is a figure explaining the conventional method which solves the subject of FIG. 従来の高感度化に対応した構造の課題を説明する図である。It is a figure explaining the subject of the structure corresponding to the conventional high sensitivity. ポリシリコンゲートに対して自己整合的なイオン注入により斜め入射を行う場合の電荷蓄積部が所望の大きさに形成されない様子を示す図である。It is a figure which shows a mode that the electric charge storage part in the case of performing oblique incidence by self-aligned ion implantation with respect to a polysilicon gate is not formed in a desired size. ポリシリコンゲート形成前に半導体基板に対して垂直に近い角度でイオン注入を行う様子を示す図である。It is a figure which shows a mode that ion implantation is carried out at the angle near perpendicular | vertical with respect to a semiconductor substrate before polysilicon gate formation.

符号の説明Explanation of symbols

２０１ 半導体基板
２０２ 一様な第二導電型領域
２０３ ウェル領域
２０４、２０４′ 電荷蓄積部
２０５ 表面シールド層
２０６ ドレイン領域
２０７ パンチスルーストッパー領域
２０８ 転送ゲート
２０９ ゲート酸化膜
２１０ 分離層 201 Semiconductor substrate 202 Uniform second conductivity type region 203 Well region 204, 204 'Charge storage portion 205 Surface shield layer 206 Drain region 207 Punch-through stopper region 208 Transfer gate 209 Gate oxide film 210 Separation layer

Claims (7)

第一導電型半導体領域内に形成された第一導電型半導体からなる電荷蓄積部と、前記電荷蓄積部上に形成された第二導電型半導体からなる表面シールド層と、前記電荷蓄積部の電荷を読み出すための転送ゲート電極と、前記転送ゲート電極の前記電荷蓄積部に対して他端に位置した第一導電型半導体からなるドレイン領域とを有するＭＯＳ型撮像装置において、
前記電荷蓄積部の一部が前記転送ゲート電極の直下にあり、且つ、前記転送ゲート電極下のシリコン−ゲート酸化膜界面から離れた深さに形成されており、
前記電荷蓄積部は、複数回のイオン注入により形成されており、
前記転送ゲート電極の直下に設けられた前記電荷蓄積部の一部は、複数回のイオン注入により、一回目のイオン注入で形成されるよりも不純物濃度が高くなるように形成されていることを特徴とするＭＯＳ型撮像装置。 A charge accumulation portion made of a first conductivity type semiconductor formed in the first conductivity type semiconductor region; a surface shield layer made of a second conductivity type semiconductor formed on the charge accumulation portion; and a charge of the charge accumulation portion In a MOS imaging device having a transfer gate electrode for reading out and a drain region made of a first conductivity type semiconductor located at the other end with respect to the charge storage portion of the transfer gate electrode,
A portion of the charge storage portion is directly under the transfer gate electrode and formed at a depth away from the silicon-gate oxide film interface under the transfer gate electrode;
The charge storage part is formed by multiple ion implantations,
A part of the charge storage portion provided immediately below the transfer gate electrode is formed to have a higher impurity concentration by a plurality of ion implantations than that formed by the first ion implantation. Characteristic MOS type imaging device. 前記電荷蓄積部は、前記第一導電型半導体領域より不純物濃度が高いことを特徴とする請求項１に記載のＭＯＳ型撮像装置。 The MOS type imaging device according to claim 1, wherein the charge accumulation unit has an impurity concentration higher than that of the first conductive semiconductor region. 前記第一導電型半導体領域はウエル領域であり、該ウエル領域は第二導電型半導体領域上に形成されており、該第二導電型半導体領域は第一導電型の半導体基板上に形成されていることを特徴とする請求項１に記載のＭＯＳ型撮像装置。 The first conductivity type semiconductor region is a well region, the well region is formed on a second conductivity type semiconductor region, and the second conductivity type semiconductor region is formed on a first conductivity type semiconductor substrate. The MOS type imaging device according to claim 1, wherein 前記電荷蓄積部と前記ドレイン領域との導通を防ぐための第二導電型半導体からなるパンチスルーストッパー領域を有することを特徴とする請求項１〜３のいずれかに記載のＭＯＳ型撮像装置。 4. The MOS type imaging device according to claim 1, further comprising a punch-through stopper region made of a second conductivity type semiconductor for preventing conduction between the charge storage portion and the drain region. 前記第一導電型半導体領域内の各画素間を分離する位置に第二導電型半導体からなる分離層を有することを特徴とする請求項１〜４のいずれかに記載のＭＯＳ型撮像装置。 5. The MOS image pickup device according to claim 1, further comprising: a separation layer made of a second conductivity type semiconductor at a position for separating pixels in the first conductivity type semiconductor region. 前記転送ゲート電極形成前に前記電荷蓄積部を形成することを特徴とする請求項１〜５のいずれかに記載のＭＯＳ型撮像装置。 6. The MOS type image pickup device according to claim 1, wherein the charge storage portion is formed before the transfer gate electrode is formed. 前記電荷蓄積部を形成する際の複数のイオン注入は同一のマスクにより形成することを特徴とする請求項６に記載のＭＯＳ型撮像装置。 7. The MOS type image pickup device according to claim 6, wherein the plurality of ion implantations for forming the charge storage portion are formed by the same mask.
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