JP2008119106A - Graphics lsi and synchronous reproduction method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively curtail the number of output terminals of the CPU necessary for the connection of devices. <P>SOLUTION: A graphics LSI 3 is provided which is connected both to the CPU 1 and to an audio LSI 6 through a bus. The graphics LSI has an audio housing area for hosing audio system execution information sent from the CPU into a housing destination address and a transfer circuit 33b which reads out the audio system execution information housed in the audio housing area to be transferred to a register 62 on the side of the audio LSI. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an integrated system that includes a graphic LSI controlled by a CPU and an audio LSI, and reproduces images and sounds synchronously.

  Conventionally, in a system for controlling a gaming machine such as a pachinko machine, a graphic LSI (Large Scale Integration) and an audio LSI are provided in parallel with a CPU (Central Processing Unit). Graphic system execution information (parameters and commands) issued by the CPU is transferred to the graphic LSI via a bus connecting the CPU and the graphic LSI. The audio system execution information issued by the CPU is transferred to the audio LSI via a bus connecting the CPU and the audio LSI. The CPU controls these LSIs to reproduce images and sounds synchronously.

  Patent Document 1 discloses a configuration in which a display control board is connected to a subsequent stage of a game control board on which a CPU is mounted and a voice control board is connected to a subsequent stage of the display control board as a control circuit of a pachinko gaming machine. Yes. A special game such as image display and sound output is controlled based on a command sent from the game control board. At that time, the display control board transfers the command sent from the display control game control board to the voice control board according to the type.

  Further, Patent Document 2 has a configuration in which an image processing device is connected to a subsequent stage of a CPU, and an LCD and a sound source LSI are commonly connected (in parallel connection) to the same bus at the subsequent stage (output side) of the image processing apparatus. It is disclosed. This bus is originally intended to supply a display image to the LCD, but data transfer to the sound source LSI via this bus is performed using the horizontal blank period generated when the horizontal line to be scanned is switched. Done. In such a configuration, it is not necessary to directly connect the sound source LSI to the CPU, so that the number of output terminals of the CPU can be reduced as compared with the case where it is directly connected to the CPU.

JP 2004-16281 A JP 2004-29440 A

  As mentioned in Patent Document 2, when two devices such as a graphic LSI and an audio LSI are directly connected to the CPU, as many output terminals as the number of lines constituting these connection buses are required. There is an inconvenience that the number of terminals is increased. In Patent Document 2, such an inconvenience is solved by connecting both the LCD and the sound source LSI to the output bus of the image processing apparatus. However, since not only data transfer to the sound source LSI but also display image transfer is performed on the same bus, there is a temporal restriction that data transfer to the sound source LSI can be performed only in the horizontal blank period. Due to such restrictions, when the amount of data to be transferred to the sound source LSI is large, a situation occurs in which necessary data cannot be transferred in a lump and must be transferred in pieces. As a result, new problems such as reduced transfer efficiency and complicated transfer control are caused.

  The present invention has been made in view of such circumstances, and an object thereof is to effectively reduce the number of CPU terminals required for device connection.

  Another object of the present invention is to increase the efficiency of device control and to shorten the CPU occupation time required for the access.

  Another object of the present invention is to suppress a reduction in transfer efficiency and a complicated transfer control with respect to data transfer to an audio LSI.

  Furthermore, another object of the present invention is to improve controllability related to synchronous reproduction of images and sounds.

  In order to solve such a problem, a first invention provides a graphic LSI connected to a CPU via a first bus. The graphic LSI includes a first storage unit, a second storage unit, a graphic processing unit, and a transfer circuit. The first storage unit has a graphic system storage area and an audio system storage area. In the graphic storage area, an address range as a storage destination of graphic execution information for causing the graphic LSI to perform image reproduction processing is assigned in advance, and a storage destination address designated by the CPU within this assigned address range is assigned. The graphic system execution information issued by the CPU is stored. The audio system storage area is a storage location of audio system execution information to be performed by the audio LSI, and an address range different from the storage system of the graphic system execution information is allocated in advance, and is specified by the CPU within the allocated address range. The audio system execution information issued by the CPU is stored at the stored address. The second storage unit is a storage unit that is provided to store the display image and is different from the first storage unit. The graphic processing unit performs an image reproduction process according to the graphic system execution information stored in the graphic system storage area in the first storage unit, and writes the display image generated by this process in the second storage unit. At the same time, the graphic processing unit outputs the display image read from the second storage unit to the output device via a second bus different from the first bus. The transfer circuit stores audio system execution information stored in the audio system storage area in the first storage unit in response to a transfer instruction from the CPU in order to cause the audio LSI to perform sound reproduction processing according to the audio system execution information. Are transferred to the audio LSI asynchronously with the output of the display image by the graphic processing unit via a third bus different from the first bus and the second bus.

  Here, in the first invention, the first storage unit stores a transfer flag indicating whether or not audio system execution information is being transferred from the audio system storage area to the audio LSI, and is a flag accessible by the CPU. You may further have a storage area. In this case, when the transfer from the audio system storage area to the audio LSI is being performed, the transfer circuit sets the transfer flag to a status indicating that the audio system execution information is being transferred, so that the CPU executes Access to the audio storage area is prohibited. Further, the transfer circuit sets the transfer flag to a status indicating that the audio system execution information is not being transferred when the transfer from the audio system storage area to the audio LSI is not performed, whereby the audio system by the CPU is set. Allow access to storage area.

  In the first invention, the first storage unit may further include a transfer system storage area for storing transfer parameters issued by the CPU and instructing transfer contents of the audio system execution information. In this case, the transfer circuit executes the transfer of the audio system execution information with the transfer contents corresponding to the transfer parameters stored in the transfer system storage area. This transfer parameter may include an instruction of the transfer size of the audio system execution information read from the audio system storage area.

  According to a second aspect of the present invention, there is provided a synchronous reproduction method for synchronously reproducing images and sounds in an integrated system having a CPU, a graphic LSI connected to the CPU via a first bus, and an audio LSI. In this synchronous reproduction method, the CPU issues graphic execution information with designation of a storage destination address within a pre-assigned address range as a storage destination of graphic execution information that causes the graphic LSI to perform image reproduction processing. A second step of storing the graphic system execution information issued by the CPU in a storage location designated by the CPU in the graphic system storage area of the first storage unit in the graphic LSI, An image reproduction process corresponding to the graphic system execution information stored in the graphic system storage area of the storage unit is performed, and a display image generated by this process is displayed on a second different from the first storage unit in the graphic LSI. A third step of writing to the storage unit, and a display image read from the second storage unit Graphic system execution information as a storage location for the fourth step of outputting to the output device via a second bus different from the first bus and the audio system execution information for causing the audio LSI to perform audio reproduction processing. A fifth step in which the CPU issues audio system execution information with designation of the storage destination address within a pre-assigned address range different from the storage destination of the storage destination in the audio storage area of the first storage unit A sixth step of storing the audio system execution information issued by the CPU in a storage location designated by the CPU, and a transfer from the CPU to cause the audio LSI to perform a sound reproduction process according to the audio system execution information. In response to the instruction, the audio system execution information stored in the audio system storage area is transferred to the first bus and the second bus. Via a different third bus, asynchronously with the output of the display image by the graphic processor, and a seventh step of transferring the audio LSI.

  Here, in the second invention, the first storage unit stores a transfer flag indicating whether or not audio system execution information is being transferred from the audio system storage area to the audio LSI, and is a CPU accessible flag. You may further have a storage area. In this case, when the transfer from the audio system storage area to the audio LSI is being performed, the seventh step sets the transfer flag to the first status indicating that the audio system execution information is being transferred. Thus, the step of prohibiting the CPU from accessing the audio system storage area, and if the transfer from the audio system storage area to the audio LSI is not performed, the transfer flag is set so that the audio system execution information is not being transferred. It is preferable to have a step of permitting the CPU to access the audio system storage area by setting the second status to be indicated.

  In the second invention, the first storage unit may further include a transfer system storage area for storing transfer parameters issued by the CPU and instructing transfer contents of the audio system execution information. In this case, it is preferable that the seventh step is a step of executing the transfer of the audio system execution information with the transfer contents according to the transfer parameter stored in the transfer system storage area. The transfer parameter may include an instruction for the transfer size of the audio system execution information read from the audio system storage area.

  A third invention provides a graphic LSI connected to a CPU via a first bus. The graphic LSI includes a graphic system storage area, a first audio system storage area, a second audio system storage area, a graphic processing unit, and a transfer circuit. In the graphic storage area, an address range as a storage destination of graphic execution information for causing the graphic LSI to perform image reproduction processing is assigned in advance, and a storage destination address designated by the CPU within this assigned address range is assigned. The graphic system execution information issued by the CPU is stored. In the first audio storage area, an address range different from the storage destination of the graphic system execution information is assigned in advance as a storage destination of the audio system execution information for causing the audio LSI to perform sound reproduction processing. Audio system execution information issued by the CPU is stored at a storage destination address designated by the CPU within the address range. The second audio system storage area is assigned an address range in advance, and stores read information transferred from the audio LSI. The graphic processing unit performs image reproduction processing according to graphic system execution information stored in the graphic system storage area. The transfer circuit transfers the audio system execution information stored in the first audio system storage area to the audio LSI via a second bus different from the first bus in response to a transfer instruction from the CPU. Alternatively, read information read from the audio LSI is transferred to the second audio storage area via the second bus.

  Here, in the third invention, the information processing apparatus may further include a transfer system storage area in which transfer parameters issued by the CPU and instructing transfer contents of the audio system execution information are stored. In this case, the transfer circuit transfers the audio system execution information stored in the first audio system storage area to the audio LSI when the write transfer is instructed by the transfer parameter stored in the transfer system storage area. To do. The transfer circuit transfers read information read from the audio LSI to the second audio system storage area when the read transfer is instructed by the transfer parameter stored in the transfer system storage area.

  In the third invention, a first transfer flag indicating whether or not audio execution information is being transferred from the first audio system storage area to the audio LSI, and read information from the audio LSI to the second audio system storage area It may further have a flag storage area accessible by the CPU for storing a second transfer flag indicating whether or not is being transferred. In this case, when the transfer from the first audio system storage area to the audio LSI is performed, the transfer circuit sets the first transfer flag to a status indicating that the audio system execution information is being transferred. As a result, access to the first audio system storage area by the CPU is prohibited, and when the transfer from the first audio system storage area to the audio LSI is not performed, the first transfer flag is set to the audio system. By setting the status indicating that the execution information is not being transferred, access to the first audio storage area by the CPU is permitted. The transfer circuit sets the second transfer flag to a status indicating that the read information is being transferred when transfer from the audio LSI to the second audio system storage area is being performed. When the access to the second audio system storage area by the CPU is prohibited and the transfer from the audio LSI to the second audio system storage area is not performed, the read information is being transferred as the second transfer flag. By setting the status to indicate not, access to the second audio system storage area by the CPU is permitted.

  According to a fourth aspect of the present invention, there is provided a synchronous reproduction method for synchronously reproducing images and sounds in an integrated system having a CPU, a graphic LSI connected to the CPU via a first bus, and an audio LSI. In this synchronous reproduction method, the CPU issues graphic execution information with designation of a storage destination address within a pre-assigned address range as a storage destination of graphic execution information that causes the graphic LSI to perform image reproduction processing. A second step of storing graphic system execution information issued by the CPU in a storage location specified by the CPU in the graphic system storage area of the graphic LSI, and a graphic stored in the graphic system storage area A third step for performing image reproduction processing according to system execution information and a pre-assigned address different from the storage location for graphic system execution information as a storage location for audio system execution information for causing audio LSI to perform sound reproduction processing Within the range, the CPU The audio system execution information issued by the CPU to the storage location specified by the CPU in the first audio system storage area of the graphic LSI. The fifth step of storing and the audio stored in the first audio system storage area in order to cause the audio LSI to perform a sound reproduction process according to the audio system execution information when the CPU instructs writing and transfer. A sixth step of transferring the system execution information to the audio LSI via a second bus different from the first bus; and read information read from the audio LSI when the CPU instructs reading and transferring Is transferred to the second audio system storage area of the graphic LSI via the second bus. , And a seventh step of accessing the second audio system storage area CPU designates an address.

  Here, in the fourth invention, when transfer from the first audio system storage area to the audio LSI is performed, access to the first audio system storage area by the CPU is prohibited and the first When the transfer from the audio system storage area to the audio LSI is not performed, an eighth step of permitting access to the first audio system storage area by the CPU, and the second audio system storage from the audio LSI When transfer to the area is performed, access to the second audio system storage area by the CPU is prohibited and transfer from the audio LSI to the second audio system storage area is not performed. May further include a ninth step of permitting access to the second audio system storage area by the CPU.

  According to a fifth aspect of the present invention, there is provided a synchronous reproduction method for synchronously reproducing images and sounds in an integrated system having a CPU, a graphic LSI connected to the CPU via a first bus, and an audio LSI. In this synchronous reproduction method, the graphic system execution information for causing the graphic LSI to perform image reproduction processing is sent through the first step, and the graphic system execution information issued by the CPU is sent via the first bus. The second step of storing in the storage unit of the graphic LSI, the third step of performing image processing according to the graphic system execution information stored in the storage unit, and the audio LSI executing the audio reproduction command A fourth step issued by the CPU for the sound reproduction parameters necessary for performing, a fifth step for storing the sound reproduction parameters issued by the CPU in the storage unit via the first bus, and the CPU. Is instructed to start the transfer of audio playback parameters, the audio playback parameters stored in the storage unit are A sixth step of setting the sound reproduction parameter in the audio LSI by transferring to the audio LSI via a second bus different from the first bus, and after the transfer of the sound reproduction parameter to the audio LSI is completed. The seventh step in which the CPU issues a voice playback command for instructing the start of voice playback, and the voice playback command issued by the CPU via the first bus, the graphic LSI, and the second bus. Then, by transferring to the audio LSI, an eighth step of causing the audio LSI to execute a sound reproduction process in accordance with the designation of the sound reproduction parameter transferred previously is included.

  A sixth invention provides a synchronous reproduction method for synchronously reproducing images and sounds in an integrated system having a CPU, a graphic LSI connected to the CPU via a first bus, and an audio LSI. In this synchronous reproduction method, the graphic system execution information for causing the graphic LSI to perform image reproduction processing is sent through the first step, and the graphic system execution information issued by the CPU is sent via the first bus. The second step of storing in the storage unit of the graphic LSI, the third step of performing image processing according to the graphic system execution information stored in the storage unit, and the audio LSI executing the audio reproduction command A fourth step in which the CPU issues a plurality of audio reproduction parameters necessary for performing time division by the CPU, and a plurality of audio reproduction parameters issued by the CPU in time division via the first bus. If the CPU instructs to start the transfer of audio playback parameters, the storage unit stores the A sixth step of setting the audio reproduction parameters in the audio LSI by transferring the plurality of audio reproduction parameters to the audio LSI through a second bus different from the first bus; After the batch transfer of the audio playback parameters to the LSI is completed, a seventh step in which the CPU issues a voice playback command for instructing the start of voice playback, and the voice playback command issued by the CPU in the first bus And an eighth step of causing the audio LSI to execute audio reproduction processing in accordance with the designation of the audio reproduction parameter previously transferred by transferring to the audio LSI via the graphic LSI and the second bus. Have

  Here, in the fifth or sixth invention, the eighth step is a step of storing the voice reproduction command issued by the CPU in the storage unit via the first bus, and the step of storing the voice reproduction command by the CPU. A step of transferring the voice reproduction command stored in the storage unit to the audio LSI via the second bus when the transfer start is instructed.

  According to the first or second invention, the audio system execution information issued by the CPU is transferred to the audio LSI via the graphic LSI. Therefore, audio system execution information can be transferred to the audio LSI without directly connecting the audio LSI to the CPU. As a result, when the audio LSI is not directly connected, the number of CPU terminals can be reduced by the number required for the connection.

  According to the first or second invention, the audio system execution information to be transferred to the audio LSI is temporarily buffered in the first audio system storage area on the graphic LSI side. As a result, the efficiency of device control of the graphic LSI and audio LSI can be improved, and the CPU occupation time required for device access can be shortened. In particular, in the graphic LSI, the address range of a register serving as a storage destination is divided in advance for each type of execution information (graphic system / audio system). Therefore, the transfer target to the audio LSI can be specified only by the CPU specifying the storage destination address, and the graphic LSI itself does not need to grasp and manage the type of execution information. As a result, the transfer function of the audio system execution information can be easily realized without significantly complicating the configuration of the graphic LSI.

  According to the first or second invention, the storage location of the graphic system execution information and the audio system execution information is a storage unit separate from the display image storage location. Further, the bus for transferring the audio system execution information to the audio LSI is separated from the bus for outputting the display image to the output device. Furthermore, the transfer of the audio system execution information to the audio LSI is performed asynchronously with the display image output by the graphic processing unit. As a result, the transfer of the audio system execution information is eliminated from the time restriction associated with the scanning of the display image, so that it is possible to suppress a decrease in transfer efficiency and simplify the transfer control.

  According to the third or fourth invention, the register storage destinations are distinguished in advance by write transfer and read transfer, so that bidirectional data transfer (write transfer / read transfer) is performed between the CPU and the audio LSI. It can be executed efficiently and at high speed.

  According to the fifth or sixth invention, by controlling the transfer timing from the graphic LSI to the audio LSI by the CPU, it is not necessary to concentrate the issuance of audio reproduction parameters in a short time, and there is a time margin. Among them, it can be performed appropriately in view of the timing with a small comparison load. As a result, the load on the CPU can be distributed, so that it is possible to improve the controllability of the CPU with respect to synchronized reproduction of images and sounds.

  FIG. 1 is a block configuration diagram of an integrated system for synchronously reproducing images and sounds according to the present embodiment. This integrated system includes a CPU 1, a ROM 2 (ROM: Read Only Memory), a graphic LSI 3, an output device 4, a ROM 5, an audio LSI 6, and an output device 7. The CPU 1 and the graphic LSI 3 are connected via a certain bus, and the graphic LSI 3 and the audio LSI 6 are connected via another bus. In the present embodiment, the CPU 1 and the audio LSI 6 are not directly connected, and the graphic LSI is interposed. Therefore, data transfer between the CPU 1 and the audio LSI 6 is performed via the graphic LSI 3. .

  The graphic LSI 3 includes a CPU interface 31, a register 32, a graphic processing unit 33, a transfer circuit 34, and a command interface 35. The graphic processing unit 33 includes a RAM 33a (RAM: Random Access Memory), a transfer circuit 33b, a drawing circuit 33c, and a display circuit 33d. The CPU 1 positioned at the higher level issues graphic system execution information to the graphic LSI 3. The graphic system execution information includes an image reproduction command and an image reproduction parameter necessary for executing this command. The image reproduction parameter includes, for example, designation of an address (transfer source address) of the externally attached ROM 2 and designation of an address (transfer destination address) of the RAM 33a constituting a part of the graphic processing unit 33. The graphic system execution information issued by the CPU 1 is stored in a predetermined area of the register 32 via the CPU interface 31. When playback of an image (including both moving images and still images) is instructed by an image playback command, an image playback parameter is read from a predetermined storage location previously associated with the command, and the parameter is specified. The image reproduction process is executed. As a schematic flow of this processing, first, the transfer circuit 33b reads image data (for example, an object) from the ROM 2 that is a transfer source memory, and transfers it to the work area of the RAM 33a that is a transfer destination memory. Next, the drawing circuit 33c reads the image data stored in the work area, performs a drawing process using the image data, and writes the display image generated by this process in the frame memory area of the RAM 33a. Then, the display circuit 33d reads the display image for one frame stored in the frame memory area, and outputs / displays it on the output device 4 such as a display via the bus between the graphic LSI 3 and the output device 4.

  The graphic LSI 3 has a function of mediating data transfer between the CPU 1 and the audio LSI 6. The CPU 1 issues transfer system execution information to the graphic LSI 3 in order to control the transfer circuit 34 that executes this data transfer. The transfer system execution information includes a transfer command and transfer parameters necessary for executing this command. The transfer parameters include, for example, the size of data to be transferred (transfer size), transfer rate (transfer amount per unit time), transfer direction (write transfer / read transfer as viewed from the graphic LSI 3), and transfer target. Storage destination address and the like. The transfer system execution information issued by the CPU 1 is stored in a predetermined area of the register 32 via the CPU interface 31. Although details will be described later, when the start of data transfer is instructed by a transfer command, a transfer parameter is read from a predetermined storage location previously associated with this command, and data transfer according to the designation of this parameter is performed. Executed. The transfer instruction to the transfer circuit 34 may be performed in a command format using the register 32, but may be performed by directly outputting a control signal to the transfer circuit 34.

  Data transfer from the graphic LSI 3 to the audio LSI 6 is performed asynchronously with the output of the display image by the graphic processing unit 33. Here, “asynchronous” means horizontal scanning or vertical scanning for displaying a display image, or data transfer via the bus between the graphic LSI 3 and the output device 4 performed in synchronization with these scannings. It is done independently. As a premise for making this possible, it is necessary to separate the bus between the graphic LSI 3 and the output device 4 and the bus between the graphic LSI 3 and the audio LSI 6 (make them different). This is because if both are shared by a single bus, there is a time restriction that data cannot be transferred to the audio LSI 6 during display image transfer. At the same time, a storage unit (that is, register 32) that stores data (audio system execution information) to be transferred to the audio LSI 6, and a storage unit (that is, RAM 33a) that stores data (display image) to be transferred to the output device 4. There is also a need to separate (make different storage units). This is because if both are shared by a single memory, the audio system execution information cannot be read while the display image is being read, and the above-described asynchrony is impaired. By adopting such a configuration, it is freed from the time restrictions regarding data transfer, which is a problem in Patent Document 2 cited as the prior art. As a result, even when the data amount (transfer amount) of the audio system execution information to be transferred to the audio LSI 6 is large, it is possible to quickly transfer necessary data without performing complicated transfer control.

  The audio LSI 6 includes a command interface 61, a register 62, and an audio processing unit 63. The audio processing unit 63 includes a ROM interface 63a, a signal processing circuit 63b, and an audio interface 63c. The CPU 1 positioned at the higher level issues audio system execution information to the audio LSI 6 via the graphic LSI 3. The audio system execution information includes an audio playback command and an audio playback parameter necessary for executing this command. The audio reproduction parameter includes, for example, specification of a phrase number. The audio system execution information issued by the CPU 1 is temporarily buffered in the register 32 on the graphic LSI 3 side, and then transferred to the register 62 (storage destination) on the audio LSI 6 side via the transfer circuit 34 and the command interfaces 35 and 61. The When the start of audio reproduction is instructed by the audio reproduction command transferred from the graphic LSI 3, an audio reproduction parameter is read from a predetermined storage location previously associated with this command, and an audio corresponding to the designation of this parameter is read. Playback processing is executed. As a schematic flow of this process, first, audio data stored in the externally attached ROM 5 is transferred to the signal processing circuit 63b via the ROM interface 63a. Then, the output data signal-processed by the signal processing circuit 63b is output to the output device 7 such as a speaker via the audio interface 63c.

  FIG. 2 is a diagram showing a storage area of the register 32 provided in the graphic LSI 3. The register 32 is a set of unit areas to which a unique address is assigned. In the present embodiment, the address space of the register 32 is divided into five areas A to E (storage areas) based on the type of information to be stored.

  The area A is a graphic storage area to which an address range is assigned in advance as a storage destination of graphic execution information. The CPU 1 issues the graphic system execution information after designating the storage destination address within the address range assigned as the area A. The issued graphic system execution information is stored at a storage destination address designated by the CPU 1. Then, by reading the stored execution information, the graphic processing unit 33 performs an image reproduction process based on the read execution information.

  The area B is a storage destination of audio system execution information, and is an audio system storage area to which an address range different from the storage system of graphic system execution information is assigned in advance. The size of the area B is fixedly set. The CPU 1 issues the audio system execution information after designating the storage destination address within the address range assigned as the area B. The issued audio system execution information (which may include the storage destination address of the register 62 of the audio LSI 6) is stored at the storage destination address designated by the CPU 1. This area B is used for data transfer (write transfer) from the graphic LSI 3 to the audio LSI 6. The contents stored in the area B correspond to information to be transferred to the audio LSI 6 in order to perform the audio reproduction process. As described above, since the storage destination is distinguished between the audio system execution information and the graphic system execution information, the graphic LSI 3 itself does not need to grasp and manage the type of the execution information.

  The area C is an audio storage area in which an address range is assigned in advance as a storage destination of information read from the audio LSI 6 (hereinafter referred to as “read information”), and its size is fixedly set. . Unlike the previous area B, this area C is used for data transfer (read transfer) from the audio LSI 6 to the graphic LSI 3. Therefore, the stored contents of the area C correspond to read information (for example, information indicating the operating state of the audio LSI 6) acquired from the register 62 on the audio LSI 6 side for the CPU 1 to access. Thus, the reason for distinguishing the storage destination in advance between write transfer and read transfer is to efficiently perform bidirectional data transfer (write transfer / read transfer).

  The area D is a transfer system storage area to which an address range is assigned in advance as a storage destination of transfer system execution information (particularly transfer parameters), and its size is fixedly set. The CPU 1 issues a transfer parameter after designating the storage destination address assigned as the area D. The issued transfer parameter is stored in the storage destination address designated by the CPU 1 (that is, the area D). When an instruction to start data transfer is issued by the CPU 1, the transfer circuit 34 reads the transfer parameter stored in the area D and executes data transfer according to the instruction. That is, when write transfer is instructed, the stored contents of area B are read. The amount of information read out here is variable within the size range of the area B, and the information indicated by the transfer size included in the transfer parameter is sequentially read out. Then, the data is transferred to the audio LSI 6 at the data transfer amount per unit time specified by the transfer rate, and stored in the storage destination (part of the register 62) specified as the storage destination address. By setting such transfer parameters, the transfer circuit 34 can execute transfer of data (execution information) according to various types and sizes. On the other hand, when the read transfer is instructed, the data transferred from the register 62 is stored in the area C on the register 32 side. The other points are the same as the write transfer.

  The area E is a flag storage area for storing the transfer flag Ftr. The transfer flag Ftr indicates whether or not data transfer is being performed between the areas B and C of the register 32 and the register 62 on the audio LSI 6 side, and is appropriately changed by the transfer circuit 34. Specifically, when the transfer is completed, the transfer circuit 34 sets the status of the transfer flag Ftr to “0” to permit the CPU 1 to access the areas B and C, while the transfer is in progress. Sets the status to “1” and prohibits the CPU 1 from accessing the areas B and C. The CPU 1 that can access the area E monitors the status of the transfer flag Ftr at any time by a known method such as polling, and determines whether or not access to the areas B and C is permitted. Thereby, the CPU 1 can grasp the transfer state between the graphic LSI 3 and the audio LSI 6 by acquiring the transfer flag Ftr. In addition to storing the transfer flag Ftr in the register 32, the transfer flag Ftr may be stored in other storage means accessible by both the transfer circuit 34 and the CPU 1. Further, although details will be described later, when two types of modes of writing transfer and reading transfer are used as data transfer between the graphic LSI 3 and the audio LSI 6, it is preferable to prepare a transfer flag separately for each mode. . In the following description, the write transfer flag is Ftr1, and the read transfer flag is Ftr2.

  FIG. 3 is an explanatory diagram showing an example of the linking operation of the graphic LSI 3 and the audio LSI 6. The illustrated case shows a write transfer from the register 32 (area B) of the graphic LSI 3 to the register 62 on the audio LSI 6 side. The write transfer typically occurs in the case where the image reproduction by the graphic LSI 3 and the audio reproduction by the audio LSI 6 are synchronized. In order to simplify the explanation, it is assumed that no execution information is stored in the register 32 of the graphic LSI 3 and the register 62 of the audio LSI 6 in the initial state.

  4 shows the register 32 (areas B, D, E) of the graphic LSI 3 and the register 62 on the audio LSI 6 side in a series of steps from step 13 (step 17) to step 14 (step 18) of FIG. FIG.

  First, in step 11, the CPU 1 sets an image reproduction parameter for the register 32 of the graphic LSI 3. The image reproduction parameter issued by the CPU 1 is stored in the graphic system storage area A of the register 32 via the CPU interface 31. Prior to the instruction to execute image reproduction, the moving image reproduction parameter may be issued / stored a plurality of times.

  Next, in step 12, the CPU 1 sets an audio reproduction parameter for the register 32 of the graphic LSI 3. The audio reproduction parameter issued by the CPU 1 is stored in the audio system storage area B of the register 32 via the CPU interface 31. Prior to the instruction to execute audio reproduction, the audio reproduction parameter may be issued / stored a plurality of times.

  In step 13, after issuing the transfer parameter (timing T1 in FIG. 4), the CPU 1 instructs the graphic LSI 3 to start data transfer. Upon receiving this instruction, the transfer circuit 34 reads the transfer parameter from the transfer system storage area D, and starts writing and transferring the audio reproduction parameter (stored in the area B) according to the instruction. The transfer target is specified by the transfer size included in the transfer parameter, and information corresponding to the transfer size is read from the area B. The transfer rate is specified by a transfer rate included in the transfer parameter, and data transfer is executed at the transfer rate. This also applies to each data transfer described later. The transfer circuit 34 changes the status of the write transfer flag Ftr1 stored in the transfer flag storage area E from “0” (transfer end) to “1” (during transfer) with the start of the write transfer. Change (timing T2 in FIG. 4). While the status of the transfer flag Ftr1 is “1”, access (write) to the audio storage area B by the CPU 1 is prohibited (timing T3 in FIG. 4). As the write transfer ends, the transfer circuit 34 changes the status of the transfer flag Ftr1 from “1” (during transfer) to “0” (transfer end) (timing T4 in FIG. 4). As a result, access to the audio storage area B by the CPU 1 is permitted. The CPU 1 detects that the status of the transfer flag Ftr1 has returned to “0” by polling or the like, and confirms that the write transfer of the audio reproduction parameter has been completed (timing T5 in FIG. 4; step 14).

  In step 15, the CPU 1 sets an audio reproduction command to the register 32 of the graphic LSI 3 on the condition that the audio reproduction parameter writing / transfer has been completed. The audio playback command issued by the CPU 1 is stored in the audio storage area B of the register 32 via the CPU interface 31.

  In step 16, the CPU 1 sets an image reproduction command to the register 32 of the graphic LSI 3. The image playback command issued by the CPU 1 is stored in the graphic storage area A of the register 32 via the CPU interface 31. As a result, the image reproduction parameter corresponding to this command is read from the graphic storage area A, and image processing corresponding to this is started in the graphic processing unit 33.

  In step 17, the CPU 1 issues a data transfer start instruction to the graphic LSI 3. Upon receiving this instruction, the transfer circuit 34 reads the transfer parameter from the transfer system storage area D, and starts writing and transferring the audio reproduction command (stored in the area B) according to the instruction. Further, the transfer circuit 34 changes the status of the transfer flag Ftr1 stored in the transfer flag storage area E from “0” (transfer end) to “1” (during transfer) with the start of the write transfer. . The transferred voice reproduction command is stored in the register 62 on the audio LSI 6 side. As a result, the audio reproduction parameter corresponding to this command is read from the register 62, and the audio reproduction process corresponding to this is started in the audio processing unit 63. As the write transfer ends, the transfer circuit 34 changes the status of the transfer flag Ftr1 from “1” (transfer in progress) to “0” (transfer end). The CPU 1 detects that the status of the transfer flag Ftr1 has returned to “0”, and confirms that the write transfer of the audio reproduction command has been completed (step 18).

  The linked operation of the graphic LSI 3 and the audio LSI 6 as described above has the following characteristics.

(1) The CPU issues a voice playback command for instructing the start of voice playback after the transfer of voice playback parameters to the audio LSI 6 is completed . Not only a command corresponding to a “play” button (trigger), but also parameters such as “the song, etc., at which track, at what volume, and what kind of sound effect are applied” are required. At the time of audio reproduction, parameters and commands are handled as a set. Therefore, it is necessary to control the parameters one by one, for example, for each song or each phrase, rather than just decisive. Therefore, at the time of execution of the command, the transfer of parameters related to this (setting to the register 62) must be completed. On the contrary, if the command is executed before the parameter transfer is completed, it is not preferable because a voice reproduction in which the parameter is not reflected occurs at an initial stage.

(2) At least with respect to the audio reproduction parameter, the transfer from the graphic LSI 3 to the audio LSI 6 is started by the transfer start instruction from the CPU 1. In this regard, the CPU 1 does not control the transfer timing between the graphic LSI 3 and the audio LSI. The case will be described as a comparative example. FIG. 5 is a timing chart of parameter transfer in the comparative example. The song A is played before the timing t1, and the song B is played after the timing t3. In this case, it is necessary to set the parameters d1 to d4 of the music piece B to the audio LSI register during the period t1 to t3 when the music pieces A and B are not reproduced. This is because if the parameter of the song A in the register is changed to the parameter of the song B before the timing t1 when the song A is being reproduced, it is reflected in the song A being reproduced. Further, the inconvenience of setting the parameter of the music piece B after the timing t3 when the reproduction of the music piece B is started is as described above.

  The CPU monitors the end of the reproduction of the music piece A by an internal counter, the above-described write transfer, etc., and issues the audio reproduction parameters d1 to d4 immediately after the timing t1 when the reproduction of the music piece A is finished. The issued parameters d1 to d4 are transferred to and stored in the graphic LSI via a bus between the CPU and the graphic LSI (hereinafter referred to as “CG bus”), and then the bus between the graphic LSI and the audio LSI ( Hereinafter, the data is transferred to the audio LSI via the “GA bus”. The transfer into the audio LSI must be completed by the timing t3 when the reproduction execution of the music B is instructed. Therefore, the parameters d1 to d4 must be issued in a short period (that is, substantially within the period of t1 to t3), and the load on the CPU is concentrated.

  On the other hand, FIG. 6 is a timing chart of parameter transfer in the present embodiment. First, before the timing t1, the CPU 1 issues a plurality of audio reproduction parameters d1 to d4 necessary for audio reproduction of the music piece B in a time division manner. These parameters d1 to d4 are stored in the graphic LSI 3 as needed via the CG bus. Then, at the timing t2 when the transfer start is instructed by the CPU 1, the parameters d1 to d4 stored in the register 32 of the graphic LSI 3 are collectively transferred to the audio LSI 6 via the GA bus.

  As described above, when the CPU 1 controls the transfer timing from the graphic LSI 3 to the audio LSI 6, the parameters d1 to d4 are stocked in advance in the register 32 of the graphic LSI 3 (that is, before the timing t1). Therefore, it is not necessary to concentrate the issuance of the parameters d1 to d4 in a short period of time, and it can be performed in a time-sharing manner in view of a relatively light load with a time margin. This makes it possible to distribute the load on the CPU 1 as compared with the comparative example described above. As a result, the controllability of the CPU 1 can be improved with respect to the synchronized reproduction of images and sounds.

  In general, a command serving as a trigger for sound reproduction has a smaller data amount than a parameter. Therefore, for the command, the control of the transfer timing by the transfer start instruction may be omitted.

  FIG. 7 is an explanatory diagram showing another example of the linking operation of the graphic LSI 3 and the audio LSI 6. The illustrated case shows a read transfer from the register 62 on the audio LSI 6 side to the register 32 (area C) of the graphic LSI 3. The read transfer occurs, for example, in the case where the image reproduction by the graphic LSI 3 is started after the audio fade-out by the audio LSI 6 ends. In order to simplify the explanation, in the initial state, audio fade-out is executed in the audio LSI 6, and information indicating the audio fade-out state, that is, audio status is stored in the register 62. The audio status is 1-bit audio system execution information (corresponding to the read information described above), status “0” indicates the end of fade-out, and status “1” indicates that the fade-out is being executed.

  First, in step 21, as in step 11, the CPU 1 sets an image reproduction parameter for the register 32 of the graphic LSI 3.

  Next, in step 22, after issuing the transfer parameter, the CPU 1 instructs the graphic LSI 3 to start data transfer. Upon receiving this instruction, the transfer circuit 34 reads the transfer parameter from the transfer system storage area D and starts reading and transferring the voice status (stored in the register 62) in accordance with the instruction. Further, the transfer circuit 34 changes the status of the read transfer flag Ftr2 stored in the transfer flag storage area E from “0” (transfer end) to “1” (during transfer) with the start of this read transfer. . While the status of the transfer flag Ftr2 is “1”, access (write) to the audio storage area C by the CPU 1 is prohibited. The transfer circuit 34 periodically writes the audio status, and when the audio status of the area C is changed from “1” to “0”, that is, the audio that is being executed in the audio LSI 6 is faded out. When the audio status of the audio LSI 6 becomes “0” and this audio status is read into the area C, the writing is ended. Note that during the transfer of the audio status, the CPU 1 monitors the transfer state as needed, similarly to the timing T3. Then, along with the completion of the write transfer, the transfer circuit 34 changes the status of the transfer flag Ftr2 from “1” (transfer in progress) to “0” (transfer end). As a result, access to the audio storage area C by the CPU 1 is permitted. The CPU 1 detects that the status of the transfer flag Ftr2 has returned to “0” by polling or the like, and confirms that the writing and transferring of the audio reproduction parameter has been completed (step 23).

  In step 24, as in step 16, the CPU 1 sets an image reproduction command to the register 32 of the graphic LSI 3. As a result, the image reproduction parameter corresponding to this command is read from the graphic storage area A, and image processing corresponding to this is started in the graphic processing unit 33.

  Thus, according to the present embodiment, the audio system execution information (audio reproduction parameter / audio reproduction command) issued by the CPU 1 is transferred to the audio LSI 6 via the graphic LSI 3. Thereby, the audio system execution information can be transferred to the audio LSI 6 without connecting the audio LSI 6 directly to the CPU 1. Therefore, when the audio LSI 6 is not directly connected, it is possible to reduce the number of terminals (number of pins) of the CPU 1 by the number necessary for the connection. Since the present invention is characterized by the data transfer process itself to the audio LSI 6 via the graphic LSI, it does not prohibit the CPU 1 and the audio LSI 6 from being connected by bus (even if the bus is connected for some reason). Good).

  Further, according to this embodiment, information to be transferred to the audio LSI 6 or read information transferred from the audio LSI 6 is temporarily buffered in the areas B and C of the register 32 on the graphic LSI 3 side. In general, an audio LSI often has a low-throughput CPU interface compared to a graphic LSI. Therefore, the access efficiency is poor for the CPU (which is connected to the high-throughput CPU interface of the graphic LSI). On the other hand, in the present embodiment, by providing the graphic LSI 3 with the above buffering function, the efficiency of device control of the graphic LSI 3 and the audio LSI 6 can be improved, and the CPU occupation time required for device access can be increased. It becomes possible to shorten.

  Further, in the present embodiment, an address range different from the storage destination of audio system execution information (that is, graphic system storage area A) is assigned in advance as the storage destination of audio system execution information (that is, audio system storage areas B and C). ing. Information to be transferred to the audio LSI 6 is specified by address designation from the CPU 1. Therefore, it is not necessary for the graphic LSI 3 to individually grasp and manage information to be transferred to the audio LSI 6. Further, since the audio storage areas B and C are merely buffers for data transfer between the CPU 1 and the audio LSI 6, it is not necessary for the graphic LSI 3 to grasp and manage the contents (parameter / command type) to be transferred. Therefore, the data transfer function between the CPU 1 and the audio LSI 6 can be easily realized without significantly complicating the configuration of the graphic LSI 3.

  Further, according to the present embodiment, the storage location of the graphic system execution information and the audio system execution information is a storage unit (that is, the register 32 and the RAM 33a) that is separate from the display image storage location. As a result, the other storage unit (for example, register 32) can be accessed (access independence) regardless of the access status of one storage unit (for example, RAM 33a). Further, the bus for transferring the audio system execution information to the audio LSI 6 is separated from the bus for outputting the display image to the output device 7. This enables data transfer on the other bus regardless of whether data is being transferred on one bus. Furthermore, the transfer of the audio system execution information to the audio LSI 6 is performed asynchronously with the display image output by the graphic processing unit 33. As a result, the transfer of the audio system execution information is freed from the time restrictions associated with the scanning of the display image, so that a reduction in transfer efficiency can be suppressed and the transfer control can be simplified.

  Furthermore, according to the present embodiment, the storage destination of the register 32 is distinguished in advance by write transfer and read transfer, so that bidirectional data transfer (write transfer / read transfer) is efficiently performed between the CPU 1 and the audio LSI 6. Can be executed efficiently and quickly.

  In the above-described embodiment, the graphic LSI 3 and the audio LSI 6 are merely separate blocks from a functional viewpoint. In view of the essence of the present invention, are the actual hardware configurations separate chips? It doesn't matter. The present invention is naturally applicable to a configuration in which both are made into one chip. When both are made into one chip, that is, when the chip functioning as the graphic LSI 3 also functions as the audio LSI 6, the only difference is that the connection bus between the graphic LSI 3 and the audio LSI 6 is not an external bus but an internal bus. Other than that, it is almost the same.

Block diagram of the integrated system according to the present embodiment The figure which shows the storage area of the register | resistor with which graphic LSI is equipped Explanatory drawing which shows an example of cooperation operation | movement of a graphic LSI and an audio LSI The figure which shows the transfer procedure from graphic LSI Parameter transfer timing chart in the comparative example Parameter transfer timing chart in this embodiment Explanatory drawing which shows another example of cooperation operation | movement of a graphic LSI and an audio LSI

Explanation of symbols

1 CPU
2 ROM
3 Graphic LSI
4 Output device 5 ROM
6 Audio LSI
7 Output device 31 CPU interface 32 Register 33 Graphic processing unit 33a RAM
33b transfer circuit 33c drawing circuit 33d display circuit 34 transfer circuit 35 command interface 61 command interface 62 register 63 audio processing unit 63a ROM interface 63b signal processing circuit 63c audio interface

Claims (5)

In the graphic LSI connected to the CPU via the first bus,
An address range as a storage destination of graphic system execution information for causing the graphic LSI to perform image reproduction processing is allocated in advance, and is issued by the CPU to a storage destination address designated by the CPU within the allocated address range. Graphic system storage area for storing the executed graphic system execution information,
An address range different from the storage location of the graphic system execution information is allocated in advance as a storage location of the audio system execution information for causing the audio processing means to perform audio reproduction processing, and the CPU within the allocated address range is assigned by the CPU. A first audio system storage area for storing audio system execution information issued by the CPU at a specified storage destination address;
An address range is assigned in advance, and a second audio storage area for storing read information transferred from the audio processing means;
A graphic processing unit for performing image reproduction processing according to the graphic system execution information stored in the graphic system storage area;
In response to a transfer instruction from the CPU, the audio system execution information stored in the first audio system storage area is sent to the audio processing means via a second bus different from the first bus. A graphic LSI comprising: a transfer circuit that transfers or transfers the read information read from the audio processing means to the second audio system storage area via the second bus. A transfer system storage area in which transfer parameters issued by the CPU and instructing transfer contents of the audio system execution information are stored;
The transfer circuit includes:
When write transfer is instructed by the transfer parameter stored in the transfer system storage area, the audio system execution information stored in the first audio system storage area is transferred to the audio processing means,
When read transfer is instructed by a transfer parameter stored in the transfer system storage area, the read information read from the audio processing means is transferred to the second audio system storage area. The graphic LSI according to claim 1. A first transfer flag indicating whether or not the audio execution information is being transferred from the first audio system storage area to the audio processing means; and the audio processing means to the second audio system storage area. A flag storage area accessible by the CPU for storing a second transfer flag indicating whether the read information is being transferred;
The transfer circuit includes:
When transfer from the first audio system storage area to the audio processing means is being performed, the first transfer flag is set to a status indicating that the audio system execution information is being transferred. If the CPU prohibits the CPU from accessing the first audio system storage area and the transfer from the first audio system storage area to the audio processing means is not performed, the first transfer is performed. By setting a flag to a status indicating that the audio system execution information is not being transferred, allowing the CPU to access the first audio system storage area;
When transfer from the audio processing means to the second audio storage area is being performed, by setting the second transfer flag to a status indicating that the read information is being transferred, If the CPU prohibits access to the second audio system storage area and the transfer from the audio processing means to the second audio system storage area is not performed, the second transfer flag is set. 3. The graphic LSI according to claim 1, wherein access to the second audio storage area by the CPU is permitted by setting to a status indicating that the read information is not being transferred. . In a synchronous reproduction method for synchronously reproducing images and sounds in an integrated system having a CPU, a graphic LSI connected to the CPU via a first bus, and audio processing means,
A first step in which the CPU issues graphic execution information with designation of a storage destination address within a pre-assigned address range as a storage destination of graphic execution information for causing the graphic LSI to perform image reproduction processing;
A second step of storing the graphic system execution information issued by the CPU in a storage location designated by the CPU in a graphic system storage area of the graphic LSI;
A third step of performing image reproduction processing according to the graphic system execution information stored in the graphic system storage area;
As a storage location of audio system execution information that causes the audio processing means to perform sound reproduction processing, the CPU specifies a storage destination address within a pre-assigned address range different from the storage location of the graphic system execution information. A fourth step of issuing audio system execution information;
A fifth step of storing the audio system execution information issued by the CPU in a storage location designated by the CPU in a first audio system storage area of the graphic LSI;
The audio system execution stored in the first audio system storage area in order to cause the audio processing means to perform a sound reproduction process according to the audio system execution information when a write transfer is instructed by the CPU. A sixth step of transferring information to the audio processing means via a second bus different from the first bus;
When read transfer is instructed by the CPU, the read information read from the audio processing means is transferred to the second audio system storage area of the graphic LSI via the second bus, and And a seventh step in which the CPU designates an address and accesses the second audio system storage area. When transfer from the first audio system storage area to the audio processing means is being performed, access to the first audio system storage area by the CPU is prohibited and the first audio system is also prohibited. An eighth step of permitting access to the first audio system storage area by the CPU when transfer from the storage area to the audio processing means is not performed;
When transfer from the audio processing means to the second audio storage area is being performed, access to the second audio storage area by the CPU is prohibited, and the audio processing means And a ninth step of permitting access to the second audio system storage area by the CPU when transfer to the second audio system storage area is not performed. Item 5. A synchronous reproduction method according to item 4.

Images