JP3758753B2 - Data transfer apparatus and data transfer method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transfer device and a data transfer method, and in particular, displays on a display device such as a CRT (Cathode Ray Tube) in a graphic computer, a special effect device, a video game machine, etc., which are video equipment using a computer. The present invention relates to a data transfer apparatus and a data transfer method for controlling data transfer with a memory (frame memory) that stores image data to be stored.
[0002]
[Prior art]
In a conventional video game machine, for example, when a three-dimensional object (image) is displayed, the object is decomposed into a plurality of polygons (unit figures), and each of these polygons is drawn, whereby the whole object Has been made to draw. Therefore, it can be said that the image drawn in this way is defined by a combination of polygons.
[0003]
In such a video game machine, for example, image data is written in a frame memory (for example, a VRAM (Video RAM (Random Access Memory))), while the image data stored in the frame memory is transferred to an NTSC (National Television System). The image is displayed by reading out the signal according to a synchronization signal of the (Commitee) method and supplying it to a monitor such as a CRT.
[0004]
By the way, in a video game machine, modes for accessing the frame memory include a rendering processor (rendering engine) that performs rendering processing for writing (drawing) image data in the frame memory, coordinate conversion, light source calculation, matrix calculation, There are a standard access mode when a CPU (Central Processing Unit) that performs geometry processing such as vector operation accesses the frame memory, a display access mode for reading image data to be displayed on the monitor from the frame memory, and the like.
[0005]
Conventionally, image data is normally written to the frame memory in the standard access mode, and image data is read from the frame memory in the display access mode. In some cases, image data is written to the frame memory using a triple port VRAM as the frame memory and in an input mode in conjunction with a synchronous display access mode. In this case, the writing of the image data to the frame memory is performed in conjunction with the reading of the image data for display.
[0006]
[Problems to be solved by the invention]
By the way, with recent advancement and development of digital technology, data transfer in the standard access mode can be performed at a higher speed than data transfer in the display access mode. As a result, it became possible to set various access modes.
[0007]
That is, for example, the standard access mode can be shared when the CPU or rendering processor accesses the frame memory and when a relatively low-speed medium accesses the frame memory.
[0008]
However, recently, high-speed processing is required to increase the power and realism of the game, and it becomes necessary for the CPU and rendering processor to access the frame memory in a random and burst manner. Therefore, if the standard access mode is shared with a case where low-speed media accesses the frame memory in a distributed manner, or when writing at the video rate, etc., the CPU, the rendering processor, and the frame memory Data transfer is inadvertently divided, which may significantly degrade processing performance.
[0009]
Therefore, there is a method of causing the CPU or rendering processor to perform such low-speed data transfer or data transfer performed in a distributed manner. However, even if a small amount of image data is transferred by this method, processing (for example, filtering or the like) cannot be started for an image until a certain set of image data is received at the transfer destination. In many cases, it is difficult to enjoy the merits of data transfer by a CPU or a rendering processor, such that some processing can be performed on the data at the same time as the data transfer.
[0010]
The present invention has been made in view of such a situation, and is intended to improve the processing performance of an apparatus.
[0011]
[Means for Solving the Problems]
The data transfer device according to claim 1 is a high-speed transfer control unit that controls high-speed transfer of image data to be displayed on the display device to a memory, and a read control unit that controls reading of the image data stored in the memory. First storage means for storing image data read from the memory, first transfer control means for controlling low-speed transfer of the image data stored in the first storage means to the display device, and display A second storage unit that stores image data supplied from an external device other than the device; a second transfer control unit that controls low-speed transfer of image data from the external device to the second storage unit; And writing control means for controlling writing of the image data stored in the second storage means to the memory.
[0012]
According to a fifth aspect of the present invention, in the data transfer method, the data transfer device stores the first storage means for storing the image data read from the memory and the image data supplied from an external device other than the display device, and the memory A second storage means for supplying the image data to be displayed on the display device at a high speed, a low-speed transfer of the image data stored in the first storage means to the display device, and an external device. The image data from are controlled independently of the low-speed transfer of the image data to the second storage means.
[0013]
The data transfer apparatus according to claim 1, wherein the high-speed transfer control unit controls high-speed transfer of the image data to be displayed on the display device to the memory, and the read control unit reads out the image data stored in the memory. Has been made to control. The first storage means stores the image data read from the memory, and the first transfer control means controls the low-speed transfer of the image data stored in the first storage means to the display device. Has been made. The second storage means stores image data supplied from an external device other than the display device, and the second transfer control means controls low-speed transfer of image data from the external device to the second storage means. It is made to do. The writing control means controls writing of the image data stored in the second storage means to the memory.
[0014]
6. The data transfer method according to claim 5, wherein the data transfer device stores the first storage means for storing the image data read from the memory, the image data supplied from an external device other than the display device, and the memory Second storage means for supplying to the display device, and high-speed transfer of the image data to be displayed on the display device to the memory, low-speed transfer of the image data stored in the first storage means to the display device, The low-speed transfer of the image data from the external device to the second storage means is controlled independently.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a plan view showing the configuration of an embodiment of a video game machine to which the present invention is applied. 2 is a front view thereof (viewed from below in FIG. 1), and FIG. 3 is a side view of its right side surface (side view viewed from the right direction in FIG. 1). Each is shown.
[0016]
The video game machine includes a game machine main body 2, an operation device 17 including a connection terminal portion 26 having a substantially square shape connected to the game machine main body 2, and a recording device 38 that is also connected to the game machine main body 2. It is composed of
[0017]
The game machine main body 2 is formed in a substantially square shape, and a disc mounting portion 3 for mounting a game recording medium on which a program and data for playing a game are recorded is provided at the center. In this embodiment, for example, a CD (Compact Disc) -ROM 51 as shown in FIG. 4 is detachably attached to the disc mounting portion 3 as a game recording medium. However, the game recording medium is not limited to a disc.
[0018]
A reset switch 4 that is operated when resetting the game and a power switch 5 that is operated when turning on / off the power are provided on the left side of the disc mounting unit 3. A disk operation switch 6 is provided which is operated when the disk mounting portion 3 is opened and closed. Further, on the front surface of the game machine main body 2, there are provided connection portions 7A and 7B to which the operation device 17 and the recording device 38 can be connected as a set. In the present embodiment, the connecting portions 7A and 7B are provided so that two sets of the operating device 17 and the recording device 38 can be connected. However, the connecting portion has a number of operations other than two sets. It is possible to provide as many devices 17 and recording devices 38 as can be connected.
[0019]
As shown in FIGS. 2 and 3, the connecting portions 7 </ b> A and 7 </ b> B are formed in two stages, the recording insertion section 8 connected to the recording device 38 is provided in the upper stage, and the connection terminal section 26 of the operating device 17 is provided in the lower stage. The connection terminal insertion part 12 to be connected is provided.
[0020]
The insertion hole of the recording insertion portion 8 is formed in a rectangular shape that is long in the lateral direction, and has a structure in which the lower end corners are more rounded than the upper end corners so that the recording device 38 cannot be inserted in reverse. It has become. Further, the recording insertion portion 8 is provided with a shutter 9 for protecting a connection terminal (not shown) for obtaining an internal electrical connection.
[0021]
The shutter 9 is attached in a state in which it is always urged outward by an elastic body (not shown) such as a spring formed in the shape of a coil torsion spring. Therefore, when the recording device 38 is inserted, the shutter 9 is opened to the back side at the leading end side where the recording device 38 is inserted, and when the recording device 38 is removed, the shutter 9 is returned by the urging force of the elastic body and automatically closed. Thus, it serves to protect the internal connection terminals from dust and further protects it from external impacts.
[0022]
As shown in FIGS. 2 and 3, the connection terminal insertion portion 12 has a shape in which the corners at the lower end of the insertion hole having a rectangular shape that is long in the horizontal direction are more rounded than the corners at the upper end. The connection terminal portion 26 of the operating device 17 does not enter in the reverse direction, and the shape of the insertion hole is different so that the recording device 38 does not enter. In this way, the size and shape of the insertion holes of the recording device 38 and the operation device 17 are different so that they are not misplaced.
[0023]
As shown in FIG. 1, the operating device 17 has a structure in which five fingers are freely moved and operated by being held between the palms of both hands, and is formed in a round shape connected to left and right objects. First and second operation portions 18 and 19, first and second support portions 20 and 21 formed in a square shape projecting from the first and second operation portions 18 and 19, first and second operations A select switch 22 and a start switch 23 provided in a constricted portion at an intermediate position between the portions 18 and 19, and third and fourth operation portions 24 formed to project from the front side of the first and second operation portions 18 and 19. 25 and a connection terminal portion 26 that is electrically connected to the game machine main body 2 via a cable 27. It is also possible to adopt a configuration that does not require the cable 27.
[0024]
The connection terminal portion 26 is attached to the tip of a cable 27 for electrical connection with the game machine main body 2, and as shown in FIG. A gripping portion is provided which is provided with a so-called jagged pattern anti-slip process (for example, a knurling process). Note that the gripping portion provided in the connection terminal portion 26 forms a so-called insertion / extraction portion, and its size, that is, its width W and length L are, for example, the same as the gripping portion of the recording device 38 described later. ing.
[0025]
The recording device 38 incorporates a non-volatile memory such as a flash memory, for example. On both side surfaces thereof, for example, a gripping portion (FIG. 3) configured in the same manner as in the connection terminal portion 26 is provided. It can be easily attached to and detached from the machine body 2. For example, when the game is temporarily interrupted, the recording device 38 is configured to store the state at that time, and when the game is restarted, the data can be read therefrom. The game can be resumed from the state corresponding to the data, that is, the state at the time of interruption.
[0026]
In the case of playing a game with the video game machine configured as described above, for example, the user connects the operation device 17 to the game machine body 2 and, if necessary, the recording device 38 also includes a game machine. Connect to the main body 2. Further, the user operates the disk operation switch 6 to set a CD-ROM 51 as a game recording medium in the disk mounting portion 3 and operates the power switch 5 to turn on the power to the game machine body 2. turn on. Thereby, in the game machine main body 2, the image and sound for the game are reproduced, so that the user plays the game by operating the operation device 17.
[0027]
Next, FIG. 5 shows an example of the electrical configuration of the game machine body 2 of FIG.
[0028]
The game machine main body 2 has two types of buses, a main bus 101 and a sub bus 102, as buses for exchanging data in each block. The main bus 101 and the sub bus 102 have a bus controller 116. Connected through.
[0029]
In addition to the bus controller 116, the main bus 101 includes a main CPU (Central Processing Unit) 111 including a microprocessor, a main memory 112 including a RAM (Random Access Memory), and a main DMAC (Direct Memory Access Controller) 113. , MDEC (MPEG Decorder), and GPU 115 are connected.
[0030]
In addition to the bus controller 116, the sub-bus 102 stores a GPU 115, for example, a sub-CPU 121 configured similarly to the main CPU 111, for example, a sub-memory 122 configured similarly to the main memory 112, a sub-DMAC 123, and an operating system. (Read Only Memory) 124, SPU (Sound Processing Unit) 125, ATM (Asynchronous Transmission Mode) communication unit 126, auxiliary storage device 127, and input device I / F (Interface) 128 are connected.
[0031]
Here, the main bus 101 is designed to exchange data at high speed, and the sub-bus 102 is designed to exchange data at low speed. That is, for data that can be exchanged at a low speed, the high speed of the main bus 101 is ensured by using the sub bus 102.
[0032]
The bus controller 116 disconnects the main bus 101 and the sub bus 102 and connects the sub bus 102 to the main bus 101. When the main bus 101 and the sub bus 102 are disconnected, only the devices connected to the main bus 101 can be accessed from the main bus 101, and only the devices connected to the sub bus can be accessed from the sub bus 102. However, when the sub-bus 102 is connected to the main bus 101, any device can be accessed from either the main bus 101 or the sub-bus 102. For example, in an initial state such as immediately after the power of the apparatus is turned on, the bus controller 116 is in an open state (the main bus 101 and the sub bus 102 are connected).
[0033]
The main CPU 111 performs various processes according to programs stored in the main memory 112. That is, for example, when the apparatus is activated, the main CPU 111 reads and executes a boot program from the ROM 124 on the sub bus 102 (connected to the sub bus 102) via the bus controller 116. Thereby, the main CPU 111 loads an application program (here, a game program) and necessary data from the auxiliary storage device 127 into the main memory 112 and the sub memory 112. The main CPU 111 executes the program loaded in the main memory 112 in this way.
[0034]
The main CPU 111 has a built-in GTE (Geometry Transfer Engine) 117, and this GTE 117 includes a parallel operation mechanism that executes a plurality of operations in parallel, for example, coordinate conversion and light source according to a request from the main CPU 111. Geometry processing such as calculation, matrix operation, and vector operation is performed at high speed. As described above, the GTE 117 performs processing (geometry processing) according to a request from the main CPU 111 to generate polygon data (hereinafter, appropriately referred to as polygon data) that constitutes an image to be displayed. To supply. When the main CPU 111 receives polygon data from the GTE 117, each polygon data is packetized and transferred to the GPU 115 via the main bus 101.
[0035]
The main CPU 111 has a built-in cache memory (Cache) 119, and instead of accessing the main memory 112, the main CPU 111 accesses the cache memory 119 so as to increase the processing speed.
[0036]
As described above, the main memory 112 stores not only programs but also data necessary for the operation of the main CPU 111. The main DMAC 113 controls the DMA transfer for the devices on the main bus 101. However, when the bus controller 116 is in the open state, the main DMAC 113 controls the devices on the subbus 102 as well. The MDEC 114 is an I / O device operable in parallel with the main CPU 111 and functions as an image expansion engine. That is, the MDEC 114 decodes image data compressed by MPEG (Moving Picture Experts Group) encoding.
[0037]
A GPU (Graphic Processing Unit) 115 functions as a rendering processor and a CRTC (CRT Controller). That is, the GPU 115 receives a packet transmitted from the main CPU 111 or PPP 120, and is arranged as polygon data in the packet, for example, Z indicating the color data and depth (depth from the viewpoint) of the vertex of the polygon. Based on the value, rendering processing is performed to write (draw) image data corresponding to the polygon in the VRAM 118. Further, the GPU 115 reads out the image data written in the VRAM 118 and outputs it as a video signal compliant with, for example, the NTSC system. Note that the GPU 115 is also configured to receive a packet from the main DMAC 113 or a device on the sub-bus 102 and write image data arranged in the packet to the VRAM 118 as necessary. The GPU 115 is also configured to read out image data stored in the VRAM 118 and transfer it to devices on the subbus 102 as necessary.
[0038]
The VRAM 118 is configured to store image data supplied from the GPU 115. Note that the image data stored in the VRAM 118 is read by the GPU 115 as described above.
[0039]
As the VRAM 118, for example, a DRAM (Dynamic RAM) having a storage capacity for a plurality of frames can be used. In this case, when writing image data of a certain frame, an image of another frame is written. Data can be read out, whereby the processing speed can be increased.
[0040]
The sub CPU 121 reads out and executes a program stored in the sub memory 122 to perform various processes. Similar to the main memory 112, the sub memory 122 stores programs and necessary data. The sub DMAC 123 controls the DMA transfer for the devices on the sub bus 102. The sub DMAC 123 acquires the bus right only when the bus controller 116 is in the closed state (when the main bus 101 and the sub bus 102 are disconnected). As described above, the ROM 124 stores a boot program, an operating system, and the like. The ROM 124 stores programs for both the main CPU 111 and the sub CPU 121. In addition, the ROM 124 here has a low access speed, and is therefore provided on the sub-bus 102.
[0041]
The SPU 125 receives a packet transmitted from the sub CPU 121 or the sub DMAC 123, and reads out audio data from the sound memory 129 in accordance with a sound command arranged in the packet. The SPU 25 is configured to supply the read audio data to a speaker (not shown) for output. The ATM communication unit 126 performs control of communication (ATM communication control) performed via a public line (not shown), for example. Thereby, a user of the video game machine can play a battle with a user of another video game machine directly or by exchanging data via a predetermined center station.
[0042]
The auxiliary storage device 127 is configured to reproduce information (programs, data) recorded on the CD-ROM 51 (FIGS. 1 and 4) using, for example, a disk drive. The auxiliary storage device 127 is also configured to record and read information with respect to the recording device 38 (FIG. 1). The input device I / F 128 is an interface for receiving an external input such as a signal corresponding to an operation of the operation device 17 (FIG. 1) as a control pad or an image or a sound reproduced by another device. A signal corresponding to the input signal is output on the sub-bus 102. The sound memory 129 stores audio data.
[0043]
In the game machine main body 2 configured as described above, when the power of the apparatus is turned on, the main CPU 111 reads the boot program from the ROM 124 and executes it, thereby being set in the auxiliary storage device 127. The program and data are read from the CD-ROM 51 and developed in the main memory 112 and the sub memory 122. Then, in the main CPU 111 or the sub CPU 121, a program developed in the main memory 112 or the sub memory 122 is executed, so that the game image and sound are reproduced.
[0044]
That is, for example, in the main CPU 111, polygon data for drawing a polygon constituting a predetermined three-dimensional image is generated according to the data stored in the main memory 112. This polygon data is packetized and transferred to the GPU 115 via the main bus 101.
[0045]
When the GPU 115 receives a packet from the main CPU 111, the GPU 115 draws a polygon to the VRAM 118 according to the polygon data arranged in the packet. The drawing result for the VRAM 118 is appropriately read out by the GPU 115 and output as a video signal. Thereby, the game screen (image) is displayed.
[0046]
On the other hand, in the sub CPU 121, a sound command for instructing sound generation is generated according to the data stored in the sub memory 122. This sound command is packetized and supplied to the SPU 125 via the sub-bus 102. The SPU 125 reads and outputs audio data from the sound memory 129 in accordance with the sound command from the sub CPU 121. Thereby, BGM (Background Music) and other sounds of the game are output.
[0047]
Next, FIG. 6 shows a configuration example of the GPU 115 of FIG.
[0048]
The control unit 202 controls the low-speed synchronous access control circuit 204, the high-speed synchronous access control circuit 205, and the low-speed random access control circuit 208. The control register 203 stores data necessary for the operation of the control unit 202.
[0049]
The low-speed synchronous access control circuit 204 (first transfer control means) is for transferring the image data stored in the line buffer 206 to the CRT 215 serving as a display device via the D / A converter 214 at a low speed. Control (control of low-speed synchronous access) is performed.
[0050]
A high-speed synchronous access control circuit 205 (reading control unit) (writing control unit) controls high-speed reading of image data stored in the VRAM 118. The high-speed synchronous access control circuit 205 also controls to write the image data written to the line buffer 207 via the sub-bus 102 to the VRAM 118.
[0051]
Line buffers 206 (first storage means) and 207 (second storage means) store image data read from the VRAM 118 by the high-speed synchronous access control circuit 205. Note that the line buffer 207 has bidirectionality, and as described above, stores the image data supplied via the subbus 102. This image data is stored in the high-speed synchronous access mode. The data is written into the VRAM 118 by the control circuit 205.
[0052]
The low-speed random access control circuit 208 (second transfer control means) includes a line buffer 207 Is transferred via the sub-bus 102, and the image data output on the sub-bus 102 is transferred to the line buffer 207 for storage. That is, as a result, data transfer by low-speed random access can be performed between the device on the sub-bus 102 and the VRAM 118 via the line buffer 207.
[0053]
Here, the above blocks constitute a quasi-synchronous control system, and the control unit 202, the control register 203, the low-speed synchronous access control circuit 204, the high-speed synchronous access control circuit 205, and the line buffer 206 are displayed on the CRT 215. A PCRTC (Programmable CRT Controller) 201 that performs control is configured.
[0054]
The rendering engine 209 receives a packet transferred via the main bus 101 and performs rendering processing, that is, writing image data into the VRAM 118. A high-speed random access control circuit 210 (high-speed transfer control means) controls high-speed transfer of image data from the rendering engine 209 to the VRAM 118. In other words, this enables data transfer by high-speed random access between the rendering engine and the VRAM 118.
[0055]
For example, the synchronization signal generation circuit 211 generates a horizontal synchronization signal and a vertical synchronization signal in an NTSC television signal, and supplies the horizontal synchronization signal to the H counter 212 and the vertical synchronization signal to the V counter 213, respectively. Has been made. The H counter 212 counts the horizontal synchronization signal from the synchronization signal generation circuit 211. The V counter 213 operates in synchronization with the counting operation of the H counter 212 and counts the vertical synchronization signal from the synchronization signal generation circuit 211. The count values in the H counter 212 and the V counter 213 are supplied to the PCRTC 201. Note that the control unit 202 of the PCRTC 201 recognizes image data to be read from the VRAM 118 based on these count values, and transfers the image data to the CRT 215 via the D / A converter 214. Access control circuit 204 and high-speed synchronous access control circuit 205 are controlled.
[0056]
The D / A converter 214 converts the image data transferred from the line buffer 206 into an analog signal by D / A conversion, and supplies the analog signal to the CRT 215. The CRT 215 displays an image (screen) corresponding to the output of the D / A converter 214.
[0057]
In FIG. 5 described above, the synchronization signal generation circuit 211, the H counter 212, the V counter 213, the D / A converter 214, and the CRT 215 are not shown.
[0058]
In the GPU 115 configured as described above, the rendering engine 209 receives a packet supplied from the main CPU 111 or the main DMAC 113 via the main bus 101, and image data is written to the VRAM 118 based on the packet. At this time, image data is transferred by performing high-speed random access from the rendering engine 209 to the VRAM 118, and the high-speed random access control circuit 210 controls the high-speed random access.
[0059]
On the other hand, the H counter 212 or the V counter 213 counts the horizontal synchronization signal or the vertical synchronization signal generated by the synchronization signal generation circuit 211, and supplies the count value to the control unit 202. The control unit 202 determines image data to be read from the VRAM 118 based on the count values from the H counter 212 and the V counter 213, and controls the low-speed synchronous access control circuit 204 and the high-speed synchronous access control circuit 205.
[0060]
As a result, the high-speed synchronous access control circuit 205 accesses the VRAM 118 at high-speed synchronous under the control of the control unit 202 and reads image data therefrom. Further, the high-speed synchronous access control circuit 205 converts the read image data into a line buffer. 206 To be stored. The low-speed synchronous access control circuit 204 includes a line buffer 206 Is read out and supplied to the CRT 215 via the D / A converter 214. As a result, the CRT 215 performs screen display corresponding to the image data read from the VRAM 118.
[0061]
By the way, in the GPU 115 of FIG. 6, independent of the high-speed random access to the VRAM 118 by the rendering engine, the low-speed random access to the VRAM 118 is controlled by the same control as the low-speed synchronous access (display access) to the VRAM 118 performed for screen display. Thus, an external medium 221 (an external device other than a display device) as a device on the subbus 102 is accessed (in this embodiment, the ATM communication unit 126, the auxiliary storage device 127, the input device I / F 128, etc.) Image data (eg, texture data, moving image data, image data compliant with the MPEG system, image data taken by a video camera, image data reproduced by a video tape recorder, etc.) is written in the VRAM 118. It is possible It has been made so. Similarly, the image data stored in the VRAM 118 can be read and supplied to the external medium 221.
[0062]
The low-speed synchronous access (display access) is performed using the synchronization signals (horizontal synchronization signal and vertical synchronization signal) output from the synchronization signal generation circuit 211 as a trigger, whereas the low-speed random access is performed on the sub-bus 102. For example, an interrupt to the bus master 222 (in this embodiment, for example, the sub CPU 121 or the sub DMAC 123) is triggered.
[0063]
That is, the low-speed random access control circuit 208 is configured to output an interrupt signal to the bus master 222. When the bus master 222 receives the interrupt signal, the bus master 222 controls the external medium 221 to transfer the image data on the sub-bus 102. To output. Further, the bus master 222 controls the low-speed random access control circuit 208, and the image data output from the external medium 221 is stored in the line buffer. 207 To transfer at low speed. Line buffer 207 The image data stored in is transferred to the VRAM 118 and stored under the control of the high-speed synchronous access control circuit 205.
[0064]
As described above, the image data output from the external medium 221 stored in the VRAM 118 is read out in the same manner as the image data written in the VRAM 118 by the rendering engine 209, and the line buffer 206 and the D / A converter 214 are read out. To be supplied to the CRT 215 and displayed.
[0065]
In addition to the interrupt, the low-speed random access may be performed by checking a flag (for example, a flag indicating a buffer full) by a polling process and using the result of the check as a trigger.
[0066]
In the above-described case, the image data output from the external medium 221 is transferred to the VRAM 118. Conversely, the image data stored in the VRAM 118 is transferred to the external medium 221. Is also possible. That is, in this case, the high-speed synchronous access control circuit 205 reads the image data from the VRAM 118 and supplies it to the line buffer 207 for storage. The image data stored in the line buffer 207 is transferred to the external medium 221 at a low speed via the sub-bus 102 under the control of the low-speed random access control circuit 208.
[0067]
Next, FIG. 7 shows a high-speed random access performed by the high-speed random access control circuit 210 (FIG. 7A), a high-speed synchronous access performed by the high-speed synchronous access control circuit 205 (FIG. 7B), and a low-speed synchronous access control circuit. The timing of the low-speed synchronous access (display access) performed by 204 (FIG. 7C) and the low-speed random access performed by the low-speed random access control circuit 208 (FIG. 7D) are shown.
[0068]
In the high-speed random access control circuit 210, when the rendering engine 209 writes image data in the VRAM 118, high-speed random access control as standard access is performed (FIG. 7A). However, the high-speed random access is performed at a timing other than the period in which the high-speed synchronous access control circuit 205 performs the high-speed synchronous access control (FIG. 7B).
[0069]
On the other hand, the low-speed synchronous access is performed periodically in synchronization with the timing at which the synchronization signal generation circuit 211 outputs the synchronization signal, independently of the high-speed random access (FIG. 7C). This is performed independently of the high-speed random access (FIG. 7D). Furthermore, low-speed synchronous access and low-speed random access are also performed independently.
[0070]
As described above, since the low-speed random access similar to the low-speed synchronous access (display access) can be performed independently of the high-speed random access, this low-speed random access is distributed to, for example, the VRAM 118. To prevent the high-speed random access from being hindered in order to perform such processing, for example, when accessing the VRAM 118 or when writing to the VRAM 118 at a low rate such as the video rate. As a result, the processing performance of the apparatus can be improved.
[0071]
Furthermore, when performing low-speed random access, image data is written to and read from the VRAM 118 via the line buffer 207 as in the case of low-speed synchronous access (display access performed using the line buffer 206). Therefore, it becomes easy to handle a rectangular image composed of a collection of lines.
[0072]
The present invention has been described with respect to the case where the present invention is applied to a video game machine. However, the present invention can be applied to an effector that gives a special effect to an image, an apparatus that performs computer graphics processing such as CAD, and the like.
[0073]
In this embodiment, only one line buffer 206 is provided as a line buffer for display access (low-speed synchronous access). However, a plurality of line buffers for display access are provided. It is possible. Similarly, a plurality of line buffers 207 can be provided.
[0074]
Further, in the present embodiment, the line buffer 206 or 207 is provided as the storage means for the low-speed synchronous access or the low-speed random access, but this storage means is not limited to the line buffer.
[0075]
【The invention's effect】
According to the data transfer device of the first aspect, the high-speed transfer control unit controls the high-speed transfer of the image data to be displayed on the display device to the memory, and the first transfer control unit performs the first transfer. The low-speed transfer of the image data stored in the storage means to the display device is controlled. Further, the second transfer control means controls the low-speed transfer of the image data from the external device to the second storage means. Therefore, the processing performance of the apparatus can be improved by independently performing the high-speed transfer control by the high-speed transfer control means, the low-speed transfer control by the first transfer control means, and the low-speed transfer control by the second transfer control means. It becomes.
[0076]
According to the data transfer method of claim 5, high-speed transfer of image data to be displayed on the display device to the memory, low-speed transfer of image data stored in the first storage means to the display device, The low-speed transfer of the image data from the external device to the second storage means is controlled independently. Therefore, it is possible to improve the processing performance of the apparatus.
[Brief description of the drawings]
FIG. 1 is a plan view showing a configuration of an embodiment of a video game machine to which the present invention is applied.
FIG. 2 is a front view of the video game machine of FIG. 1;
FIG. 3 is a side view of the video game machine of FIG. 1;
4 is a plan view showing a CD-ROM 51. FIG.
5 is a block diagram showing an example of the electrical configuration of the game machine body 2 of FIG.
6 is a block diagram illustrating a configuration example of a GPU 115 in FIG.
FIG. 7 is a timing chart showing timings of high-speed random access, high-speed synchronous access, low-speed synchronous access (display access), and low-speed random access.
[Explanation of symbols]
101 main bus, 102 sub bus, 111 main CPU, 112 main memory, 113 main DMAC, 114 MDEC, 115 GPU, 116 bus controller, 117 GTE, 118 VRAM, 121 sub CPU, 122 sub memory, 123 sub DMAC, 124 ROM, 125 SPU, 126 sound memory, 127 auxiliary storage device, 128 input device I / F, 201 PCRTC, 202 control unit, 203 control register, 204 low-speed synchronous access control circuit (first transfer control means), 205 high-speed synchronous access control Circuit (read control means) (write control means), 206, 207 line buffer (first storage means) (second storage means), 208 low speed random access control circuit (second transfer control means) 209 rendering engine 210 high-speed random access control circuit (high-speed transfer control means), 211 synchronizing signal generating circuit, 212H counter, 213 V counter, 214 D / A converter, 215 CRT, 221 external medium, 222 master

Claims (6)

A data transfer device that controls data transfer with a memory that stores image data to be displayed on a display device,
High-speed transfer control means for controlling high-speed transfer of the image data from the rendering engine to the memory;
Reading control means for controlling reading of image data stored in the memory;
First storage means for storing image data read from the memory;
First transfer control means for controlling low-speed transfer of the image data stored in the first storage means to the display device;
Second storage means for storing image data supplied from an external device other than the display device;
Second transfer control means for controlling low-speed transfer of image data supplied from the external apparatus from the external apparatus to the second storage means,
The read control means further controls writing of the image data stored in the second storage means to the memory;
The second storage means has bidirectionality, stores image data read from the memory,
The second transfer control means also controls low-speed transfer of image data read from the memory and stored in the second storage means to the external device. The data transfer apparatus according to claim 1, wherein the first and second storage units are configured by line buffers. The data transfer apparatus according to claim 1 or 2 , wherein the first and second transfer control means perform quasi-synchronous access control. The read control means and the first transfer control means are controlled according to a synchronization signal,
The high-speed transfer control means is controlled for high-speed transfer to the memory at a timing excluding a period during which the image is read by the read control means,
The data transfer apparatus according to claim 1, 2, or 3, wherein the second transfer control means is controlled independently of each of the first transfer control means and the high-speed transfer control means. The data transfer apparatus according to claim 1, 2, 3, or 4, wherein the second transfer control means performs control by using an interrupt as a trigger. A data transfer method in a data transfer device for controlling data transfer with a memory for storing image data to be displayed on a display device,
The data transfer device
First storage means for storing image data read from the memory;
A bi-directional, with supplied stores image data supplied from an external device other than the display device to the memory, a second memory means for image data is also stored which is read out from said memory,
High-speed transfer of image data to be displayed on the display device from a rendering engine to the memory, low-speed transfer of image data stored in the first storage unit to the display device, and an image from the external device The low-speed transfer of data to the second storage means is independently controlled, and the low-speed transfer of image data read from the memory and stored in the second storage means to the external device Is controlled independently of high-speed transfer of image data to be displayed on the display device to the memory .

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