JP3198022B2 - Video game equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video game device such as a home TV game machine, and more particularly to a video game device having a function of secondary storing game data and the like.

[0002]

2. Description of the Related Art Conventionally, in a video game machine such as a home TV game machine, a random access memory (RAM) for data backup built in the main body of the game machine.
emory), static random access memory (SRAM:
The game data and the like are secondarily stored by a static random access memory (RAM), a RAM cartridge inserted into a slot also used as a game cartridge, or a combination thereof.

[0003]

In a conventional video game device having a function of secondary storing game data and the like as described above, a plurality of external secondary storage devices cannot be simultaneously connected to the device main body. Data cannot be directly copied between a plurality of external secondary storage devices. Also,
2. Description of the Related Art In a battle game or the like in which a plurality of players simultaneously participate, it is not possible to directly capture the data of each player directly into the apparatus main body. Therefore, in the case of using a plurality of external secondary storage devices, there is a problem that the replacement work is always required, and it takes time and effort to transfer data.

In an external secondary storage device using a RAM cartridge which is inserted into a slot also used as a game cartridge, the external storage device is directly connected to a bus of the device main body. It cannot be inserted or removed, which is inconvenient when handling game software having a large data amount over a plurality of external secondary storage devices. Further, for example, when the storage capacity of the external secondary storage device becomes insufficient during the backup, the power of the device main body must be turned off once, and the game data that needs to be backed up is lost. There was a problem that it would.

Further, in a conventional external secondary storage device which can be randomly accessed, it is backed up by a battery. Therefore, if the capacity of the battery is exhausted and the backup is stopped, data is lost.
There is a problem that data cannot be stored semi-permanently. In view of the above-described problems in the conventional video game device, an object of the present invention is to use a plurality of small-capacity external secondary storage devices as a large-capacity external secondary storage device, and a plurality of external storage devices. An object of the present invention is to provide a video game device, a data management method, and an external secondary storage device that can back up game software having a large amount of data over a secondary storage device.

Another object of the present invention is to provide a video game apparatus capable of directly copying data between a plurality of external secondary storage devices. It is still another object of the present invention to provide a video game device capable of simultaneously taking data from a plurality of external secondary storage devices directly into the device main body. It is an object of the present invention to provide a video game device and an external secondary storage device in which the external secondary storage device can be replaced while the power of the device main body is turned on.

It is still another object of the present invention to provide an external secondary storage device for a video game device capable of semi-permanently storing data relating to a game.

[0008]

According to the present invention, there is provided a video game apparatus having a function of secondary storing game data and the like in an external secondary storage device, comprising: a main bus; A slot for detachably connecting an external secondary storage device, a communication controller for connecting the main bus to the slot, and a central processing unit connected to the main bus; The device writes data to and / or writes data to an external secondary storage device connected to the slot via the communication controller.
Alternatively, data reading from the external secondary storage device is controlled. The communication controller may be configured to electrically separate the main bus from the slot. The slot may have a serial I / O interface. The communication controller can control communication between the main bus and the serial I / O interface. The communication controller may include a protection circuit for preventing electrical destruction. The slot can be configured to be able to supply power to a microcomputer built in the external secondary storage device. The central processing unit has a connection determining function of determining whether or not an external secondary storage device is connected to the slot, and only when it is determined that the external secondary storage device is connected, the connection with the external secondary storage device is determined. It can be configured to control data write and / or data read during. The video game device may be configured to include a plurality of the above slots.

An external secondary storage device for a video game machine according to the present invention, which corresponds to the above problem, is detachably connected to a slot of the video game device, and writes and / or writes data through the slot by the video game device. An apparatus which permits reading, comprising a memory for writing data in a readable manner, and a microcomputer for controlling data communication between the video game machine and the memory, the microcomputer being connected to a slot. Is supplied from a video game machine. Here, it is also possible to configure the memory of the external secondary storage device as a random access flash memory that does not require a backup power supply. The microcomputer of the external secondary storage device may set the internal state to a non-communication state upon power supply, and then allow communication with the video game device. A serial interface may be interposed between the microcomputer of the external secondary storage device and the video game machine, while a parallel interface may be interposed between the microcomputer and the memory.

Further, the data management method of the present invention corresponding to the above-mentioned problem is a data management method by a video game device having a plurality of slots which can be managed independently and to which an external secondary storage device can be detachably connected. And assigning an order to each of the plurality of slots, connecting an unused external secondary storage device to each slot, and indicating the order in order from the external secondary storage device connected to the first slot in order. When the free space is exhausted, the control of writing the remaining portion of the data to the external secondary storage device connected to the slot of the next order together with the information indicating the order is performed on the total amount of data to be written. It is characterized in that the writing of data over a plurality of external secondary storage devices is controlled by repeating until reaching.

Still another data management method according to the present invention, which addresses the problem, is a data management method using a video game apparatus having a plurality of slots which can be managed independently and to which an external secondary storage device can be detachably connected. A method for assigning an order to a plurality of slots, connecting an external secondary storage device in which data is written to each slot to each slot, and an external secondary storage device connected to a slot in the first order. It is determined whether or not the data to be written has been written, and in the case of an external secondary storage device in which the target data has been written, the data is read from the external secondary storage device, and the amount of read data is If the total amount of data is not reached, the control of reading the remaining data from the external secondary storage device connected to the next slot in the order is controlled by the data. By repeating until reaching the amount, and controls the reading of data over a plurality of external secondary memory.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a video game apparatus according to the present invention will be described below in detail with reference to the drawings. A video game apparatus according to the present invention, for example, is configured as shown in FIG. This video game apparatus reads out and executes a game program stored in an auxiliary storage device such as an optical disk to play a game in response to an instruction from a user, as shown in FIG. In addition, a control system 50 including a central processing unit (CPU) 51 and its peripheral devices, and an image processing device (GPU: Graphic Process
ing Unit) Graphic system 60 composed of 62, etc.
And a sound processing device (SPU: Sound:
Processing system)
And an optical disk controller 80 for controlling an optical disk as an auxiliary storage device, and an input / output from an auxiliary memory for storing an instruction input from a controller for inputting an instruction from a user, a game setting, and the like. Communication control unit 90
And a bus 100 to which the control system 50 to the communication control unit 90 are connected.

The control system 50 includes a CPU 51 and interrupt control and direct memory access (DMA).
y Access) A peripheral device controller 52 for controlling transfer and the like, and a random access memory (RAM: Random Acce
ss Memory) (main memory) 53
And a read only memory (ROM) 54 storing a program such as a so-called operating system for managing the main memory 53, the graphic system 60, the sound system 70, and the like. The CPU 51 controls the entire apparatus by executing an operating system stored in a ROM 54, and is a 32-bit RISC CPU.
Consists of

In the video game apparatus, when the power is turned on, the CPU 51 of the control system 50 reads the ROM
By executing the operating system stored in the CPU 54, the CPU 51 controls the graphic system 60, the sound system 70, and the like. When the operating system is executed, the CPU 51 initializes the entire apparatus such as operation check, and then controls the optical disk control unit 80 to execute a program such as a game recorded on the optical disk. Execute. By executing a program such as a game, the CPU 51 controls the graphic system 60, the sound system 70, and the like in accordance with an input from a user to control image display, sound effects, and generation of musical sounds.

The graphic system 60 includes:
A geometry transfer engine (GTE) 61 for performing processing such as coordinate conversion;
A GPU 62 for performing drawing in accordance with a drawing instruction from No. 1;
The image processing apparatus includes a frame buffer 63 for storing an image drawn by the GPU 62 and an image decoder 64 for decoding image data compressed and encoded by orthogonal transformation such as discrete cosine transformation.

The GTE 61 has, for example, a parallel operation mechanism for executing a plurality of operations in parallel, and can perform operations such as coordinate conversion, light source calculation, matrix or vector operation at high speed in response to an operation request from the CPU 51. It has become. Specifically, this GTE 61 is, for example, 1
In the case of flat shading that draws the same color on two triangular polygons, a maximum of 1 per second
Coordinate calculations of about 500,000 polygons can be performed, so that in this video game device, the load on the CPU 51 can be reduced and high-speed coordinate calculations can be performed. .

The GPU 62 draws a polygon or the like on the frame memory 62 in accordance with a drawing command from the CPU 51. This GPU 62,
A maximum of about 360,000 polygons can be drawn per second. Further, the frame buffer 63 is formed of a so-called dual port RAM,
The drawing from the GPU 62 or the transfer from the main memory and the reading for display can be performed simultaneously. This frame buffer 63 has 1
It has a capacity of M bytes, each having 16 bits
4 is treated as a matrix of 512 pixels vertically. The frame buffer 63 has a color lookup table referred to when the GPU 62 draws a polygon or the like, in addition to a display area output as a video output.
A CLUT area in which (CLUT: Cclor Lock Up Table) is stored and a texture area in which a material (texture) to be inserted (mapped) into a polygon or the like which is subjected to coordinate conversion at the time of drawing and drawn by the GPU 62 is stored. Have been. The CLUT area and the texture area are dynamically changed according to a change in the display area.

In addition to the flat shading described above, the GPU 62 complements the colors of the vertices of the polygon to determine the color in the polygon, and pastes the texture stored in the texture area onto the polygon. Texture mapping can be performed. When performing Gouraud shading or texture mapping, the above G
The TE 61 can perform a coordinate calculation of about 500,000 polygons at maximum per second.

Further, the image decoder 64 includes the CPU
Under the control of 51, the image data of a still image or a moving image stored in the main memory 53 is decoded and stored in the main memory 53. The reproduced image data is stored in the frame buffer 63 via the GPU 62 so that it can be used as a background of the image drawn by the GPU 62 described above.

The sound system 70 includes a CPU 51
SP that generates musical sounds, sound effects, etc. based on instructions from
A U71, a sound buffer 72 for recording waveform data and the like by the SPU 71, and a speaker 73 for outputting musical sounds, sound effects and the like generated by the SPU 71 are provided. The SPU 71 converts the 16-bit audio data into a 4-bit differential signal using adaptive prediction coding (ADPCM: Adapt
ive Diffrential PCM)
A PCM decoding function, a reproduction function for generating a sound effect by reproducing waveform data stored in the sound buffer 72, a modulation function for modulating and reproducing waveform data stored in the sound buffer 72, and the like. It has.

By providing such a function, the sound system 70 can be used as a so-called sampling sound source that generates musical tones, sound effects, and the like based on waveform data recorded in the sound buffer 72 in accordance with an instruction from the CPU 51. I can do it. The optical disk control unit 80 includes an optical disk device 81 that reproduces programs, data, and the like recorded on the optical disk.
And an error correction code (ECC: Error Correction Cod
e) a decoder 82 for decoding programs, data, etc. recorded with the addition of, and a buffer 83 for temporarily storing reproduction data from the optical disk device 81 to speed up reading from the optical disk. It has.

The audio data recorded on the optical disk reproduced by the optical disk device 81 includes so-called PCM data obtained by converting an audio signal from analog to digital in addition to the above-described ADPCM data. ADPCM
As data, for example, audio data recorded by expressing the difference of 16-bit digital data by 4 bits,
After being decoded by the decoder 82, it is supplied to the above-described SPU 71, subjected to digital / analog conversion and the like by the SPU 71, and then used to drive the speaker 73.

Also, audio data recorded as PCM data, for example, as 16-bit digital data, is decoded by a decoder 82 and then used to drive a speaker 73. Further, the communication control unit 90
It has a communication controller 91 for controlling communication with the CPU 51 via the bus 100, a slot 93 to which a controller 92 for inputting an instruction from a user is connected, and an external device 2 for temporarily storing game setting data and the like. 2 as secondary storage
The communication controller 91 is provided with two card connectors 95A and 95B to which the memory cards 94A and 94B are connected.

The controller 92 connected to the slot 93 has, for example, 16 instruction keys for inputting an instruction from a user, and changes the state of the instruction key according to an instruction from the communication controller 91. Is transmitted to the communication controller 91 about 60 times per second by synchronous communication. Then, the communication controller 91 changes the state of the instruction key of the controller 92 to C
Transmit to PU51.

Thus, the instruction from the user is transmitted to the CPU 5.
1 and the CPU 51 performs a process according to an instruction from the user based on a game program or the like that is being executed. Here, between the main memory 53, the GPU 62, the image decoder 64, the decoder 82, and the like, it is necessary to transfer a large amount of image data at a high speed when reading a program, displaying or drawing an image, and the like. Therefore, in this video game device, as described above, the CPU
A so-called DMA transfer for directly transferring data between the main memory 53, the GPU 62, the image decoder 64, the decoder 82, and the like can be performed under the control of the peripheral device controller 52 without passing through the controller 51. . Thus, the load on the CPU 51 due to data transfer can be reduced, and high-speed data transfer can be performed.

The CPU 51 transmits the stored data to the communication controller 91 when it is necessary to store the setting data and the like of the game being executed.
Reference numeral 1 denotes data from the CPU 51 to the card connector 95.
A or the memory card 94A or the memory card 94B connected to the card connector slot. Here, the communication controller 91 includes a protection circuit for preventing electrical destruction. The above memory card 9
4A and 94B are separated from the bus 100, and can be detached while the power of the apparatus main body is turned on. Therefore, when the storage capacity becomes insufficient, a new memory card can be inserted without turning off the power of the apparatus main body, and the game data that needs to be backed up is not lost, and a new memory card can be inserted. By inserting a memory card, necessary data can be written to a new memory card.

The memory cards 94A, 94B
Is a flash memory MEM that is randomly accessible and does not require a backup power supply, as shown in FIG.
And control lines DTX, DT via a card connector.
R, serial I connected to signal lines RXD, TXD for data transmission and signal line SCK for serial synchronous clock.
Built-in microcomputer MPU having an I / O interface (SIO) and a parallel serial I / O interface (PIO) connected to the address line (ADRRES), data line (DATA) and control line (CONTROL) of the flash memory MEM are doing. This memory card 94A, 94
When B is connected to the card connector 95A or the card connector 95B, power is supplied from the apparatus main body to the microcomputer MPU via the card connector.

Here, the memory cards 94A and 94B are
The application recognizes the port and card connector as a file device identified by a two-digit hexadecimal number. The memory cards 94A, 94B
Implements an automatic initialization function when a file is opened. When the memory cards 94A and 94B are connected to the card connector 95A or the card connector 95B and power is supplied from the apparatus main body, the microcomputer MPU first sets the internal state to the “uncommunicated” state. Thereafter, communication via the communication controller 91 is accepted.

Then, the CPU 51 of the apparatus main body determines whether the card connector 95A or the card connector 95A is based on a field representing the "internal state" in the response packet for confirming the connection from the card to the host in the communication protocol. By testing the internal state of the microcomputer MPU built in the memory cards 94A and 94B connected to the memory card 95B, the communication with the newly connected memory cards 94A and 94B in the case of "not communicating". You can recognize that. Then, the structure of the file management data with the newly connected memory cards 94A and 94B, for example, information such as a file name, a file size, a slot number and a status is read.

With such a communication protocol, it is possible to perform communication corresponding to dynamic insertion and removal of the memory cards 94A and 94B. Thereby, game settings and the like can be stored in the two memory cards 94A and 94B. In addition, two memory cards 94A, 94
4B, data can be directly copied, and various data can be simultaneously taken directly from the two memory cards 94A, 94B into the apparatus main body.

Further, the CPU 51 on the apparatus main body side includes:
Card connector 95A or card connector 95B
The control of writing data to a plurality of memory cards connected to the memory card is performed, for example, according to the procedure shown in the flowchart of FIG.
That is, when writing data over a plurality of memory cards, first, in step S1, an offset offset indicating the order of the memory cards is set to 0, and in the next step S2, the size of the data to be saved, that is, the data amount is set. Calculate the total number of required memory cards.

Then, in the next step 3, it is determined whether or not a memory card that is not used, that is, all memory blocks are empty, is mounted in the 0th card slot allocated to the card connector 95A. If the decision result in this step 3 is "NO", that is, if an unused memory card is not inserted in the 0th card slot, the process moves to step 4 and the decision result is "YE".
S], that is, if an unused memory card is inserted in the 0th card slot, the process proceeds to step 6.

In step 4 described above, it is determined whether or not a memory card that is unused, that is, all memory blocks are empty, is mounted in the first card slot allocated to the card connector 95B. If the determination in step 4 is "NO", that is, if an unused memory card is not inserted in the first card slot, the process proceeds to step 5; If an unused memory card is inserted, the process proceeds to step S7.

In step 5 above, a message "Please insert an unused memory card" is displayed to inform the user that an unused memory card should be inserted in the 0th or 1st card slot. Return to step 3. In step 6, the 0th card slot in which an unused memory card is installed is selected,
Specify as a slot to write data. Then, the process proceeds to Step 8.

Further, in step 7, the first card slot in which an unused memory card is mounted is selected and designated as a slot for writing data.
Then, the process proceeds to Step 8. In step 8 above, the name and offset offs are added to the header area of the file.
record the number of cards and the total number of cards. Thereby, the memory card in which the data has been written can be specified.

In the next step 9, data is written and the pointer on the main memory 53 is changed to the head of the next write. In the next step 10, the offset offset
Increment t. Then, in the next step 11, it is determined whether or not all writing has been completed. If the determination in step 11 is "NO", that is, if there is data to be written, the process returns to step 3 to continue the data writing control. Ends the data write control.

The CPU 51 of the apparatus main body controls reading of data from a plurality of memory cards connected to the card connector 95A or the card connector 95B, for example, according to the procedure shown in the flowchart of FIG.
That is, when reading data across a plurality of memory cards, first, in step S21, an offset offset indicating the order of the memory cards is set to 0, and in the next step S22, the size of the data to be loaded, that is, the data amount is calculated. Calculate the total number of required memory cards.

In the next step S23, it is determined whether or not a target memory card in which data of a file to be loaded is written in the 0th card slot allocated to the card connector 95A. . If the decision result in the step S23 is "NO", that is, if the target memory card is not installed in the 0th card slot, the process proceeds to the step S24. If the memory card is inserted, the process proceeds to step S16.

In step S24, it is determined whether or not a target memory card in which data of a file to be loaded is written in the first card slot allocated to the card connector 95B. If the determination result in step S24 is “NO”, that is, 1
If the target memory card is not installed in the first card slot, the process proceeds to step S25. If the determination result is "YES", that is, if the target memory card is installed in the first card slot, the process proceeds to step S25. S2
Move to 7.

The above steps S23 and S23
The determination process in 24 is performed by detecting a match between the offsets offset recorded in the header area of the file. In step S25, a message "Please insert an offset-th memory card" is displayed to inform the user that a target memory card should be inserted in the 0th or 1st card slot, and the above-mentioned step S23 is displayed. Return to

In step 6, the 0th card slot in which the target memory card is mounted is selected and designated as a slot from which data is read. Then, the process proceeds to step S28. Further, the above step S2
In step 7, the first card slot in which the target memory card is mounted is selected and designated as a slot from which data is read. Then, the process proceeds to step S28.

In step S28, the data is read, and the pointer on the main memory 53 is changed to the head of the next read. In the next step S29, the offset offset is incremented. Then, in the next step S30, it is determined whether or not all readings have been completed. If the determination result in step S30 is "NO", that is, if there is data to be read, the process returns to step S23 to continue the data read control. Ends the data reading control.

As described above, in the video game apparatus of this embodiment, a plurality of card slots to which a memory card is connected as an external secondary storage device are connected to the host CPU 51 via the communication control section 91 connected to the main bus 100. Independently control the writing and / or reading of data over a plurality of memory cards, so that a plurality of small-capacity memory cards can be used as a large-capacity external secondary storage device, and a plurality of memory cards can be used. It is possible to back up game software having a large amount of data over a card.

The memory cards 94A and 94B
Is made of a flash memory that is randomly accessible and does not require a backup power supply, so that data can be stored semi-permanently. This video game device is connected to a parallel input / output (I /
O) 101 and a serial input / output (I / O) 102. Then, connection with peripheral devices can be performed via the parallel I / O 101,
In addition, communication with another video game device can be performed via the serial I / O 102.

[0045]

As described above, according to the video game device of the present invention, the external secondary storage device can be replaced while the power of the game device body is turned on.

[0046]

[0047]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a video game device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a memory card used in the video game device.

FIG. 3 is a flowchart showing a procedure of controlling writing of data to a plurality of memory cards by a host CPU of the apparatus main body in the video game apparatus.

FIG. 4 is a flowchart showing a procedure for controlling reading of data from a plurality of memory cards by a host CPU of the apparatus main body side in the video game apparatus.

[Explanation of symbols]

 Reference Signs List 50 control system 51 CPU 52 peripheral device control unit 53 main memory 54 ROM 60 graphic system 61 GTE 62 GPU 63 frame buffer 64 image decoder 65 display device 70 sound system 71 SPU 72 sound buffer 73 speaker 80 optical disk control unit 81 optical disk device 82 decoder 83 buffer 90 communication controller 91 communication controller 92 controller 93 slot 94A, 94B memory card 95A, 95B card connector 1100 bus 101 parallel I / O 102 serial I / O

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sadaharu Toyo 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-4-26432 (JP, A) 4-24153 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) A63F 13/00-13/12 A63F 9/24 G06K 17/00

Claims (5)

(57) [Claims] 1. A video game apparatus having a function of secondary storage of game data and the like by an external secondary storage device, comprising a serial I / O for detachably connecting a main bus to the external secondary storage device. A slot having an interface, a communication controller for connecting the main bus and the slot, and a central processing unit connected to the main bus, the central processing unit via the communication controller A video game device that controls writing of data to an external secondary storage device connected to the slot and / or reading of data from the external secondary storage device. 2. A video game apparatus having a function of secondary storage of game data and the like by an external secondary storage device, wherein a serial I / O for detachably connecting a main bus and the external secondary storage device is provided. A slot having an interface, a communication controller for electrically separating and connecting the main bus and the slot, and a central processing unit connected to the main bus, wherein the central processing unit is A video game device which controls writing of data to an external secondary storage device connected to the slot and / or reading of data from the external secondary storage device via a communication controller. 3. The video game device according to claim 1, wherein the communication controller controls communication between the main bus and the serial I / O interface. 4. The central processing unit has a connection determination function for determining whether or not the external secondary storage device is connected to the slot, and only when it is determined that the external secondary storage device is connected, 2. A data writing and / or reading data to / from an external secondary storage device is controlled.
The video game device according to any one of claims 3 to 3. 5. The video game device according to claim 1, comprising a plurality of said slots.