JPH08161438A - Video game device - Google Patents

Abstract

PURPOSE: To provide the video game device with which plural external second- order storage devices with a little capacity can be used as an external second- order storage device with large capacity. CONSTITUTION: This device is provided with a communication control part 90 connected to a main bus, to which a central processing unit 51 (CPU) at the main body of the device is connected, and plural card connectors 95A and 95B, namely, card slots, to which memory cards 94A and 94B are freely attachably and detachably connected, connected through the communication control part 90 to the main bus 100, and the respective card slots are independently managed through the communication control part 90 by the CPU 51 so that the write and/or read of data over the plural external second-order storage devices can be controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video game device such as a home TV game machine, and more particularly to a video game device having a function of secondary storage of game data and the like.

[0002]

2. Description of the Related Art Conventionally, in a video game device such as a home TV game machine, a random access memory (RAM: Random Access Memory) built in the device body for data backup.
emory), a static random access memory (SRAM:
Static Random Access Memory), a RAM cartridge that is inserted into a slot that also serves as a game cartridge, or a combination thereof, so that game data and the like are secondarily stored.

[0003]

In a conventional video game device having a function of secondary storage of game data and the like as described above, it is not possible to simultaneously connect a plurality of external secondary storage devices to the main body of the device. Data cannot be directly copied between a plurality of external secondary storage devices. Also,
In a competitive game in which a plurality of players participate at the same time, the data of each player cannot be directly fetched into the device body at the same time. Therefore, when a plurality of external secondary storage devices are used, there is a problem in that they must be replaced, and it takes time and labor to transfer the data.

Further, in an external secondary storage device using a RAM cartridge which is inserted into a slot which is also used as a game cartridge, since it is directly connected to the bus of the main body of the apparatus, it is possible to turn on the power of the main body of the apparatus, that is, in the middle of the game. It cannot be removed or inserted, which is inconvenient when handling game software having a large amount of data across a plurality of external secondary storage devices. Further, for example, if the storage capacity of the external secondary storage device becomes insufficient during backup, the power of the device main body must be turned off once, and the game data that needs to be backed up is lost. There was a problem that it would end up.

Further, in the conventional external secondary storage device which is randomly accessible, since it is backed up by the battery, if the capacity of the battery is exhausted and the backup cannot be performed, the data will be lost.
There was a problem that data could not be stored semipermanently. Therefore, in view of the problems in the conventional video game device as described above, an object of the present invention is to allow a plurality of small-capacity external secondary storage devices to be used as a large-capacity external secondary storage device. It is an object of the present invention to provide a video game device capable of backing up game software or the like having a large amount of data in the secondary storage device.

Another object of the present invention is to provide a video game device capable of directly copying data between a plurality of external secondary storage devices. Another object of the present invention is to provide a video game device capable of directly loading each data from a plurality of external secondary storage devices into the device body at the same time. An object of the present invention is to provide a video game device in which an external secondary storage device can be replaced while the power of the device main body is turned on.

It is an object of the present invention to provide a video game device capable of semi-permanently storing data by an external secondary storage device.

[0008]

SUMMARY OF THE INVENTION The present invention is a video game device having a function of secondary storage of game data and the like by an external secondary storage device, which is a main bus to which a central processing unit of the device main body is connected. And a plurality of slots connected to the main bus via the communication control unit and detachably connected to an external secondary storage device, wherein the central processing unit is the communication unit. It is characterized by having a control function of managing each slot independently via a control unit and controlling writing and / or reading of data across a plurality of external secondary storage devices.

The video game device according to the present invention is characterized in that the central processing unit has a connection determination function for determining whether or not an external secondary storage device is connected to the slot. Further, the video game device according to the present invention is characterized in that an external secondary storage device comprising a flash memory is connected to the slot.

[0010]

In the video game device according to the present invention, the plurality of slots to which the plurality of external secondary storage devices are connected are independently managed by the central processing unit via the communication control unit connected to the main bus. Thus, the writing and / or reading of the data across the plurality of external secondary storage devices is controlled.

In the video game device according to the present invention, the central processing unit determines whether or not an external secondary storage device is connected to the slot, and manages each slot independently. In addition, in the video game device according to the present invention, the game data and the like can be stored in an external secondary storage device including a flash memory connected to the slot.
I will remember it next time.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a video game device according to the present invention will be described in detail below with reference to the drawings. A video game device according to the present invention, for example, configured as shown in FIG. This video game device plays a game according to an instruction from a user by reading and executing a game program stored in an auxiliary storage device such as an optical disc, as shown in FIG. In addition, a control system 50 including a central processing unit (CPU) 51 and peripheral devices thereof, and an image processing device (GPU: Graphic Process) for drawing in a frame buffer 63.
ing Unit) 62 and the like graphic system 60
And a sound processing device (SPU: Sound
Processing unit) etc. sound system 70
And an optical disk controller 80 for controlling an optical disk which is an auxiliary storage device, and an input / output from an auxiliary memory for storing an instruction input from a controller for inputting an instruction from a user and a game setting. Communication controller 90
And a bus 100 to which the control system 50 to the communication control unit 90 are connected.

The control system 50, CPU 51, and interrupt control and direct memory access (DMA: Dynamic Memory).
y Access) Peripheral device controller 52 that controls transfer and random access memory (RAM: Random Acce
Main memory (main memory) 53 composed of ss Memory)
And a read only memory (ROM) 54 storing a program such as a so-called operating system for managing the main memory 53, the graphic system 60, the sound system 70 and the like. The CPU 51 controls the entire apparatus by executing the operating system stored in the ROM 54, and is a 32-bit RISC CPU.
Consists of

In the video game device, when the power is turned on, the CPU 51 of the control system 50 causes the ROM 51
By executing the operating system stored in 54, the CPU 51 controls the graphic system 60, the sound system 70 and the like. When the operating system is executed, the CPU 51 initializes the entire device such as operation confirmation and then controls the optical disc control unit 80 to execute a program such as a game recorded on the optical disc. Run. By executing the program of this game or the like, the CPU 51 controls the graphic system 60, the sound system 70, and the like according to the input from the user to control the display of images, the generation of sound effects, and the generation of musical sounds.

Further, the graphic system 60 is
A geometry transfer engine (GTE) 61 that performs processing such as coordinate conversion, and a CPU 5
A GPU 62 that draws in accordance with a drawing instruction from 1.
A frame buffer 63 for storing an image drawn by the GPU 62 and an image decoder 64 for decoding image data compressed and encoded by orthogonal transform such as discrete cosine transform are provided.

The GTE 61 has, for example, a parallel operation mechanism for executing a plurality of operations in parallel, and can perform coordinate conversion, light source calculation, and matrix or vector calculations at high speed in response to a calculation request from the CPU 51. It is like this. Specifically, this GTE 61 is, for example, 1
In the case of calculation that performs flat shading that draws the same color on two triangular polygons, maximum 1 per second
It is possible to calculate the coordinates of about 500,000 polygons. This makes it possible to reduce the load on the CPU 51 and perform high-speed coordinate calculations in this video game device. .

Further, the GPU 62 draws a polygon or the like on the frame memory 62 according to a drawing command from the CPU 51. This GPU 62 is
A maximum of about 360,000 polygons can be drawn in one second. Further, the frame buffer 63 is composed of a so-called dual port RAM,
Drawing from the GPU 62 or transfer from the main memory and reading for display can be performed at the same time. This frame buffer 63 is 1
It has a capacity of M bytes and is 16 bits wide by 102 each.
4 is treated as a matrix of 512 vertical pixels. In addition to the display area output as video output, the frame buffer 63 also includes a color look-up table to which the GPU 62 refers when drawing polygons and the like.
A CLUT area that stores (CLUT: Cclor Lock Up Table), and a texture area that stores the material (texture) that is inserted (mapped) into polygons that are coordinate-converted during drawing and drawn by the GPU 62 are provided. Has been. These CLUT area and texture area are dynamically changed according to the change of the display area and the like.

In addition to the above flat shading, the GPU 62 pastes the Gouraud shading that complements the colors of the vertices of the polygon to determine the color within the polygon and the texture stored in the texture area to the polygon. Texture mapping can be performed. When performing these Gouraud shading or texture mapping, the above G
The TE 61 can perform coordinate calculation of up to about 500,000 polygons per second.

Further, the image decoder 64 is the CPU
Under the control of 51, the image data of the still image or the moving image stored in the main memory 53 is decoded and stored in the main memory 53. The reproduced image data is stored in the frame buffer 63 via the GPU 62 so that it can be used as the background of the image drawn by the GPU 62.

The sound system 70 includes a CPU 51.
SP that generates musical sounds, sound effects, etc. based on instructions from
A U71, a sound buffer 72 for recording waveform data and the like by the SPU 71, and a speaker 73 for outputting a musical sound, a sound effect, etc. generated by the SPU 71 are provided. The SPU 71 uses 16-bit voice data as a 4-bit differential signal in adaptive predictive coding (ADPCM: Adapt).
AD for playing back audio data that has been subjected to ive Diffrential PCM
A PCM decoding function, a reproducing function for generating a sound effect or the like by reproducing the waveform data stored in the sound buffer 72, a modulating function for modulating and reproducing the waveform data stored in the sound buffer 72, etc. Is equipped with.

By having such a function, the sound system 70 can be used as a so-called sampling sound source for generating a musical sound, a sound effect, etc. based on the waveform data recorded in the sound buffer 72 according to an instruction from the CPU 51. You can do it. The optical disc control unit 80 is an optical disc device 81 for reproducing a program, data, etc. recorded on the optical disc.
Error correction code (ECC).
a decoder 82 for decoding a program, data, etc. recorded with e) added thereto, and a buffer 83 for speeding up reading from an optical disc by temporarily storing reproduction data from the optical disc device 81. Is equipped with.

As the audio data recorded on the optical disk reproduced by the optical disk device 81, there is so-called PCM data obtained by analog / digital conversion of an audio signal in addition to the ADPCM data described above. ADPCM
As data, for example, audio data recorded by representing the difference of 16-bit digital data by 4 bits is
After being decoded by the decoder 82, it is supplied to the above-mentioned SPU 71, subjected to processing such as digital / analog conversion in the SPU 71, and then used for driving the speaker 73.

Audio data recorded as PCM data, for example, as 16-bit digital data is decoded by the decoder 82 and then used to drive the speaker 73. Furthermore, the communication control unit 90
A slot 93 to which a communication controller 91 for controlling communication with the CPU 51 via the bus 100 is connected, to which a controller 92 for inputting an instruction from a user is connected, and an external device 2 for secondary storage of game setting data and the like 2 as next storage
The communication controller 91 is provided with two card connectors 95A and 95B to which the memory cards 94A and 94B are connected.

The controller 92 connected to the slot 93 has, for example, 16 instruction keys for inputting an instruction from the user, and changes the state of the instruction key according to the instruction from the communication controller 91. , Is transmitted to the communication controller 91 about 60 times per second by synchronous communication. Then, the communication controller 91 changes the state of the instruction key of the controller 92 to C.
It transmits to PU51.

As a result, the instruction from the user is sent to the CPU 5
1 is input to the CPU 51, and the CPU 51 performs processing according to an instruction from the user based on the game program or the like being executed. Here, between the main memory 53, the GPU 62, the image decoder 64, the decoder 82, etc., it is necessary to transfer a large amount of image data at high speed when reading a program, displaying an image, drawing, or the like. Therefore, in this video game device, as described above, the CPU
The so-called DMA transfer for directly transferring data between the main memory 53, the GPU 62, the image decoder 64, the decoder 82 and the like can be performed by the control of the peripheral device control section 52 without passing through 51. . As a result, the load on the CPU 51 due to data transfer can be reduced, and high-speed data transfer can be performed.

Further, when it is necessary to store the setting data of the game being executed, the CPU 51 transmits the stored data to the communication controller 91, and the communication controller 9
1 is the data from the CPU 51, the card connector 95
The data is stored in the memory card 94A or the memory card 94B connected to A or the card connector slot. Here, the communication controller 91 has a built-in protection circuit for preventing electrical breakdown. Memory card 9 above
4A and 94B are separated from the bus 100, and can be attached and detached with the main body of the device turned on. Therefore, if the storage capacity becomes insufficient, a new memory card can be installed without shutting off the power of the device body, and game data that needs to be backed up is not lost You can install a memory card and write the necessary data to a new memory card.

Further, the memory cards 94A, 94B
Is a flash memory MEM that is randomly accessible and does not require a backup power supply, as shown in FIG.
And control lines DTX and DT via the card connector.
Serial I connected to R, signal lines RXD and TXD for data transmission, and signal line SCK for serial synchronization clock
Built-in microcomputer MPU having an I / O interface (SIO) and a parallel serial I / O interface (PIO) connected to the address line (ADRRES), data line (DATA) and control line (CONTROL) of the flash memory MEM. are doing. This memory card 94A, 94
When B is connected to the card connector 95A or the card connector 95B, power is supplied from the apparatus main body to the microcomputer MPU via the card connector.

Here, the memory cards 94A and 94B are
From the application, it is recognized as a file device identified by a 2-digit hexadecimal number that specifies a port and a card connector. In addition, this memory card 94A, 94B
Implements an automatic initialization function when opening a file. The microcomputer MPU first sets the internal state to the "uncommunication" state when the memory cards 94A and 94B are connected to the card connector 95A or the card connector 95B and power is supplied from the apparatus body. After that, communication via the communication controller 91 is accepted.

Then, the CPU 51 on the apparatus main body side, based on the field indicating the "internal state" in the reply packet for confirming the connection from the card to the host in the communication protocol, either the card connector 95A or the card connector. By testing the internal state of the microcomputer MPU built in the memory cards 94A, 94B connected to the 95B, it is possible to communicate with the newly connected memory cards 94A, 94B in the case of "not communicating". You can recognize that. Then, the structure of file management data with the newly connected memory cards 94A and 94B, for example, information such as file name, file size, slot number and status is read.

With such a communication protocol, it is possible to perform communication corresponding to the dynamic insertion and removal of the memory cards 94A and 94B. As a result, game settings and the like can be stored in the two memory cards 94A and 94B. Also, two memory cards 94A, 9
It is possible to directly copy the data with 4B or to take in various data from the two memory cards 94A and 94B directly to the main body of the apparatus at the same time.

Further, the CPU 51 on the apparatus main body side is
The above card connector 95A or card connector 95B
The data write control to the plurality of memory cards connected to is performed by the procedure shown in the flowchart of FIG. 3, for example.
That is, when writing data over a plurality of memory cards, first in step S1, the offset offset indicating the order of the memory cards is set to 0, and in the next step S2, the size of the data to be saved, that is, the amount of data is determined. Calculate the total number of required memory cards.

Then, in the next step 3, it is judged whether or not a memory card which is unused, that is, has all memory blocks vacant, is attached to the 0th card slot assigned to the card connector 95A. If the determination result in step 3 is "NO", that is, if an unused memory card is not loaded in the 0th card slot, the process proceeds to step 4, and the determination result is "YE
[S], that is, when an unused memory card is mounted in the 0th card slot, the process proceeds to step 6.

In step 4, it is determined whether or not a memory card that is unused, that is, has a free memory block, is attached to the first card slot assigned to the card connector 95B. If the determination result in this step 4 is "NO", that is, if an unused memory card is not inserted in the first card slot, the process proceeds to step 5, and the determination result is "YES", that is, the first card slot. If an unused memory card is installed, the process proceeds to step 7.

In step 5 above, a message "Please insert an unused memory card." Is displayed to inform the user that an unused memory card should be inserted in the 0th or 1st card slot. Return to step 3. In step 6 above, select the 0th card slot in which an unused memory card is installed,
Designate as a slot to write data. Then, the process proceeds to step 8.

Further, in the above step 7, the first card slot in which an unused memory card is mounted is selected and designated as a slot for writing data.
Then, the process proceeds to step 8. Then, in step 8, the name and offset offs are added to the header area of the file.
Record et and total card count. As a result, the memory card in which the data has been written can be specified.

In the next step 9, data is written and the pointer in the main memory 53 is changed to the beginning of the next writing. In the next step 10, offset offset
Increment t. Then, in the next step 11, it is determined whether or not all writing has been completed. If the determination result in step 11 is "NO", that is, there is data to be written, the process returns to step 3 and the data write control is continued, and if the determination result is "YES", that is, there is no data to be written. Ends the data write control.

The CPU 51 on the apparatus main body side controls the reading of data from a plurality of memory cards connected to the card connector 95A or the card connector 95B, for example, by the procedure shown in the flowchart of FIG.
That is, when reading data across a plurality of memory cards, first, in step S21, the offset offset indicating the order of the memory cards is set to 0, and in the next step S22, the size of the data to be loaded, that is, the data amount is determined. Calculate the total number of required memory cards.

Then, in the next step S23, it is determined whether or not the target memory card in which the data of the file to be loaded is written is attached to the 0th card slot assigned to the card connector 95A. . If the determination result in step S23 is "NO", that is, if the target memory card is not mounted in the 0th card slot, the process proceeds to step S24, and if the determination result is "YES", that is, the target card is in the 0th card slot. If the memory card is loaded, the process moves to step 16.

In step S24, it is determined whether or not a target memory card in which data of a file to be loaded is written is attached to the first card slot assigned to the card connector 95B. The determination result in step S24 is "NO", that is, 1
If the target memory card is not mounted in the second card slot, the process proceeds to step S25, and if the determination result is “YES”, that is, if the target memory card is mounted in the first card slot, the step is performed. S2
Go to 7.

The steps S23 and S
The determination processing in 24 is performed by detecting the coincidence of the offset offset recorded in the header area of the file. Then, in the step S25, a message "Please insert the offset th memory card." Is displayed to inform the user that the target memory card should be inserted in the 0th or 1st card slot. Return to.

In step 6, the 0th card slot in which the target memory card is mounted is selected and designated as the slot for reading data. Then, the process proceeds to step S28. Further, the above step S2
In step 7, the first card slot in which the target memory card is mounted is selected and designated as the slot from which data is read. Then, the process proceeds to step S28.

Then, in step S28, the data is read and the pointer on the main memory 53 is changed to the beginning of the next reading. In the next step S29, the offset offset is incremented. Then, in the next step S30, it is determined whether or not all reading is completed. If the determination result in step S30 is "NO", that is, if there is data to be read, the process returns to step S23 to continue the data read control, and if the determination result is "YES", that is, there is no data to write. Ends the data read control.

As described above, in the video game apparatus of this embodiment, the host CPU 51 is provided with a plurality of card slots to which memory cards are connected as external secondary storage devices via the communication control unit 91 connected to the main bus 100. Are independently managed to control writing and / or reading of data across a plurality of memory cards, so that a plurality of small capacity memory cards can be used as a large capacity external secondary storage device, and a plurality of memories can be used. It is possible to back up game software and the like that has a large amount of data over the card.

In addition, the memory cards 94A and 94B
Is a flash memory that can be randomly accessed and does not require a backup power source, so that data can be stored semipermanently. In addition, this video game device has a parallel input / output (I / I) connected to the bus 100.
O) 101 and serial input / output (I / O) 102. Then, it is possible to connect to peripheral devices via the parallel I / O 101.
Also, communication with other video game devices can be performed via the serial I / O 102.

[0045]

As described above, in the video game device according to the present invention, a plurality of slots to which a plurality of external secondary storage devices are connected are centrally operated via the communication control unit connected to the main bus. Since the processing device independently manages and controls writing and / or reading of data across a plurality of external secondary storage devices, a plurality of small-capacity external secondary storage devices can be used as a large-capacity external secondary storage device. It can be used, and it is possible to back up game software having a large amount of data across a plurality of external secondary storage devices.

Further, in the video game device according to the present invention, the plurality of slots to which the plurality of external secondary storage devices are connected are independently operated by the central processing unit via the communication control unit connected to the main bus. By managing, data can be directly copied between a plurality of external secondary storage devices. Further, each data can be directly fetched from the plurality of external secondary storage devices directly into the device body.

Further, in the video game device according to the present invention, the game data and the like are secondarily stored by the external secondary storage device composed of the flash memory connected to the slot, so that the data can be semipermanently saved. it can

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video game device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a memory card used in the video game device.

FIG. 3 is a flowchart showing a procedure for controlling writing of data to a plurality of memory cards by a host CPU on the apparatus main body side in the above video game apparatus.

FIG. 4 is a flow chart showing a procedure of controlling reading of data from a plurality of memory cards by a host CPU on the apparatus main body side in the video game apparatus.

[Explanation of symbols]

 50 Control system 51 CPU 52 Peripheral device control unit 53 Main memory 54 ROM 60 Graphic system 61 GTE 62 GPU 63 Frame buffer 64 Image decoder 65 Display device 70 Sound system 71 SPU 72 Sound buffer 73 Speaker 80 Optical disc control unit 81 Optical disc device 82 decoder 83 buffer 90 communication controller 91 communication controller 92 controller 93 slot 94A, 94B memory card 95A, 95B card connector 1100 bus 101 parallel I / O 102 serial I / O

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sadaharu Toyohashi 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (3)

[Claims] 1. A video game device having a function of secondary storage of game data and the like by an external secondary storage device, comprising a communication control unit connected to a main bus to which a central processing unit of the device main body is connected. A plurality of slots connected to the main bus via the communication controller and detachably connected to an external secondary storage device, wherein the central processing unit connects each slot via the communication controller. A video game device characterized by having a control function of independently managing and controlling writing and / or reading of data across a plurality of external secondary storage devices. 2. The video game device according to claim 1, wherein the central processing unit has a connection determination function for determining whether or not an external secondary storage device is connected to the slot. 3. The video game device according to claim 1, wherein a memory card having a built-in flash memory as an external secondary storage device is connected to the slot.