JP7091223B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine that performs a lottery process due to a gaming operation and executes an image effect corresponding to the lottery result, and more particularly to a gaming machine that can stably execute a powerful image effect.

A ball game machine such as a pachinko machine is equipped with a symbol start port provided on the game board, a symbol display unit that displays a series of symbol variation modes by a plurality of display symbols, and a large winning opening for opening and closing the opening / closing plate. It is composed of. Then, when the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is set, and after the game ball is paid out as the prize ball, the displayed symbol is changed for a predetermined time on the symbol display unit. After that, when the symbol is stopped in a predetermined mode such as 7, 7, 7, a big hit state is reached, and the big winning opening is repeatedly opened to generate a game state advantageous to the player.

Whether or not to generate such a game state is determined by a big hit lottery executed on the condition that the game ball wins at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in the winning state, an effect operation called a reach action or the like is executed for about 20 seconds, and then special symbols are arranged. On the other hand, the same reach action may be executed even in the case of a lost state, and in this case, the player pays close attention to the transition of the staging operation while strongly paying attention to the big hit state. Then, if the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

JP-A-2017-093633 JP-A-2017-093632 Japanese Unexamined Patent Publication No. 2016-159030 Japanese Unexamined Patent Publication No. 2016-159029

In this type of gaming machine, there is a high demand for complicated and abundant various effects, especially for image effects. Therefore, although the applicant has made various proposals (Cited Documents 1 to 4), further sophistication of image production and improvement of image production control are desired.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine capable of performing improved image effect control.

In order to achieve the above object, the gaming machine according to the present invention is described in an image control means having a CPU circuit that issues a display list that specifies a display screen of the display device, and a display list issued by the image control means. Further, the image control means is configured to include an image generation means having a drawing circuit for generating image data based on an instruction command of an integer M (M ≧ 1) times the reference size, and the image control means is the CPU circuit. A DMAC circuit that repeats a DMA (Direct Memory Access) operation for each transfer unit data size based on instructions from the CPU, a control register in which setting values that specify the operation of the DMAC circuit are set, and a display list created by the CPU. The image control means is configured to have a list buffer to be stored, and the image control means has the transfer unit data size defined as an integral multiple (> 0) of the reference size and the head of the list buffer with respect to the DMA operation. The drawing after the instruction operation of the first means for instructing the address and the transfer destination of the display list, the second means for instructing the total data size of the display list to be transferred, and the first and second means. It is configured to have a third means for instructing the start of the operation of the DMAC circuit in a state where the drawing operation of the circuit is started, and the instruction operation of the first to third means writes an instruction value in the control register. The display list is configured by an instruction command that is an integer M (M ≧ 1) times the reference size, and the total data size is an integer N times (N ≧ 1) the transfer unit data size. To.

According to the above-described invention, it is possible to smoothly and appropriately perform an appropriate image control operation even in an advanced image production.

It is a perspective view which shows the pachinko machine of this Example. It is a front view which shows the gaming area of the gaming machine of FIG. It is a block diagram which shows the whole circuit composition of the gaming machine of FIG. It is a block diagram which shows the circuit structure of the staging control unit in a little detail about the gaming machine of FIG. It is a drawing explaining the composite chip which constitutes the staging control part. It is a drawing explaining the cycle steal transfer operation and the pipeline transfer about DMAC. It is a drawing explaining an index space, an index table, a virtual drawing space, and a drawing area. It is a block diagram which described the internal structure of a data transfer circuit together with the related circuit structure. It is a block diagram which described the internal structure of a display circuit together with the related circuit structure. It is a flowchart explaining the control operation of the staging control CPU 63 when the preloader is not used. It is a drawing explaining the structure of a display list. It is a flowchart which shows the DL issue process which issues a display list DL. It is a flowchart explaining the operation when DMAC is involved in the operation of FIG. It is a flowchart explaining the operation following the process of FIG. It is a flowchart explaining the control operation of the staging control CPU 63 about the case of using a preloader. It is a flowchart explaining a part of FIG. It is a flowchart explaining another part of FIG. It is a time chart which shows the operation of each part of VDP about the Example which does not use a preloader. It is a time chart which shows the operation of each part of VDP about the Example which uses the preloader. It is a block diagram which shows the whole circuit composition about another Example. It is a block diagram which shows a part of FIG. 20 in a little detail. It is a flowchart explaining the operation content about another Example.

Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing the pachinko machine GM of this embodiment. This pachinko machine GM consists of a rectangular frame-shaped wooden outer frame 1 that is detachably attached to the island structure and a front frame 3 that is pivotally attached to the outer frame 1 via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 not from the back side but from the front side, and a glass door 6 and a front plate 7 are pivotally attached to the front side thereof so as to be openable and closable.

Illuminations lamps such as LED lamps are arranged in a substantially C shape on the outer periphery of the glass door 6. On the other hand, a total of three speakers are arranged at the upper left and right positions and the lower side of the glass door 6. The two speakers arranged at the upper part are configured to output the sound of the left and right channels R and L, respectively, and the lower speaker is configured to output the bass sound.

An upper plate 8 for storing a game ball for launch is mounted on the front plate 7, and a lower plate 9 for storing a game ball overflowing or extracted from the upper plate 8 and a launch handle are at the lower part of the front frame 3. 10 is provided. The launch handle 10 is interlocked with the launch motor, and the game ball is launched by a hitting mallet that operates according to the rotation angle of the launch handle 10.

A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and the operation is possible. The button chance state is a game state provided as needed.

Further, a rotary switch type volume switch VLSW is arranged below the chance button 11, and the player operates the volume switch VLSW to change the level from silence level (= 0) to the highest level (= 7). The speaker volume can be adjusted in 8 steps. The volume of the speaker is initially set by a setting switch (not shown) that can be operated only by the staff, and the initial set volume is maintained unless the player operates the volume switch VLSW. In addition, the abnormality notification sound for notifying that an abnormal situation has occurred is emitted at the maximum volume regardless of the initial set volume by the staff or the set volume of the player.

On the right side of the upper plate 8, an operation panel 12 for ball lending operation for a card-type ball lending machine is provided, a frequency display unit that displays the remaining amount of the card with a three-digit number, and a game ball for a predetermined amount. A ball lending switch for instructing lending and a return switch for instructing the return of the card at the end of the game are provided.

As shown in FIG. 2, on the surface of the game board 5, a guide rail 13 composed of an outer rail and an inner rail made of metal is provided in an annular shape, and a central opening HO is provided in the substantially center thereof. A movable effect body (not shown) is stored under the central opening HO in a concealed state, and at the time of the movable notice effect, the movable effect body rises and becomes an exposed state, so that the predetermined reliability is achieved. The notice production is realized. Here, the advance notice effect is an effect of uncertainly notifying the player that a jackpot state advantageous to the player will be invited, and the reliability of the advance notice effect means the probability that the big hit state will be invited.

A main display device DS1 composed of a large (for example, 1280 horizontal × 1024 vertical pixels) liquid crystal color display (LCD) is arranged in the central opening HO, and a small size (for example, horizontal) is arranged on the right side of the main display device DS1. A movable sub-display device DS2 composed of a liquid crystal color display (480 × 800 pixels in height) is arranged. The main display device DS1 is a device that displays a specific symbol related to a jackpot state in a variable manner and displays a background image, various characters, and the like in an animation manner. The display device DS1 has a special symbol display unit Da to Dc in the central portion and a normal symbol display unit 19 in the upper right portion. Then, in the special symbol display units Da to Dc, a reach effect that is expected to invite a big hit state may be executed, and an appropriate notice effect or the like is executed in the special symbol display units Da to Dc and its surroundings.

Normally, the sub-display device DS2 displays image information in a stationary state in which the display screen is tilted at an angle that is easy for the player to see. However, at the time of the predetermined advance notice effect, the predetermined advance notice image is displayed while moving to the left side of the figure while changing the inclination angle to an angle that is easy for the player to see.

That is, the sub-display device DS2 of the embodiment is not only a display device but also functions as a movable staging body that executes a warning staging. Here, the notice effect by the sub-display device DS2 is set with high reliability, and the player pays attention to the moving operation of the sub-display device DS2 with great expectation.

By the way, in the game area where the game ball falls and moves, the first symbol start opening 15a, the second symbol start opening 15b, the first big winning opening 16a, the second big winning opening 16b, the normal winning opening 17, and the gate 18 Are arranged. Each of these winning openings 15 to 18 has a detection switch inside, so that the passage of a game ball can be detected.

At the upper part of the first symbol start port 15a, an effect stage 14 configured to be able to win a prize in the first symbol start port 15 is arranged after the game ball entering from the introduction port IN moves in a seesaw shape or a roulette shape. There is. Then, when the game ball wins a prize in the first symbol start opening 15, the special symbol display units Da to Dc are configured to start the variable operation.

The second symbol start port 15b is configured to be opened and closed by an electric tulip equipped with a pair of left and right opening / closing claws, and when the stop symbol after the change of the normal symbol display unit 19 displays a hit symbol, it is predetermined. The opening / closing claws are opened only for a time or until a predetermined number of game balls are detected.

The normal symbol display unit 19 displays a normal symbol, and when a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted at the time when the game ball passes through the gate 18. The stop symbol determined by the lottery random value is displayed and stopped.

The first big winning opening 16a is configured to have a slide board that advances and retreats in the front-rear direction, and the second big winning opening 16b is configured to have an opening / closing plate whose lower end is pivotally supported and opened forward. .. The operation of the first big winning opening 16a and the second big winning opening 16b is not particularly limited, but in this embodiment, the first big winning opening 16a corresponds to the first symbol starting opening 15a and the second big winning opening. 16b is configured to correspond to the first symbol start port 15b.

That is, when the game ball wins in the first symbol start opening 15a, the variable operation of the special symbol display units Da to Dc is started, and then when the predetermined jackpot symbols are aligned with the special symbol display portions Da to Dc, the first jackpot The barrel special game is started, and the slide board of the first large winning opening 16a is opened forward to facilitate the winning of the game ball.

On the other hand, as a result of the variable operation started by winning the game ball to the second symbol start opening 15b, when the predetermined jackpot symbols are aligned with the special symbol display units Da to Dc, the second jackpot special game is started and the second jackpot is started. The opening / closing plate of the two major winning openings 16b is opened to facilitate the winning of the game ball. The game value of the special game (big hit state) varies depending on the big hit symbols that are lined up, but which game value is given is determined in advance based on the lottery result according to the winning timing of the game ball. It is determined.

In a typical big hit state, the opening / closing plate closes when a predetermined time elapses after the opening / closing plate of the large winning opening 16 is opened, or when a predetermined number (for example, 10) of game balls win a prize. Such an operation is continued up to, for example, 15 times, and is controlled in a state advantageous to the player. If the stop symbol after the change of the special symbol display units Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game is in a high probability state (probability change state). Granted.

FIG. 3 is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes each of the above-mentioned operations, and FIG. 4A is a detailed diagram of a part thereof.

As shown in FIG. 3, this pachinko machine GM has a power supply board 20 that receives AC24V and outputs various DC voltages, power supply abnormality signals ABN1 and ABN2, and a main control board 21 that is centrally responsible for game control operations. , An effect interface board 22 equipped with a circuit element SND for sound effect, and an effect control board 23 that uniformly executes lamp effect, sound effect, and image effect based on the control command CMD received from the main control board 21. The game ball is paid out by controlling the payout motor M based on the liquid crystal interface board 24 located between the effect control board 23 and the display devices DS1 and DS2 and the control command CMD'received from the main control board 21. It is mainly composed of a payout control board 25 and a launch control board 26 that launches a game ball in response to a player's operation.

In the case of this embodiment, the staging interface board 22, the staging control board 23, and the liquid crystal interface board 24 are directly connected to the male connector and the female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire substrate can be minimized, and noise resistance can be improved by minimizing the connection line.

As shown in the figure, the control command CMD'output by the main control board 21 is transmitted to the payout control board 25 via the main board relay board 33. On the other hand, the control command CMD output by the main control board 21 is transmitted to the staging control board 23 via the staging interface board 22. The control commands CMD and CMD'are both 16-bit length, but are transmitted in parallel in two steps every 8-bit length.

A computer circuit including a one-chip microcomputer is mounted on the main control board 21 and the payout control board 25. Further, the effect control board 23 is equipped with a composite chip 50 having a built-in computer circuit such as a VDP circuit (Video Display Processor) 52 and a built-in CPU circuit 51. Therefore, these control boards 21, 25, 23, the circuits mounted on the staging interface board 22 and the liquid crystal interface board 24, and the operations realized by the circuits are functionally collectively referred to in the present specification. , The main control unit 21, the staging control unit 23, and the payout control unit 25. The staging control unit 23 and the payout control unit 25 serve as sub-control units for the main control unit 21.

Further, the pachinko machine GM is roughly classified into a frame-side member GM1 surrounded by a broken line in FIG. 3 and a board-side member GM2 fixed to the back surface of the game board 5. The frame-side member GM 1 includes a front frame 3 to which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. It is fixedly installed in. On the other hand, the board-side member GM2 is replaced in response to the model change, and a new board-side member GM2 is attached to the frame-side member GM1 instead of the original board-side member. All except the frame-side member 1 are board-side members GM2.

As shown in the broken line frame of FIG. 3, the frame-side member GM 1 includes a power supply board 20, a payout control board 25, a launch control board 26, and a frame relay board 36, and these circuit boards are included. Each of the front frames 3 is fixed in place. On the other hand, on the back surface of the game board 5, a main control board 21 and an effect control board 23 are fixed together with display devices DS1 and DS2 and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by connection connectors C1 to C4 centrally arranged at one location.

The power supply board 20 is connected to the main board relay board 33 through the connection connector C2, and is connected to the power supply relay board 34 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors the on / off of the AC power supply. When the power supply monitoring unit MNT detects that the AC power supply is cut off, the power supply abnormality signals ABN1 and ABN2 are immediately transitioned to the L level. The power supply abnormality signals ABN1 and ABN2 immediately reach the H level after the power is turned on.

The main board relay board 33 outputs the power supply abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, DC32V output from the power supply board 20 to the main control unit 21 as they are. Further, the power supply relay board 34 outputs the AC and DC power supply voltages received from the power supply board 20 to the staging interface board 22 as they are.

As shown in the figure, a voice circuit SND such as a voice processor 27 is mounted on the effect interface board 22, and a composite chip 50 having a computer circuit such as a VDP circuit 52 and a CPU circuit 51 is mounted on the effect control board 23. It is installed.

Further, the effect interface board 22 is equipped with a reset circuit RST3 that detects an increase in the power supply voltage and generates a reset signal SYS (CPU reset signal) when the power is turned on. This CPU reset signal SYS is transmitted to the audio circuit SND of the staging interface board 22 and the composite chip 50 of the staging control board 23 to synchronously reset the power supply of each electronic element. As will be described later, when the program processing of the CPU circuit 51 is in an infinite loop state, the watchdog timer 58 (see FIG. 4A) built in the CPU circuit 51 is activated, and the audio circuit SND and the composite chip are activated. 50 is synchronously reset abnormally.

Next, the payout control board 25, which is a frame-side member GM1, is directly connected to the power supply board 20 without going through a relay board, and receives the same power supply abnormality signal ABN2 and backup power supply BAK as received by the main control unit 21. Received with the power supply voltage of. Further, the main control unit 21 and the payout control unit 25 are respectively equipped with reset circuits RST1 and RST2, and are configured to generate a power reset signal when the power is turned on and reset each computer circuit. ..

As described above, in this embodiment, the reset circuits RST1 to RST3 are arranged on the main control unit 21, the payout control unit 25, and the effect interface board 22, respectively, and the CPU reset signal SYS is transmitted between the circuit boards. Not transmitted. That is, since there is no wiring cable for transmitting the CPU reset signal SYS, the possibility that the computer circuit is abnormally reset due to the noise superimposed on the wiring cable is eliminated.

However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the payout control unit 25 each have a built-in watchdog timer, and do not receive a regular clear pulse from the CPUs of the control units 21 and 25. In that case, each CPU is forcibly reset.

Further, an initialization switch SW that can be operated by a staff member is arranged in the main control unit 21, and a RAM clear signal CLR indicating whether or not the initialization switch SW is turned ON is output when the power is turned on. It is configured. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the payout control unit 25, and determines whether or not to initialize the entire area of the built-in RAM of the one-chip microcomputers of the control units 21 and 25. ing.

Further, the main control unit 21 and the payout control unit 25 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary termination processing prior to a power failure or business termination. Further, the backup power supply BAK is a DC 5V DC power supply that retains the data of the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 even after the AC power supply 24V is cut off due to the closing of business or a power failure. Therefore, the main control unit 21 and the payout control unit 25 can restart the game operation before the power is cut off after the power is turned on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

As shown in FIG. 3, the main control unit 21 receives from the payout control unit 25 a prize ball counting signal indicating a payout operation of a game ball, a status signal CON related to an abnormality in the payout operation, and an operation start signal BGN. There is. The status signal CON includes, for example, a supply shortage signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 25 is completed after the power is turned on.

Further, the main control unit 21 is connected to each game component of the game board 5 via the game board relay board 32. Then, while receiving the switch signal of the detection switch built in each of the winning openings 16 to 18 on the game board, it drives solenoids such as electric tulips. The solenoids and the detection switch are configured to operate at the power supply voltage VB (12V) distributed from the main control unit 21. Further, each switch signal indicating the winning state of the symbol start port 15 is converted into a TTL level or CMOS level switch signal by an interface IC that operates at a power supply voltage VB (12V) and a power supply voltage Vcc (5V). After that, it is transmitted to the main control unit 21.

As described above, the effect interface board 22, the effect control board 23, and the liquid crystal interface board 24 are integrated by connecting the connectors, and the effect interface board 22 is powered via the power supply relay board 34. Each level of DC voltage (5V, 12V, 32V) is received from the substrate 20 (see FIGS. 3 and 4A).

As shown in FIG. 3, the staging interface board 22 receives the control command CMD and the strobe signal STB from the main control unit 21 and transfers them to the staging control board 23. More specifically, as shown in FIG. 4A, the control command CMD and the strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the staging control board 23 via the input buffer 40. ..

Further, the CPU reset signal SYS generated by the reset circuit RST3 is supplied to the effect control board 23 and the voice circuit SND such as the voice processor 27 via the input buffer 40 and the OR circuit G1. As shown in the figure, the underflow signal UF of the WDT circuit 58 is also supplied to the OR circuit G1, and when either of the two signals SYS or UF becomes the active level, the internal circuit of the composite chip 50 and the voice circuit SND Is synchronized and reset (abnormal reset). The internal circuit of the composite chip 50 to be abnormally reset includes a CPU circuit 51 and a VDP circuit 52, and the voice circuit SND to be abnormally reset includes a voice processor 27 and a voice memory 28.

As shown in FIG. 4A, the input buffer 44 of the effect interface board 22 receives the chance button 11 and the switch signal of the volume switch VLSW from the frame relay boards 35 and 36, and outputs each switch signal to the CPU of the effect control board 23. It is transmitted to the circuit 51. Specifically, a 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW and a 1-bit length indicating the ON / OFF state of the chance button 11 are transmitted to the CPU circuit 51.

Further, the lamp drive board 30 and the motor lamp drive board 31 are connected to the staging interface board 22, and are also connected to the lamp drive board 37 via the frame relay boards 35 and 36. As shown in the figure, the output buffer 42 is arranged corresponding to the lamp drive board 30, and the input buffer 43a and the output buffer 43b are arranged corresponding to the motor lamp drive board 31. In FIG. 4A, for convenience, the input buffer 43a and the output buffer 43b are collectively referred to as an input / output buffer 43. The input buffer 43a receives the outputs SN0 to SNn of the origin sensor that grasps the current position (rotation position of the effect motors M1 to Mn) of the accessory that is the movable effect body, and transmits the output to the CPU circuit 51 of the effect control board 23. There is.

The same type of driver IC is mounted on the lamp drive board 30, the motor lamp drive board 31, and the lamp drive board 37, and the staging interface board 22 receives the serial signal received from the staging control board 23 for each driver IC. Transferring to. Specifically, the serial signal is a lamp (motor) drive signal SDAT and a clock signal CK, and the drive signal SDAT is transmitted to each driver IC by a clock synchronization method, and a large number of LED lamps and illuminated lamps are used for lamp production. , The effect effect is executed by the effect motors M1 to Mn.

In the case of this embodiment, the lamp effect is executed by the lamp groups CH0 to CH2 of the three systems, and the lamp drive board 37 clocks the lamp drive signal SDAT0 of CH0 via the frame relay boards 35 and 36. Received in synchronization with signal CK0. The series of lamp drive signals SDAT0 transmitted as serial signals are simultaneously updated in the lighting state by being output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level.

The above points are the same for the lamp drive board 30, the driver IC of the lamp drive board 30 receives the lamp drive signal SDAT1 of the lamp group CH1 in synchronization with the clock signal CK1, and the operation control signal ENABLE1 is at the active level. At the timing when it changes to, the lighting state of the lamp group CH1 is updated all at once.

On the other hand, the driver IC mounted on the motor lamp drive board 31 receives the lamp drive signal transmitted in the clock synchronous manner to drive the lamp group CH2, and also receives the motor drive signal transmitted in the clock synchronous manner to drive the lamp group CH2. It drives the effect motor groups M1 to Mn composed of a plurality of stepping motors. The lamp drive signal and the motor drive signal are a series of serial signals SDAT2, which are serially transmitted in synchronization with the clock signal CK1. Then, the drive states of the lamp group CH2 and the motor groups M1 to Mn are updated.

Subsequently, the voice circuit SND will be described. As shown in FIG. 4A, the effect interface board 22 includes a voice processor (voice synthesis circuit) 27 that reproduces a voice signal based on an instruction received from the CPU circuit 51 (effect control CPU 63) of the effect control board 23. A voice memory 28 for storing compressed voice data, which is the original data of the voice signal to be reproduced, and a digital amplifier 29 for receiving the voice signal output from the voice processor 27 are mounted.

The voice processor 27 accesses the voice memory 28 based on the operation parameter (set value by the voice command) received from the effect control CPU 63 to the voice control register which is a built-in register, and reproduces and outputs a necessary voice signal. .. As shown in FIG. 4A, the voice processor 27 and the voice memory 28 are connected by a voice address bus having a length of 26 bits and a voice data bus having a length of 16 bits. Therefore, 1 Gbit (= ²²⁶ * 16) of data can be stored in the voice memory 28.

In the case of this embodiment, the compressed audio data stored in the audio memory 28 is phrase compressed data specified by the phrase number NUM (000H to 1FFFH) having a length of 13 bits, and is equivalent to one song of a series of background music. (BGM), a group of production sounds (notice sounds), and the like are stored in a maximum of 8192 types (= 213), each corresponding to the phrase number NUM. The phrase number NUM is specified by a set value (operation parameter) of a voice command transmitted from the effect control CPU 63 to the voice control register of the voice processor 27.

Further, as shown in FIG. 4A, the data bus and the address bus of the CPU circuit 51 of the effect control unit 23 are connected to the clock circuit (real time clock) 38 and the effect data memory 39 mounted on the liquid crystal interface board 24. It also extends. The clock circuit 38 is connected to the lower 4 bits of the address bus of the CPU circuit 51 and the lower 4 bits of the data bus, and is configured so that the CPU circuit 51 can be arbitrarily accessed. Further, the effect data memory 39 is a memory element SRAM (Static Random Access Memory) that can be accessed at high speed, and is connected to 16 bits of the address bus of the CPU circuit 51 and 16 bits of the lower 16 bits of the data bus, and is stored there. The game record information and the like are appropriately R / W accessed from the CPU circuit 51.

The clock circuit 38 and the effect data memory 39 are driven by a secondary battery (not shown), and the secondary battery is appropriately charged by the power supply voltage from the power supply board 20 during the game operation. Therefore, even after the power is cut off, the timekeeping operation of the clock circuit 38 is continued, and the game performance information stored in the effect data memory 39 is permanently stored and retained (non-volatileity is imparted).

As shown on the right side of FIG. 4A, the effect control board 23 includes a composite chip 50 incorporating a CPU circuit 51 and a VDP circuit 52, a control memory (PROM) 53 for storing a control program of the CPU circuit 51, and a control memory (PROM) 53. It is equipped with a DRAM (Dynamic Random Access Memory) 54 that can access a large amount of data at high speed, and a CGROM 55 that stores a large amount of CG data required for effect control.

FIG. 5A is a circuit block diagram showing the composite chip 50 constituting the staging control unit 23, including related circuit elements. As shown in the figure, the composite chip 50 of the embodiment includes a built-in CPU circuit 51 that issues a display list DL at predetermined time intervals, and display devices DS1 and DS2 that generate image data based on the issued display list DL. It has a built-in VDP circuit 52 to drive. The built-in CPU circuit 51 and the VDP circuit 52 are connected to each other through a CPU IF circuit 56 that relays transmission / reception data to each other.

Further, a control memory (PROGRAM_ROM) 53 for non-volatilely storing a control program and necessary control data and a work memory (RAM) 57 having a storage capacity of about 2 Mbytes are connected to the CPUIF circuit 56, respectively. It is configured to be accessible from the built-in CPU circuit 51.

The display list DL contains a series of instruction commands for specifying each frame of the display devices DS1 and DS2. In the case of this embodiment, in the series of instruction commands, a texture load command such as a TXLOAD command for reading the image material (texture) from the CGROM 55 and decoding it, and a VRAM area (index space) of the decoding destination are specified in advance. Texture setting commands such as the SET INDEX command, primitive drawing commands such as the SPRITE command for arranging decoded image material in a predetermined position in the virtual drawing space, and drawing commands in the virtual drawing space. Environment setting commands such as the SETDAVR command and SETDAVF command for specifying the drawing area actually drawn on the display device among the drawn images, and the index table control command (WRIDXTBL) related to the index table IDXTBL that manages the index space. Is included.

Note that FIG. 7C shows a virtual drawing space (X direction ± 8192: Y direction ± 8192), a drawing area that can be arbitrarily set in the virtual drawing space, and images to be output to the display devices DS1 and DS2. The relationship with the actual drawing area in the frame buffers FBa and FBb for primary storage of data is shown.

The built-in CPU circuit 51 is a circuit having the same performance as a general-purpose one-chip microcomputer, and has an effect control CPU 63 that comprehensively controls image effect based on the control program of the control memory 53, and a CPU when the program goes out of control. A watchdog timer (WDT) 58 that forcibly resets, a RAM 59 that has a storage capacity of about 16 kbytes and is used as a work area of the CPU, and a DMAC (Direct Memory Access Controller) that realizes data transfer without going through the CPU. 60, a serial input / output port (SIO) 61 having a plurality of input ports Si and an output port So, and a parallel input / output port (PIO) 62 having a plurality of input ports Pi and an output port Po. Has been done.

For convenience, the expression "input / output port" is used, but in the effect control unit 23, the input / output port includes an input port and an output port that operate independently. This point is the same for the input / output circuit 64p and the input / output circuit 64s described below.

The parallel input / output port 62 is connected to an external device (effect interface board 22) through the input / output circuit 64p, and the effect control CPU 63 has a chance with the encoder output 3 bits of the volume switch VLSW via the input circuit 64p. The switch signal of the button 11, the control command CMD, and the interrupt signal STB are received. The encoder output 3 bits and the switch signal 1 bit are supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p.

Similarly, the received control command CMD is supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p. Further, the strobe signal STB is supplied to the interrupt terminal of the staging control CPU 63 via the input / output circuit 64p to activate the reception interrupt processing. Therefore, the staging control CPU 63 that grasps the control command CMD based on the reception interrupt processing uniformly controls the voice staging, the lamp staging, the motor staging, and the image staging corresponding to the control command CMD through the staging lottery and the like. Will be done.

Although not particularly limited, in this embodiment, the SMC unit (Serial Management Controller) 78 of the VDP circuit 52 is used for the lamp effect and the motor effect. The SMC unit 78 is a composite controller having a built-in LED controller and Motor controller, and is configured to be able to output a serial signal by a clock synchronization method. Further, the Motor controller is configured to be able to output a latch pulse at an arbitrary timing based on a set value in a predetermined control register 70, and is configured to be able to input a serial signal by a clock synchronization method.

Therefore, in this embodiment, the motor drive signal and the LED drive signal are output from the SMC unit 78 in synchronization with the clock signal, while the latch pulse is output as the operation control signal ENABLE at an appropriate timing. .. Further, the origin sensor signals SN0 to SNn from the effect motor groups M1 to Mn are configured to be serially input by a clock synchronization method.

As described with respect to FIG. 4A, the clock signals CK0 to CK2, the drive signals SDAT0 to SDATA2, and the operation control signals ENABLE0 to ENABLE2 pass through the output buffers 41 to 43, and the predetermined drive boards 30, 31, It is transmitted to 37. Further, the origin sensor signals SN0 to SNn are serially input to the SMC unit 78 from the motor lamp drive board 31 via the input / output buffer 43.

However, it is not essential to use the SMC unit 78 in this embodiment. That is, since the CPU circuit 51 has a built-in general-purpose serial input / output port SIO61, it is also possible to execute a lamp effect and a motor effect by using these.

Specifically, it is as shown by the broken line in FIG. 5A, and in the configuration shown by the broken line, the clock signals CK0 to CK2, via the input / output circuit 64s internally connected to the serial input / output port SIO61. The drive signals SDATA0 to SDATA2 are output, and the operation control signals ENABLE0 to ENABLE2 are output via the input / output circuit 64p. For convenience, it is expressed as an input / output port or an input / output circuit, but what actually functions is an output port or an output circuit.

Here, the serial output port SO is configured to have a built-in 16-stage FIFO register. Then, the DMAC circuit 60 is activated by receiving an operation start instruction (see ST18 in FIG. 10B) from the staging control CPU 63, and the necessary drive data are ordered from the lamp / motor drive table (see FIG. 10B). It is configured to read into the FIFO and transfer it to the FIFO register of the serial output port SO by DMA. The drive data stored in the FIFO register is serially output from the serial output port SO by a clock synchronization method. Although the DMAC circuit has a plurality of (for example, 4) DMA channels, the DMAC circuit is configured to perform DMA transfer of lamp drive data on the first DMA channel and DMA transfer of motor drive data on the second DMA channel. ing.

Next, the WDT circuit 58 provided in the built-in CPU circuit 51 has a WDT counter that performs a down count operation based on the set values in a plurality of control registers (WDT control registers and the like) accessible from the effect control CPU 63. It is composed of. This WDT counter starts from a predetermined initial value and is down-counted toward zero in a predetermined operation cycle. When the down-count value reaches zero, an internal interrupt (WDT interrupt) is generated and the active level is increased. It is configured to output the underflow signal UF of.

As described above with respect to FIG. 4A, the underflow signal UF is transmitted to each unit via the OR circuit G1 and abnormally resets the composite chip 50 and the voice circuit SND in synchronization with each other. However, the effect control CPU 63 returns the counter value to the initial value by writing a predetermined 1-bit value to the initialization bit of the WDT control register every predetermined time (for example, 1/30 second), and the above-mentioned abnormal reset is performed. Avoiding the occurrence. When the counter value of the WDT counter returns to the initial value, the initialization bit also returns to the original value.

As described above, in the present embodiment, the staging control CPU 63 only needs to write access the initialization bit (1 bit) of the WDT control register, and like the CPUs of the main control unit 21 and the payout control unit 25, the reset circuits RST1 and RST2 Since it is not necessary to output a clear pulse to, the control load is reduced by this amount. Further, since a WDT interrupt is generated when an underflow abnormality occurs, the time when the abnormality reset occurs can be stored non-volatilely in the effect data memory 39 by invoking an appropriate WDT interrupt processing program. FIG. 4B shows a circuit configuration in such a case, and the effect control CPU 63 is put into a reset state by software reset processing after the execution of the WDT interrupt processing program.

The DMAC circuit 60 has a predetermined number of times for each predetermined data transfer unit in a predetermined DMA transfer mode from a transfer source (Source) to a transfer destination (Destination) based on a set value in a predetermined operation control register. , A circuit that repeats data transfer.

For example, in the embodiment in which the serial output port SO functions (see the broken line in FIG. 5A), the operation control register of the CPU circuit 51 is set to the start address of the lamp / motor drive table (the start value of the transfer source address). , The address of the input register of the serial output port SO (fixed value of the transfer destination address), the data transfer unit (8 bits), and the number of transfers are specified. Then, the DMAC circuit 60, which has received the operation start instruction in the predetermined operation control register, transfers the drive data to the predetermined transfer destination address by DMA while updating the transfer source address.

This point is almost the same in the case of the embodiment (FIGS. 13 and 17 (c)) in which the display list DL is issued by the DMAC circuit 60. That is, the effect control CPU 63 stores the start address of the transfer source (DL buffer), the address of the transfer destination (transfer port TR_PORT), the DMA transfer mode, and the data transfer unit in the predetermined operation control register of the CPU circuit 51. The number of transfers and other conditions will be set. These points will be further described later with reference to FIG.

Generally, the DMA transfer mode includes a cycle steal transfer mode, a burst transfer mode (pipeline transfer), and a demand transfer mode. In this embodiment, the cycle steal transfer mode is used to perform DMA transfer by 1. By passing the bus control right to the staging control CPU 63 each time the cycle is executed, the operation of the staging control CPU 63 is not hindered.

FIG. 6 is a drawing illustrating the cycle steal transfer operation and the pipeline transfer, and the DMAC circuit 60 operates with at least one cycle between the read access activation and the write access activation of one data transfer. In this vacant cycle, the bus of the effect control CPU 63 can be used. As is clear from the contrasting relationship in FIG. 6, in pipeline transfer, the bus is not opened to the CPU until one cycle (one operand transfer) is completed, whereas in cycle stealing transfer mode, every read access, Since the bus is open to the CPU, the operation of the CPU is not significantly delayed.

Then, for example, in the embodiment in which the DMAC circuit 60 is used when the display list DL is issued to the VDP circuit 52, the data transfer unit (1 operand) for one cycle is set to 32 × 2 bits, and the display list DL is stored. While increasing the source address of the built-in RAM 59 as appropriate (+8 for each operand transfer), the DMA transfer operation is performed for the transfer port register TR_PORT (see FIG. 8) of the data transfer circuit 72 specified by the fixed address. Is running.

As will be described later, in the embodiment, by adding the required number of NOP (no operation) commands to the display list DL, the entire data size is set to a fixed value (for example, 4 × 64 = 256 bytes or an integer thereof). It is adjusted to double), and the issuance of the display list DL is completed by repeating one operand transfer of 32 bits × 2 times 32 times (or an integral multiple thereof). Even if the drawing circuit 76 executes the NOP command, virtually no change occurs.

Next, the VDP circuit 52 will be described. The VDP circuit 52 includes a CGROM 55 that stores compressed data that is a component of still images and moving images that make up an image effect, and an external DRAM (Dynamic) that has a storage capacity of about 4 Gbit. The Random Access Memory) 54, the main display device DS1 and the sub display device DS2 are connected to each other. The DRAM 54 is preferably composed of DDR (Double-Data-Rate SDRAM).

Although not particularly limited, in this embodiment, the CGROM 55 is composed of a flash SSD (solid state drive) composed of a NAND flash memory having a storage capacity of about 62 Gbit, and is compressed data required for serial transmission. Is configured to get. Therefore, the problem of skew (difference in transmission speed for each bit data) that inevitably occurs in parallel transmission is solved, and extremely high-speed transmission operation becomes possible. Although not particularly limited, in this embodiment, the CGROM 55 is accessed at high speed by the HSS (High Speed Serial) method compliant with Serial ATA.

Regardless of whether or not the HSS method compliant with SerialATA is adopted, the NAND type flash memory is mechanically more stable than the hard disk and can be accessed at high speed, but is a sequential access memory. Compared to DRAM and SRAM (Static Random Access Memory), there is a problem with random accessibility. Therefore, in this embodiment, by executing a preload operation in which a group of compressed data (CG data) is read out to the DRAM 54 prior to the drawing operation, smooth random access of the CG data during the drawing operation is realized. ing. By the way, the access speed becomes slower in the order of built-in VRAM> external DRAM> CGROM.

In detail, the VDP circuit 52 includes a control register group 70 in which various operation parameters defining the operation of the VDP (Video Display Processor) can be set by the effect control CPU 63, and image data to be displayed on the display devices DS1 and DS2. Regarding the built-in VRAM (video RAM) 71 of about 48 Mbytes used at the time of generation, the data transfer circuit 72 that executes data transmission / reception between each part inside the chip and data transmission / reception with the outside of the chip, and the built-in VRAM 71, the Source and Destination An index table IDXTBL that can specify address information, a preloader 73 that executes preload operation, a graphics decoder (GDEC) 75 that decodes (decodes and decompresses) compressed data read from CGROM 55, and still image data and moving images after decoding. A drawing circuit 76 that generates image data for each frame of the display devices DS1 and DS2 by appropriately combining data, and a geometry engine 77 that generates a stereoscopic image by appropriate coordinate conversion as part of the operation of the drawing circuit 76. And 3 systems (A / B / C) display circuits 74A to 74C and 3 systems (A / B / C) that can read the image data of the frame buffers FBa and FBb generated by the drawing circuit and execute appropriate image processing in parallel. An output selection unit 79 that appropriately selects and outputs the output of the display circuit 74 of A / B / C), an LVDS unit 80 that converts image data output by the output selection unit 79 into an LVDS signal, and an SMC capable of transmitting and receiving serial data. Built-in CPUIF unit 81 that relays data transmission / reception between unit 78 and CPUIF circuit 56, CG bus IF unit 82 that relays data reception from CGROM55, and DRAMIF unit 83 that relays data transmission / reception between external DRAM 54. It is configured to include a VRAM IF unit 84 that relays data transmission / reception with the VRAM 71.

FIG. 5B illustrates the relationship between the CPU IF unit 81, the CG bus IF unit 82, the DRAM IF unit 83, and the VRAM IF unit 84, and the control register group 70, the CGROM 55, the DRAM 54, and the built-in VRAM 71. As shown in the figure, the CG data acquired from the CGROM 55 is transferred as preload data to the preload area of the external DRAM 54 via the data transfer circuit 72 and the DRAM IF unit 83, for example.

However, the above-mentioned preload operation is not an essential operation, and the data transfer destination is not limited to the external DRAM 54 and may be the built-in VRAM 71. Therefore, for example, in the embodiment in which the preload operation is not executed, the CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and the VRAM IF unit 84 (FIG. 5 (b)).

By the way, in this embodiment, the built-in VRAM 71 stores image data for specifying the expansion area of the compressed data read from the CGROM 55 and each ARGB information (32 bits = 8 × 4) of W × H display pixels of the display device. A frame buffer area to be used, a Z-buffer area for storing depth information of each display pixel, and the like are required. In the ARGB information, A means 8-bit α-plane data, and RGB means 8-bit data of the three primary colors.

Here, each of the above-mentioned areas of the built-in VRAM 71 is indirectly accessed by the staging control CPU 63 based on various instruction commands (such as the above-mentioned texture and SPRITE) described in the display list DL, and the READ / WRITE access thereof. In, it is complicated to specify the Destination address and the Source address of the built-in VRAM 71 one by one. Therefore, in this embodiment, in the initial processing after the CPU reset, a one-dimensional or two-dimensional logical memory space (hereinafter referred to as an index space) required for drawing operation is secured, and an index number is assigned to each index space. By doing so, access based on the index number is possible.

Specifically, after the CPU is reset, the built-in VRAM 71 is roughly divided into three types of memory areas, and a required number of index spaces are secured in each memory area. Then, by constructing the index table IDXTBL (see FIG. 7A) that stores the index space and the index number in association with each other, the operation based on the subsequent index number is realized.

It is also necessary to (1) add this index space after the initial processing, and conversely, (2) open it. Therefore, a flag capable of determining whether or not the addition / release processing is possible and whether or not the addition / release processing is actually completed during the operation of the addition / release effect control CPU 63 is possible. The area FG is provided in the index table IDXTBL. The built-in VRAM 71 is roughly classified into three types of memory areas, an AAC area (a), a page area (b), and an arbitrary area (c), which will be described below, and these three types of memory areas (a) and (b). Corresponding to (c), the index table IDXTBL is divided into three categories (FIG. 7 (a)).

Although not particularly limited, in the case of this embodiment, the built-in VRAM 71 has (a) an AAC area in which an index space and its index number are automatically assigned by internal processing and has a memory cache function, and (b) for example, 4096 bits × 128 lines. The two-dimensional space of is used as a unit space, and the page area can be divided into a page area where an index space can be secured within an integral multiple of the space, and (c) an arbitrary area where the start address STx and the horizontal size Hx can be set arbitrarily. (See FIG. 7 (b)). However, the head address STx of the index space arbitrarily set in the arbitrary area needs to have its lower 8 bits of 0 and be in units of predetermined bits (2048 bits = 256 bytes).

Then, after the CPU is reset, the AAC area (a) and the page area (b) are secured by defining the maximum value of the memory space required for each and the start address (lower 8 bits = 0), and the remaining memory. The area becomes an arbitrary area (c). Then, the required number of index spaces are secured in each area (a), (b), and (c). When the arbitrary area (c) is used, the horizontal size Hx of the index space that handles two-dimensional data can be arbitrarily set as a multiple of 32 bytes (256 bits), while its vertical size is a fixed value (for example,). , 2048 line).

In any case, since the index space and the index number are automatically assigned to the AAC area (a) by the VDP circuit 52, for example, the decoding destination is set to the AAC area (a) by the SETINDEX command of the texture setting command. If specified in, the TXLOAD (texture load) command for reading CG data from the CGROM55 only needs to specify the Source address of the CGROM55 and the horizontal / vertical size after expansion (decoding). Therefore, in this embodiment, the decoding destination of a still image (texture) such as a character that temporarily appears at the time of a preview effect or an I-stream moving image is set to the ACC area (a).

Since the memory cache function is added to this AAC area (a), for example, when the same texture of the CGROM 55 is read into the AAC area (a) multiple times, the AAC area is used from the second time onward. The decoded data cached in (a) can be utilized, and extra READ access and decoding processing can be suppressed. However, when the AAC area (a) is used up, old data is automatically destroyed. Therefore, in this embodiment, most of the built-in VRAM (48 Mbytes) is allocated to the page area (b), so that the AAC area (a) is used. ) The cache function does not work effectively.

By the way, texture is a concept that generally refers to the texture and texture of the surface of an object, but in the present specification, sprite image data constituting a still image, image data constituting one frame of a moving image, and the like are used. , It is used as a concept that includes not only image data to be pasted on drawing primitives such as triangles and squares, but also image data after decoding. When copying image data inside the built-in VRAM71 (hereinafter referred to as "move" for convenience), use the SETINDEX command of the texture setting command to set the image data of the move source as a texture and then use the SPRITE command. Will be executed.

By executing the SPRITE command, the source image data of the movement source is formally drawn in the virtual drawing space shown in FIG. 7 (c), but the drawing in the virtual drawing space actually drawn on the display device is performed. If the correspondence between the area and the index space that serves as the frame buffer is set in advance using environment setting commands (SETDAVR, SETDAVF) or texture setting commands (SETINDEX), for example, the SPRITE command can be used to create a virtual drawing space. By drawing, the source image data of the movement source is drawn in the predetermined index space (frame buffer) (see FIG. 7 (c)).

In any case, in this embodiment, the built-in VRAM 71 is roughly divided into an AAC area (a), a page area (b), and an arbitrary area (c), and an appropriate number of index spaces can be secured for each. , Each index space is specified by an independent index number for each region (a) (b) (c). The index number is, for example, 1 byte long, and the staging control CPU 63 freely assigns an index number in the range of 0 to 255 for the page area (b) and the arbitrary area (c) (excluding the AAC area). Will be done.

Therefore, in this embodiment, as shown in FIG. 7A, a pair of frame buffers FBa are secured in the arbitrary area (c) for the display device DS1, and the index numbers 255 and 25 are used in both of the double buffer structures. 254 is given. That is, as the frame buffer FBa for the main display device DS1, the index space 255 and the index space 254 used by switching in a toggle manner are secured. Although not particularly limited, the index spaces 255 and 254 have a horizontal size of 1280 corresponding to the number of horizontal pixels of the display device DS1. Since each pixel is specified by ARGB information 32 bits, the horizontal size 1280 means 32 × 1280 = 40960 bits.

Further, for the display device DS2, another pair of frame buffers FBb is secured in the arbitrary area (c), and index numbers 252 and 251 are assigned to both of the double buffer structures. That is, the index space 252 and the index space 251 are secured as the frame buffer FBb for the sub display device DS2. The index spaces 252 and 251 have a horizontal size of 480 corresponding to the number of horizontal pixels of the display device DS2.

The frame buffers FBa and FBb are secured in the arbitrary area (c) by setting the arbitrary area (c) to an arbitrary horizontal size as a multiple of 32 bytes (= 256 bits = 8 pixels). This is because if the number of horizontal pixels of the display devices DS1 and DS2 is matched, the reserved area will not be wasted. On the other hand, in the page area (b), only the horizontal / vertical size that is an integral multiple of the unit space of 128 pixels × 128 lines can be set.

However, the vertical size of the two-dimensional index space secured in the arbitrary region (c) is a fixed value (for example, 2048 lines). Therefore, in the frame buffer FBa, only the area of horizontal size 1280 × vertical size 1024 is the data effective area for the main display device DS1. This point is the same for the sub-display device DS2, and in the frame buffer FBb, only the area of the horizontal size 480 × the hanging size 800 is an effective data area for the sub-display device DS2 (FIG. 7 (c), FIG. 10 (d)).

The above points will be further described later, but in any case, in the frame buffers FBa and FBb, each double buffer (255/254, 252/251) is alternately used as a drawing area for the drawing circuit 76, and the frame buffers FBa and FBb are used alternately. The double buffers (255/254, 252/251) are alternately used as the display area for the display circuits 74A and 74B. In this embodiment, since the Z buffer that stores the depth information of the display pixels is not used, a missing number (253) occurs. However, when the Z buffer is used, the index number 253, 250 in the arbitrary area (c) is used. The index space 253,250 serves as a Z buffer for the display device DS1 and the display device DS2.

Further, in this embodiment, when an additional index space (memory area) is secured in the arbitrary area (c) in which the frame buffers FBa and FBb are secured, an index number starting from 0 is assigned. .. Although not limited in any way, in this embodiment, the effect image composed of characters and other still images is arbitrarily used as a work area for a preview effect to appear on a part of the screen in an appropriate rotation posture as needed. An index space (0) is secured in the area (c).

However, it is not essential to use the work area, and instead of the arbitrary area (c), an index space as a work area may be secured in the page area (b). If the page area (b) is used, an index space having an index space that is a multiple of a square unit space having a horizontal size of 128 (= 4096 bits) × a vertical size of 128 can be secured, which is suitable for handling a small staging image.

By the way, in this embodiment, the image is composed of a moving image including a background image, and the image effect is realized only by the moving image. In particular, a large number (usually 10 or more) of moving images are drawn at the same time during the variable effect. All of these videos are stored in the CGROM 55 in a compressed state as a series of video frames, but an I-stream video composed of only I-frames and an IP stream video composed of I-frames and P-frames. It is divided into. Here, the I frame (Intra coded frame) means a frame that compresses the input image as it is, independently of other screens. On the other hand, the P frame (Predictive coded frame) means a frame for performing forward predictive coding, and an I frame or a P frame located in the past in time is required.

Therefore, in this embodiment, the IP stream moving image is developed not in the AAC area (a) where there is a concern about the destruction of old data, but in the page area (b). That is, a large number of index spaces (IDX ₀ to IDX _N ) are secured in the page area (b) where an index space having a multiple dimension of horizontal size 128 × vertical size 128 can be secured, and a series of video frames are always the same. The index space IDXi of is used for decoding. Specifically, the TXLOAD command is executed after specifying that "the decoding destination of the IP stream video MVi is the index space (i) of the index number i in the page area (b)" by the SETINDEX command. ..

Then, one video frame (any of a series of video frames) on the CGROM 55 specified by the TXLOAD command is first acquired in the ACC area (a), and then automatically activated by the GDEC (graphics decoder) 75. , One frame of the acquired video is decoded and expanded in the index space (i) of the page area (b).

On the other hand, in this embodiment, the I-stream moving image is treated the same as the still image, and the TXLOAD command is specified by the SETINDEX command as "the decoding destination of the I-stream moving image MVj is the AAC area (a)". To execute. As a result, the moving image frame is acquired in the AAC area (a), and then the automatically activated GDEC75 expands the decoded data in the ACC area (a). As described above, the index space of the AAC area (a) is automatically generated, so it is not necessary to specify the index number. The expansion volume required for the index space, that is, the horizontal size and vertical size of the decoded texture (video frame), is TXLOAD regardless of whether the expansion destination is the AAC area (a) or the page area (b). Pre-specified by the command.

In any case, the IP stream moving image MVi and the I stream moving image MVj are generally composed of N moving image frames (I frame and P frame). Therefore, in the TXLOAD command, for example, the Source address of the CGROM 55 in which the kth (1 ≦ k ≦ N) moving image frame is stored, the horizontal / vertical size after expansion, and the like are specified. Although not limited in any way, in this embodiment, most of the memory space (about 30 Mbytes) of the built-in VRAM 71 is allocated to the page area (b).

In addition, in order to speed up the decoding process of the compressed moving image data, it is conceivable to provide a dedicated GDEC (graphics decoder) circuit. Then, if a dedicated GDEC circuit is built in the VDP circuit 52, it is sufficient to indicate the start address of the video compressed data to the GDEC circuit in the decoding process of the compressed video data composed of N compressed video frames. It is no longer necessary to specify the start address for each of the N compressed video frames.

However, if a plurality of such dedicated GDEC circuits are built in for each compression algorithm, the internal configuration of the VDP circuit 52 is further complicated. Therefore, in this embodiment, software GDEC is used, and decoding processing is realized for data such as IP stream moving image, I stream moving image, still image, and other α values by software processing corresponding to each compression algorithm. The processing time difference between the hardware processing and the software processing does not matter so much, and the processing time becomes a problem mainly in the access (READ) time from the CGROM 55.

Subsequently, returning to FIG. 5A and continuing the description, the data transfer circuit 72 uses a resource (storage medium) inside the VDP circuit and an external storage medium as a transfer source port or a transfer destination port between them. It is a circuit that executes a data transfer operation like DMA (Direct Memory Access). FIG. 8 is a block diagram showing the internal configuration of the data transfer circuit 72 together with the related circuit configurations.

As shown in FIG. 8, the data transfer circuit 72 is configured to transmit / receive data to / from the CGROM 55, the DRAM 54, and the built-in RAM 71 via the integrated connection bus ICM having a router function. The CGROM 55 and the DRAM 54 are accessed via the CG bus IF unit 82 and the DMAMIF unit 83.

On the other hand, the built-in CPU circuit 51 issues a display list DL to the drawing circuit 76 and the preloader 73 via the transfer port register TR_PORT built in the data transfer circuit 72. The built-in CPU circuit 51 and the data transfer circuit 72 are bidirectionally connected, but when the display list DL is issued, the transfer port register TR_PORT is a data write port that accepts one unit of data constituting the display list DL. Functions as. The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits corresponding to the FIFO structure of the CPU bus control unit 72d.

As shown in the figure, the effect control CPU 63 can write-access the transfer port register TR_PORT via the CPUIF unit 81, while when the DMAC circuit 60 is utilized, the DMAC circuit 60 directly accesses the transfer port register TR_PORT. Write access will be made. The series of instruction commands written in the transfer port register TR_PORT (that is, the instruction command sequence constituting the display list DL) is a CPU bus having a built-in FIFO buffer having a FIFO structure (32 bits x 130 stages) in units of 32 bits. It is configured to be automatically stored in the control unit 72d.

Further, the data transfer circuit 72 executes a data transmission / reception operation on a transmission path of 3 channels ChA to ChC, and has a FIFO structure (64 bit × N stage) in the ChA control circuit 72a (N = 130). Stage), a ChB control circuit 72b (N = 1026 stages), and a ChC control circuit 72c (N = 130 stages).

The instruction command sequence (display list DL) stored in the CPU bus control unit 72d is the drawing circuit 76 or the drawing circuit 76 based on the set value in the data transfer register RGij (a type of various control registers 70) by the effect control CPU 63. It is transferred to the preloader 73. As shown by the arrow, the display list DL is transferred from the CPU bus control unit 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b, and transferred to the preloader 73 via the FIFO buffer of the ChC control circuit 72c. It is configured to be.

In this embodiment, the ChB control circuit 72b and the ChC control circuit 72b are specialized in the transfer operation of the display list DL, and the data stored in the FIFO buffer of the CPU bus control unit 72d is the ChB control circuit. It is transferred to the drawing circuit 76 or the display list analyzer of the preloader 73 as a part of the display list DL, respectively, via the 72b or the FIFO buffer of the ChC control circuit 72c.

Then, the drawing circuit 76 starts a drawing operation based on the transferred display list DL. On the other hand, the preloader 73 executes a necessary preload operation based on the transferred display list DL. By the preload operation, the CG data of the CGROM 55 is read ahead to the preload area secured in the DRAM 54, and the display list DL (hereinafter referred to as the rewrite list DL') in which the source address of the texture is changed is secured in the DRAM 54 with respect to the TXLOAD command or the like. It is saved in the DL buffer area.

On the other hand, the ChA control circuit 72a and the connection bus access arbiter circuit 72e function for data transfer between storage media such as the CGROM 55, the DRAM 54, and the built-in RAM 71. Further, the IDXTBL access arbiter circuit 72f functions when the built-in RAM 71, which requires the address information of the index table IDXTBL, is accessed. Here, the connection bus access arbitration circuit 72e arbitrates data transmission with each storage element (CGROM55, DRAM54) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 72f arbitrates data communication with the built-in VRAM 71 by controlling the ChA control circuit 72a based on the index table IDXTBL.

In the case of the embodiment in which the preloader 73 functions, the rewrite list DL'stored in the DL buffer area of the DRAM 54 is transferred to the drawing circuit 76 via the connection bus access arbiter circuit 72e and the ChB control circuit 72b. It will be.

As described above, the data transfer circuit 72 of the present embodiment has a data transfer source arbitrarily selected from various storage resources (Resource) and a data transfer destination arbitrarily selected from various storage resources (Resource). High-speed data transfer is realized between them. As confirmed from FIG. 8, the storage resource in which the data transfer circuit 72 functions includes not only the built-in RAM 71 but also an external device via the CPU IF unit 56, the CG bus IF unit 82, and the DRAM IF unit 83.

Then, the amount of data transferred to an external device on which the ChA control circuit 72a functions, such as the amount of data to be acquired from the CGROM 55 at one time (memory sequential read), is the display on which the ChB control circuit 72b and the ChC control circuit 72c function. It is enormous as compared with the case of the list DL, and the amount of data transfer differs greatly from each other.

Here, for these various types of data transfer, it is conceivable to configure the unit data amount and total transfer data amount to be finely set, but this complicates the control operation inside the VDP and facilitates smooth transfer operation. Be hindered. Therefore, in this embodiment, the minimum data amount Dmin for data transfer is uniquely defined, and the total transfer data amount is limited to an integral multiple of the minimum data amount DTmin, so that high-speed and smooth data transfer operation can be performed. It has been realized. Although not particularly limited, in the data transfer circuit 72 of the embodiment, the minimum data amount Dmin (unit data amount) is 256 bytes, and the total transfer data amount is limited to an integral multiple of this.

Therefore, the instruction command sequence of the display list DL stored in the FIFO buffer of the CPU bus control unit 72d every 32 bits is stored in the ChB control circuit 72b or the ChC control circuit 72b at the timing when the total amount reaches the minimum data amount Dmin. It will be transferred and stored in each FIFO buffer.

The display list DL is composed of a series of instruction commands, but in this embodiment, the command length of the display list DL is an integer N times of 32 bits corresponding to the write unit (32 bits) of the transfer port register TR_PORT. It consists only of the instruction command (N> 0). Therefore, the drawing circuit 76 and the preloader 73 that receive the instruction command of the display list DL via the data transfer circuit 72 can start the command analysis process (DL analyze) quickly and smoothly. It should be noted that the command length of a 32-bit integer N times does not mean that all of them are significant bits, but also includes an involuntary bit (Don't care bit), which means a 32-bit integer N times.

Next, the preloader 73 will be described. As outlined above, the preloader 73 interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72b) and preliminarily inputs the CG data on the CGROM 55 referenced by the TXLOAD command to the DRAM 54. It is a circuit to transfer to the preload area of. Further, the preloader 73 stores the rewrite list DL'in which the reference destination of the CG data is rewritten to the address after transfer in the DL buffer of the DRAM 54 in relation to this TXLOAD command. The DL buffer and the preload area are reserved in advance at the time of initial processing after the CPU reset (ST3 in FIG. 10).

Then, the rewrite list DL'is a display list analyzer (DL Analyzer) of the drawing circuit 76 via the connection bus access arbiter circuit 72e of the data transfer circuit 72 and the ChB control circuit 72b at the start of the drawing operation of the drawing circuit 76. ).

In this embodiment, since the preload area is set in the external DRAM 54 having a sufficient storage capacity, for example, multiple preloads that preload CG data for a plurality of frames at once are possible. That is, regarding the operation period of the preloader 73, the operation period of a series of preload operations including the look-ahead operation of CG data is appropriately set within a range of an integral multiple of the operation cycle δ at the time of intermittent operation of the VDP circuit 52. Multiple preloads are realized with.

However, in the following description, for convenience, an embodiment without multiple preloads will be described. Therefore, the preloader 73 of the embodiments will complete the preload operation for one frame during one operation cycle (δ). As will be described later with reference to FIG. 10, in this embodiment, the operation cycle δ during the intermittent operation of the VDP circuit 52 is 1/30 second, which is twice the period of the vertical synchronization signal of the display device DS1.

Next, the drawing circuit 76 sequentially analyzes the instruction command sequence of the display list DL and the rewriting list DL'transferred via the data transfer circuit 72, and cooperates with the graphics decoder 75, the geometry engine 77, and the like. Then, it is a circuit that draws an image for one frame of each display device DS1 and DS2 in the frame buffer formed in the VRAM 71.

As described above, in the embodiment in which the preloader 73 is made to function, the reference destination of the CG data in the rewrite list DL'is not the CGROM 55 but the preload area set in the DRAM 54. Therefore, the sequential access to the CG data generated during the execution of drawing by the drawing circuit 76 can be quickly executed, and even a high-resolution moving image with intense movement can be drawn without any problem. That is, according to this embodiment, as the CGROM 55, it is possible to perform complicated and advanced image production while utilizing an inexpensive SATA module.

As described with respect to FIG. 7, the frame buffer FB secured in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a reading area, and the two areas are used by alternately switching the usage. .. Further, in the present embodiment, since the two display devices DS1 and DS2 are connected, the frame buffers FBa / FBb of two sections are secured as shown in FIG. 7. Therefore, the drawing circuit 76 draws image data for one frame in the drawing area (writing area) of the frame buffer FBa for the display device DS1 and draws the image data for one frame and draws the image data of the frame buffer FBa for the display device DS2 (writing area). In addition, one frame of image data will be drawn. When the image data is written in the drawing area, the display circuit 74 reads the image data in the other read area (display area) and outputs the image data to the display devices DS1 and DS2.

The display circuit 74 is a circuit that reads out the image data of the frame buffers FBa and FBb, performs final image processing, and outputs the data (see FIG. 9). The final image processing includes, for example, scaling processing for enlarging / reducing the image, delicate color correction processing, and dithering processing for minimizing the quantization error of the entire image. Then, after undergoing these image processing, a digital RGB signal (24 bits in total) is output together with a horizontal sync signal and a vertical sync signal. As shown in FIG. 9, in this embodiment, three display circuits A / B / C that execute the above operations in parallel are provided, and each display circuits 74A to 74C have a frame buffer corresponding to each. The image data of FBa / FBb / FBc is read out, and the above final image processing is executed. However, in this embodiment, since there are two display devices, the frame buffer FBc is not secured and the display circuit 74C does not function.

In connection with this operation, the output selection unit 79 of this embodiment transmits the output signal of the display circuit 74A to the LVDS unit 80a, and transmits the output signal of the display circuit 74B to the LVDS unit 80b (FIG. FIG. 9). Then, the LVDS unit 80a converts image data (a total of 24 bits of digital RGB signals) into an LVDS signal, adds a pair for transmitting a clock signal, and outputs a total of five pairs of differential signals to the main display device DS1. ing. The main display device DS1 has a built-in LVDS signal conversion receiving unit RV, which restores an RGB signal from the LVDS signal and displays an image corresponding to the output of the display circuit 74A.

This point is the same for the LVDS unit 80b, and for a total of 24 bits of each 8 bits of digital RGB signals, a pair for transmitting a clock signal is added and output to the conversion receiving unit RV as a total of 5 pairs of differential signals, and a sub. The display device DS2 realizes image display by a total of 24 bits of RGB signals received from the conversion receiving unit RV. Therefore, the sub display device DS2 and the main display device DS1 have a resolution of ²⁸ * ²⁸ * ²⁸ .

It is not always necessary to use an LVDS signal. For example, when the transmission distance is short, the digital RGB signal is transmitted to the display device as it is via the digital RGB unit 80c, or when the transmission distance is long. Converts a digital RGB signal into a V-By-one (registered trademark) signal in the conversion transmission unit TR'and transmits it to the conversion reception unit RV', and then returns it to the digital RGB signal in the conversion reception unit RV'. Is also suitable. Although the broken line in FIG. 9 shows this operation mode, the above operation can be performed with any output signal of the display circuits 74A to 74C by appropriately setting the operation of the output selection unit 79. It becomes.

Next, the SMC unit 78 (Serial Management Controller) is a composite controller having a built-in LED controller and Motor controller. Then, while outputting the LED drive signal and the motor drive signal in synchronization with the clock signal to the LED / Motor driver (driver IC with a built-in shift register) mounted on the external board, the latch pulse is output at an appropriate timing. It is configured to be outputable.

Regarding the internal circuit of the VDP circuit 52 and its operation described above, the operation content to be executed by the internal circuit is defined by the operation parameters (set values) set by the effect control CPU 63 in the control register group 70, and the execution of the VDP circuit 52. The state can be specified by READ the operation status value of the control register group 70. The control register group 70 means a large number of VDP registers mapped to a memory space (0 to FFFFFF) of about 1 Mbyte on the memory map of the effect control CPU 63, and the effect control CPU 63 operates via the CPU IF unit 81. The parameter WRITE (setting) operation and the operation status value READ operation are executed (see FIG. 5 (b)).

In the control register group 70, the "system control register" in which the initial setting values related to the system operation such as the interrupt operation are written, the AAC area (a) and the page area (b) are determined in the built-in VRAM, and the index table IDXTBL is stored. An "index table register" related to construction or modification, a "data transfer register" in which setting values related to data transfer processing by the data transfer circuit 72 between the effect control CPU 63 and the internal circuit of the VDP circuit 52 are written, and a graphic. A "GDEC register" that specifies the execution status of the decoder 75, a "drawing register" in which setting values related to instruction commands and the drawing circuit 76 are written, and a "preloader register" in which setting values related to the operation of the preloader 73 are written. The "display register" in which the setting values related to the operation of the display circuit 74 are written, the "LED control register" in which the setting values related to the LED controller (SMC unit 78) are written, and the settings related to the Motor controller (SMC unit 78). It includes a "motor control register" in which the value is written.

In the following description, one or more registers RGij included in the control register group 70 may be referred to by the above-mentioned individual names or collectively referred to as VDP register RGij, but in any case, the staging control CPU 63 may be referred to. The internal operation of the VDP circuit 52 is controlled by writing an appropriate set value to the predetermined VDP register RGij. Specifically, the effect control CPU 63 realizes a predetermined image effect based on the display list DL updated at an appropriate time interval and the set value in the predetermined VDP register RGij. In this embodiment, since the effect control CPU 63 is in charge of the effect control CPU 63 including the lamp effect and the motor effect, the VDP register RGij also includes the LED control register and the motor control register.

Subsequently, a unified effect control operation of image effect, sound effect, motor effect, and lamp effect realized by the composite chip 50 incorporating the built-in CPU circuit 51 and the VDP circuit 52 described above will be described. FIG. 10 is a flowchart illustrating the control operation of the staging control CPU 63 of the built-in CPU circuit 51.

The operation of the effect control CPU 63 is displayed as a main process (a) that is activated after the CPU is reset, a timer interrupt process (b) that is activated every 1 mS, and a reception interrupt process (not shown) that is activated by receiving the control command CMD. It is configured to include a VBLANK interrupt process (c) that is activated by receiving a VBLANK signal generated at the start timing of the V blank (vertical return period) of the apparatus DS1.

In the receive interrupt process, the control command CMD received from the main control unit 21 is stored in a predetermined receive buffer so that it can be referred to in the main process (ST13), and the process ends. In VBLANK interrupt processing, the interrupt counter VCNT is incremented for each VBLANK interrupt, and at the start timing of the main processing, the interrupt is interrupted after grasping the operation start timing of 1/30 second based on the value of the interrupt counter VCNT. The counter VCNT is cleared to zero (ST4).

On the other hand, as shown in FIG. 10B, the timer interrupt processing includes the progress processing (ST18) of the lamp effect and the motor effect, and the sensor signal acquisition process for acquiring the origin sensor signals SN0 to SNn signals, chance button signals, and the like. (ST19) and is included. The lamp effect and the motor effect are controlled based on the effect scenario that centrally manages all the effect operations, and when the effect counter EN manages the effect start time, the effect scenario update process (ST11) includes the motor drive table and The lamp drive table is designed to be specified.

After that, the motor effect proceeds based on the specified motor drive table, and the lamp effect proceeds based on the specified motor drive table. As described above, there is also an embodiment in which the DMAC circuit (first and second DMA channels) 60 functions during the operation of step ST18. The motor effect progresses every 1 mS, but the lamp effect progresses at an appropriate timing longer than 1 mS.

Subsequently, the main process (a) will be described with respect to an embodiment in which the preloader does not function. As shown in FIG. 10A, the main process is divided into an initial process (ST1 to ST3) executed after the CPU reset and a regular process (ST4 to ST14) repeatedly executed every 1/30 second thereafter. Will be done.

Since the steady processing is started at the timing when the interrupt counter VCNT becomes VCNT ≧ 2 (ST4), the operation cycle δ of the steady processing is 1/30 second. This operation cycle δ is nothing but a substantial operation cycle δ of the VDP circuit 52 that operates intermittently based on the control of the staging control CPU 63. The determination condition is VCNT ≧ 2, considering the possibility that the steady processing (ST4 to ST14) is abnormally prolonged and the timing of VCNT = 2 is overlooked, but the situation is that VCNT = 3. Is designed not to occur.

Continuing the description of the main process (FIG. 10 (a)) based on the above, in the present embodiment, in the initial process, the built-in VRAM 71 having a storage capacity of 48 Mbytes is combined with the ACC region (a) having an appropriate storage capacity. It is appropriately divided into a page area (b) and an arbitrary area (c) (ST1). Specifically, for the ACC area (a) and the page area (b), the start address and the required total data size of each are set in the predetermined index table register RGij (ST1). As a result, the ACC area (a) secured in this way and the residual area not included in the page area (b) become an arbitrary area (c).

In addition, the necessary index space IDXi is secured for the page area (b) and the arbitrary area (c) (ST2). Specifically, the index space IDXi of each area (b) (c) is secured by setting necessary address information in the predetermined index table register RGij.

For example, when the index space IDXi is provided in the page area (b), the address information of an arbitrary horizontal size Hx and an arbitrary vertical size Wx corresponding to an arbitrary index number i is a predetermined index table register RGij. Is set to (ST2).

As described above, the index space IDXi in the page area (b) has a horizontal size of 128 × a vertical size of 128 lines as a unit space, and one pixel is specified by 32 bits of information, so that it is perpendicular to the horizontal size Hx. Based on the setting of the size Wx, the index space IDXi of the data size (bit length) = 32 × 128 × Hx × 128 × Wx is secured. The start address of the index space IDXi in the page area (b) is automatically assigned internally.

Further, when the index space IDXi is provided in the arbitrary area (c), the address information of the arbitrary start address STx and the arbitrary horizontal size Hx corresponding to the arbitrary index number i is the predetermined index table register RGIj. Is set to (ST2). Here, "arbitrary" is premised on a predetermined condition, and the horizontal size Hx is arbitrarily determined in units of 256 bits, the lower 8 bits of the head address STx is 0, and is arbitrarily determined in units of 2048 bits. As explained above, the vertical size of the arbitrary area is fixed to the 2048 line, so based on the setting of the horizontal size Hx, after the start address STx, the data size (bit length) = 2048 x Hx index. Space has been secured.

As described above, the required number of index space IDXi is generated by setting the necessary address information for the page area (b) and the arbitrary area (c) in the predetermined index table register RGIj (ST2). .. Then, in response to this setting process (ST2), the index table IDXTBL that specifies the address information of each index space IDXi is automatically constructed. As shown in FIG. 7A, the start address of each index space IDXi is stored in the index table IDXTBL together with other necessary information, and is stored at the time of data transfer inside the VDP circuit 52 or as an external storage resource (Resource). ) Is referred to when the data is acquired (see FIG. 8). Since the index space IDXi in the AAC area (a) is automatically generated and automatically disappears when necessary, the setting process of step ST2 is unnecessary.

As shown in FIGS. 7A and 7B, each pair of frame buffers FBa and FBb are secured in the arbitrary area (c), and each is assigned an index number. In the embodiment in which the Z buffer is not used, a pair of index spaces 255 and 254 to which the index numbers 255 and 254 are assigned are secured as the frame buffer FBa. Further, as the frame buffer FBb, a pair of index spaces 252 and 251 to which the index numbers 252 and 251 are assigned are secured. In this embodiment, a work area (index space 0) having an index number of 0 is also secured in the arbitrary area (c).

Further, in this embodiment, the required number of index space IDXi, which is the decoding area of the IP stream moving image, is secured in the page area (a), and the index number i is assigned. However, initially, only the index space IDX ₀ for the background moving image (IP stream moving image) is secured. Then, the index space IDXj in the page area (a) is increased based on the setting process in the index table register RGij and the instruction command of the display list DL according to the necessity in the image effect (variation effect or advance notice effect). After that, when it becomes unnecessary, the index space IDXj is released. That is, FIG. 7A shows the index table IDXTBL during steady operation.

The index space of the ACC area (a) is automatically generated when necessary based on the instruction command described in the display list DL, and the index table IDXTBL contains the start address of the automatically generated index space IDXj. And other necessary information is set automatically. In this embodiment, this AAC region (a) is used as a decoding region for still images and other textures.

The above operation of securing the index space is realized exclusively by the setting operation to the index table register RGij included in the control register group 70, but following the processing of steps ST1 to ST2, the other VDP registers RGij By executing the necessary setting operation, the steady operation (intermittent operation) of the VDP circuit 52 shown in FIGS. 18 to 19 is enabled.

For example, the number of display lines and the number of horizontal pixels are set for each display device DS1 and SD2 by writing a predetermined operation parameter (number of lines and number of pixels) to a predetermined display register RGij that defines the operation of the display circuit 74. (ST30). As a result, in each frame buffer FBa and FBb, the vertical and horizontal dimensions of the effective data area (broken line portion in FIG. 10D) to be READ-accessed by the display circuit 74 are specified.

Next, a predetermined operation parameter (address value) is written in the predetermined display register RGij to specify the vertical display start position and the horizontal display start position for each frame buffer FBa and FBb (ST31). As a result, the effective data area whose vertical and horizontal dimensions are specified in the process of step ST30 is determined on the frame buffers FBa and FBb. Here, the vertical display start position and the horizontal display start position are relative address values in each index space, and in the embodiment shown in FIG. 10D, the display start position is (0,0).

Subsequently, the display register RGij (DSPAINDEX) relating to the display circuit 74A driving the main display device DS1 and the display register RGij (DSPBINDEX) relating to the display circuit 74B driving the sub display device DS2 are respectively "display area (0)". And "display area (1)" are set to define each display area (ST32).

Here, the "display area" means an index space (frame buffers FBa, FBb) in which image data should be read in order for the display circuits 74A and 74B to drive the display devices DS1 and DS2, and each has a double buffer structure. It means either one of the double buffers in the frame buffers FBa and FBb. However, the display circuits 74A and 74B actually read out the image data only in the "effective data area" specified in steps ST30 to ST31 in the display area (0) or the display area (1).

Although not limited in any way, in this embodiment, for the frame buffer FBa, the index space 254 of the index number 254 in the VRAM arbitrary area (c) is defined as the “display area (0)”, and the index number in the VRAM arbitrary area (c) is defined. The index space 255 of 255 is defined as a "display area (1)" (ST32).

Further, regarding the frame buffer FBb, the index space 251 of the index number 251 in the VRAM arbitrary area (c) is set as the “display area (0)), and the index space 252 of the index number 252 in the VRAM arbitrary area (c) is set as the “display area (display area (0)). 1) ”(ST32). The definition of the "display area" in the initial processing (ST3) is not particularly limited, and the index space (display area) in which the display circuit 74 should READ access the image data is toggled for each operation cycle δ. It may be switched.

In this embodiment, once the above initial processing (ST30 to ST32) is completed, the setting value to the predetermined system control register RGIj is not changed due to the influence of noise or the like. A predetermined prohibition value is set in the register RGij (first prohibition setting ST33).

Here, the setting values for which future writing is prohibited include (1) setting values related to the display clocks of the display devices DS1 and DS2, (2) setting values related to the sampling clock of the LVDS, and (3) selection of the output selection circuit 79. It includes setting values related to operation, (4) synchronization relations of a plurality of display circuits DS1 and DS2 (the display circuit 74B is dependent on the operation cycle of the display circuit 74A), and the like. Although there is a software process for canceling the first prohibition setting, it is not used in this embodiment. However, it is also preferable to use it as needed.

Next, by setting a predetermined prohibition value in the second type prohibition setting register RGij, the write prohibition setting is set for the VDP register RGij of the initial setting system (second prohibition setting ST34). Here, the prohibited setting includes the VDP register RGij according to steps ST30 to ST32.

On the other hand, by setting a predetermined prohibition value in the third type prohibition setting register RGij, it is possible to set prohibition to a large number of VDP registers including the VDP register related to the setting process of steps ST1 to ST3 (the first). Prohibition setting of 3). However, it is not used in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be arbitrarily canceled by writing the release value in the predetermined release register RGij, and the set value is changed during steady operation. Is also possible.

Since the initial setting process has been described above, next, before the steady process (ST4 to ST14) is described, the steady operation (intermittent operation) of the VDP circuit 52 controlled by the staging control CPU 63 is shown in FIGS. 18A and 18A. A brief description will be given based on FIG. 19 (b).

The intermittent operation of the VDP circuit 52 is as shown in FIGS. 18 and 19, and in the embodiment in which the preloader 73 is not used, as shown in FIG. 18A, the display list DLi completed by the effect control CPU 63 is It is issued to the drawing circuit 76 in the operation cycle (T1), and the drawing circuit 76 completes the image data in the frame buffers FBa and FBb by the drawing operation based on the display list DLi. Then, the image data completed in the frame buffers FBa and FBb is output to the display devices DS1 and DS2 by the display circuit 74 in the next operation cycle T1 + δ, and based on the subsequent drawing operation of the display devices DS1 and DS2. , The display screen is detected by the player.

On the other hand, in the embodiment using the preloader 73, as shown in FIG. 19A, the display list DLi completed by the staging control CPU 63 is issued to the preloader 73 in the operation cycle (T1), and the preloader 73 is , Interpret the display list DLi, perform the necessary look-ahead operation, and rewrite a part of the display list DLi to complete the rewrite list DL'. The pre-read CG data and the rewrite list DL'are stored in appropriate places in the DRAM 54.

Next, the drawing circuit 76 acquires the rewrite list DL'from the DRAM 54 in the next operation cycle (T1 + δ), and completes the image data in the frame buffers FBa and FBb by the drawing operation based on the rewrite list DL'. .. Then, the image data completed in the frame buffers FBa and FBb is further output to the display devices DS1 and DS2 by the display circuit 74 in the next operation cycle (T1 + 2δ), so that the subsequent display devices DS1 and DS2 are drawn. The display screen is detected by the player based on the movement.

Although the intermittent operation of the VDP circuit 52 has been schematically described above, in order to realize the above-mentioned operations of FIGS. 18 to 19, the staging control CPU 63 has the value of the interrupt counter VCNT after the initial processing (ST1 to ST3). Is repeatedly referred to, the operation start timing is waited to be reached, and when the operation start timing (one-step V blank start timing) is reached, the interrupt counter VCNT is cleared to zero (ST4).

After that, steady operation is started, but in this embodiment, it is first determined whether or not the operation start condition for starting steady operation is satisfied (ST5). The determination timing is the timing of T1, T1 + δ, T1 + 2δ, ..., That is, the start timing of the vertical blanking interval (VBLANK) of the display device DS1 shown in FIGS. 18 to 19. The display timing of the display device DS2 is set at the time of initial setting (ST3) so as to depend on the display timing of the display device DS1.

Since the operation start condition determined at the start timing of the vertical blanking interval (VBLANK) differs depending on whether or not the preloader 73 is used, an embodiment (FIG. 10) in which the preloader 73 is not used will be described first. In this case, the circuit configuration and the program are originally designed so that the internal operation of the VDP proceeds as shown in the time chart of FIG. 18A. That is, based on the display list DL1 completed in the operation cycle (T1), the drawing circuit 76 should finish the drawing operation during the operation cycle (T1 to T1 + δ). However, for example, as in the display list DL3 completed in the operation cycle (T1 + 2δ) of FIG. 18A, it cannot be said that the drawing operation may not be completed during the operation cycle (T1 + 2δ to T1 + 3δ).

The determination process in step ST5 takes such a situation into consideration, and the staging control CPU 63 accesses the status register RGij (a type of control register group 70) indicating the operating state of the drawing circuit 76, and at the timing of step ST5, The drawing circuit 76 determines whether or not the required operation has been completed. In the embodiment in which the preloader 73 is not utilized, for example, at the timing T1 + δ in FIG. 18A, the status information of the drawing circuit 76 is read-accessed to confirm that the drawing operation based on the display list DL1 is completed.

Then, when the operation start condition is not satisfied (nonconformity), the abnormality flag ER for counting the number of abnormalities is incremented, and the steps ST6 to ST8 processing are skipped. The abnormality flag ER is determined in the processing of steps ST9 and ST10 together with the other serious abnormality flag ABN, and if the number of continuous abnormalities is not large (ER ≦ 2) on the assumption that the serious abnormality flag ABN is in the reset state, the abnormality flag ER is determined. The effect command analysis process is executed in the same manner as in the normal state (ST13).

In the effect command analysis process (ST13), it is determined whether or not the control command CMD is received from the main control board 21, and if the control command CMD is received, the control command CMD is analyzed and necessary processing is executed. (ST13). Here, the necessary processing includes a process for preparing to start a new variation effect based on the control command CMD instructing the start of the variation effect, and a process for starting error notification based on the control command CMD indicating the occurrence of an error.

Subsequently, in order to return the WDT timer to the initial value, after writing the specified 1 bit to the initial bit of the WDT control register (ST14), the process returns to the process of step ST4. The effect control CPU 63 does not need to output a clear pulse to the external device, and has an advantage that it is sufficient to simply execute a write instruction to the built-in register as described above.

The case where the operation start condition is non-conforming and the abnormality flag ER is ER ≦ 2 has been described above. In such a case, the display area read by the display circuit 74 is toggled in the operation cycle. The process (ST6) and the display list creation process (ST7) are skipped, and the staging scenario does not proceed (see ST8 to ST12). This is because the image data of the frame buffers FBa and FBb in an incomplete state is not output. Therefore, for example, in the operation cycle (T1 + 3δ) of FIG. 18A, the image effect does not proceed, and the original screen (screen based on DL2) is redisplayed with a frame drop.

Here, in order to avoid dropping frames, a configuration that waits until the operation start condition is satisfied is also conceivable. However, since there are many control processes (ST6 to ST12) to be executed by the staging control CPU 63 and it is necessary to secure each processing time, in this embodiment, a frame drop occurs when the operation start condition is not satisfied. There is.

However, even if a frame is dropped, the progress of the image effect is only delayed by about 1/30 to 2/30 seconds as compared with the lamp effect and the motor effect that are progressed by the interrupt process (FIG. 10 (b)). Yes, this is not noticed by the player. Moreover, when the frame is dropped, the effect scenario processing (ST11) including the update process of the effect counter EN and the voice progress process (ST12) are also skipped, so that the reach effect, the advance notice effect, and the character that are started after that are also skipped. In the production, there is no possibility that the start timings of the image production, the voice production, the lamp production, the motor production, and the like are shifted.

That is, in the staging scenario, the start timing of the image staging, the sound staging, the lamp staging, and the motor staging and the staging content to be executed after that are centrally managed, and the staging counter EN, which is updated only when normal, starts. Since the timing is controlled, the synchronization of various productions will not be out of sync. For example, if there is an effect operation that combines an explosion sound, an explosion image, an accessory movement, and a lamp flash operation, each of the above effect operations is started correctly in synchronization even after a frame drop occurs. To.

The above is a description of a relatively minor abnormality, but when the serious abnormality flag ABN is in the set state or when the number of continuous abnormalities is large (ER> 2), an infinite loop state is set after the determination in step ST10. There is. As a result, the down count operation of the WDT timer progresses, the composite chip 50 including the staging control CPU 63 is abnormally reset, and then the initial processing (ST1 to ST3) is re-executed, so that an abnormal situation occurs. It is expected that the root cause will be eliminated.

As described with respect to FIG. 4, at the time of this abnormality, the audio circuit SND is also abnormally reset, so that the image effect, the sound effect, the lamp effect, and the motor effect all return to the initial state. However, since these reset operations have no effect on the main control unit 21 and the payout control unit 25, there is no possibility that a situation such as the disappearance of the jackpot state or the disappearance of the prize ball will occur.

Although the abnormal situation has been described above, in reality, the above-mentioned abnormality rarely occurs even in a minor case, and after the processing of step ST5, the setting to the predetermined display register RGIj (DSPACTL / DSPBCTL) is performed. Based on this, the "display area" of the frame buffers FBa and FBb for storing the image data to be read by the display circuit 74A and the display circuit 74B is toggled (ST6). As described above, since the "display area (0)" and the "display area (1)" are defined in advance in the initial processing (ST3), in the processing of step ST6, the frame buffers FBa and FBb are used this time. It is specified whether the "display area" of the above is the display area (0) or the display area (1).

By executing this step ST6, the display circuit 74A alternately outputs image data from the index space 254 (display area (0)) and the index space 255 (display area (1)) for each operation cycle δ. It will be read out and the display device DS1 will be driven. Similarly, the display circuit 74B alternately reads image data from the index space 251 (display area (0)) and the index space 252 (display area (1)) at each operation cycle δ to display the sub-display device DS2. It will be driven. As described above, the display circuit 74 actually performs READ access only to the effective data area in the display area (0) / display area (1).

In any case, in this embodiment, since the "display area" is switched for each operation cycle, the display circuits 74A and 74B use the display devices DS1 and DS2 for the image data completed by the drawing circuit 76 in the immediately preceding operation cycle. The output process to is started. However, since the processing in step ST5 is started from the start of the vertical blanking interval (V blank) of the main display device DS1, the image data output processing is actually started after the vertical blanking interval is completed. Will be done. In FIG. 18A, the arrow shown in the column of the display circuit indicates the operation cycle of this output processing.

When the processing of step ST6 having the above significance is completed, the staging control CPU 63 subsequently completes the display list DL that specifies the image data to be output to the display device by the display circuit 74 in the next operation cycle. (ST7). Although not particularly limited, in this embodiment, the list buffer area (DL buffer) of the RAM 59 is secured, and the display list DL is completed there (see FIG. 8).

The display list DL is configured by listing a series of instruction commands in an appropriate order, and is configured to end with an EODL (End Of DL) command. Then, in this embodiment, in order to realize smooth operation of the data transfer circuit 72, the drawing circuit 76, and the preloader 73, all the instruction commands including the EODL command are executed by an integer N times (N> 0) having a command length of 32 bits. It is limited to the instruction command of. As described above, the instruction command composed of a 32-bit integer N times may include a don't care bit.

As described above, since the display list DL of the embodiment is composed of only instruction commands having a command length of 32 bits and an integer N times (N> 0), the data volume value (total amount of data) of the entire display list DL is determined. It is always an integral multiple of the minimum unit of command length (32 bits = 4 bytes). Further, in this embodiment, the data volume value of the display list DL is set to an integral multiple (1 or more) of the minimum data amount Dmin in consideration of the minimum data amount Dmin of the data transfer circuit 72, and the instruction command is used. It is adjusted to be an integral multiple of the minimum unit (4 bytes). For example, if Dmin = 256 bytes, the data volume value of the display list DL is adjusted to any value of 256 bytes, 512 bytes, and so on.

Here, it is also preferable to appropriately adjust to 256 bytes or 512 bytes according to the complexity of the effect content, but in this embodiment, there are two display devices, and the sub display device DS2 is The data volume value of the display list DL is always adjusted to 256 bytes in consideration of not performing such a complicated image effect.

However, this method is not limited in any way, and is adjusted to 512 bytes or 768 bytes in the case of three or more display devices or in the case of a gaming machine that executes complicated image production including the sub display device DS2. Will be done. Further, during a normal effect, the data volume value of the display list DL is adjusted to 256 bytes, and the data volume value of the display list DL is adjusted to 512 bytes or 768 bytes only when a special effect is executed. Is also suitable.

However, in the case of this embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) specified in advance in each operation cycle δ. The adjustment method is a simple method (A) that fills the 32-bit length NOP (No Operation) command after the 32-bit length EODL command, or after filling the shortage area with the 32-bit length NOP command. Finally, a standard method (B) in which a 32-bit length EODL command is described can be considered. It should be noted that the data volume value (total data amount) of the display list DL is terminated by the EODL command without any adjustment, and dummy data is additionally transferred during the operation of the data transfer circuit 72, which is an integral multiple of the minimum data amount Dmin. An unadjusted method (C) for securing the transfer amount of the data can be considered.

Here, when the standard method (B) is adopted, first, the command counter CNT is initially set to a specified value (64-1 corresponding to 256 bytes), and each time a significant instruction command is written in the DL buffer area. , The command counter CNT is appropriately subtracted, and when the writing of a series of significant instruction commands is completed, the NOP command is described until the command counter CNT becomes zero, and finally the EODL command is described. In the case of this embodiment, since the command length is limited to an integer N times (N> 0) of 32 bits, the above processing is easy, and the subtraction processing of the command counter CNT is an integer. It is a subtraction process corresponding to N.

On the other hand, when the simple method (A) is adopted, it is sufficient to first fill the entire list buffer area (DL buffer) with the NOP command when creating the display list DL, so it is seemingly superior to the standard method (B). Seems to be. Further, from the viewpoint of simplicity, the non-adjustment method (C) seems to be excellent. However, in this embodiment, the standard method (B) is basically adopted, and the actual data amount from the beginning of the display list DL to the EODL command, that is, the data amount up to the EODL command is always the data transfer circuit 72. The minimum data amount of Dmin is adjusted to be an integral multiple of Dmin.

This is in consideration of an embodiment using the preloader 73, and if the simple method (A) or the non-adjustment method (C) is adopted, the actual data amount of the display list DL up to the EODL command is random. This is because the value becomes a value, and problems occur when transferring the rewrite list DL'rewritten by the preloader 73 to the DRAM 54 or when transferring the rewrite list DL'from the DRAM 54 to the drawing circuit 76. The ChA control circuit 72a of the data transfer circuit 72 functions when the rewrite list DL'is transferred to the DRAM 54, and the ChB control circuit 72b functions when the rewrite list DL'is transferred to the drawing circuit 76 (FIG. 16). Refer to), in either case, only the rewrite list DL'up to the EODL command is transferred.

The advantages of the standard method (B) for adjusting the data volume value of the display list DL have been described above, but in the embodiment in which the preloader 73 is not used, the issued display list DL is only processed by the drawing circuit 76. Therefore, the use of the simple method (A) and the non-adjustment method (C) is not prohibited at all.

However, in the following description, the details of the display list DL will be described with reference to FIG. 11 on the premise that the standard method (B) is adopted in principle regardless of whether or not the preloader 73 is used.

Although not particularly limited, in the present embodiment, the instruction command sequence (L11 to L16) relating to the main display device DS1 is first described in the display list DL, and then the instruction command sequence (L17 to L20) relating to the sub display device DS2 is described. I am trying to describe it. Further, the standard method (B) is adopted to adjust the data volume value of the display list DL to a fixed length (256 bytes). Note that FIG. 11 also shows, in effect, the procedure in which the staging control CPU 63 writes an instruction command to the list buffer area of the RAM 59, and the operation of the drawing circuit 76 based on the display list DL.

As shown in FIG. 11, at the beginning of the display list DL, an instruction command (SETDAVR) of the environment setting system is described, and the upper left base point address (X, Y) on the index space IDX is set for the frame buffer FBa of the display device DS1. Specify (L11). As described with respect to FIG. 7A, in this embodiment, a pair of frame buffers FBa are secured in the arbitrary area (c) for the display device DS1. Then, normally, by setting the base point address (X, Y) = (0,0) corresponding to the effective data area for the display circuit 74, the drawing circuit 76 is utilized from the head position of the frame buffer FBa. ..

In FIG. 7 (c), L11 is attached to the actual drawing area on the lower left side thereof, which means that the actual drawing area on the frame buffer FBa is set to the base point address (0,) of the frame buffer FBa by the instruction command L11. 0) It means that it was specified to start from the position. However, the vertical and horizontal dimensions of the actual drawing area and the index number that specifically specifies the actual drawing area are still undecided, and are determined by the instruction command (SETINDEX) L13 described later. The instruction command L11 also specifies whether or not to use the Z buffer.

Next, the upper left base point coordinates (Xs, Ys) and the lower right diagonal point coordinates (Xe, Ye) are set on the virtual drawing space by the instruction command (SETDAVF) of the environment setting system, and the W × H dimension is set. The drawing area of is defined (L12). Here, the virtual drawing space is a virtual two-dimensional space in the X direction ± 8192 and the Y direction ± 8192 that can be drawn by an instruction command for drawing (SPRITE command or the like) (see FIG. 7 (c)). ..

By this instruction command L12 (SETDAVF), the virtual drawing space is divided into a drawing area in which the drawing contents are actually reflected on the display device DS1 and other non-drawing areas. Further, the instruction command L12 (SETDAVF) associates the actual drawing area whose start position (base point address) is defined by the instruction command L11 with the drawing area on the virtual drawing space.

In other words, the instruction command L12 defines a W × H actual drawing area starting from the base point address, which corresponds to the drawing area on the virtual drawing space, in the frame buffer FBa (index space is undecided). It will be. Therefore, the drawing area specified by the instruction command L12 needs to be the same as or smaller than the horizontal size of the frame buffer FBa. Normally, the drawing area and the actual drawing area are defined so as to have the same dimensions as the effective data area (FIG. 10D) for the display circuit 74.

Then, after the drawing circuit 76 executes the instruction commands L11 and L12, only the drawing contents drawn in the virtual drawing space, which are included in the drawing area, are reflected in the actual drawing area of the frame buffer FBa. become. Therefore, the drawing contents of the portion protruding from the drawing area and the portion described as the work area in FIG. 7C are not reflected in the frame buffer as they are. When securing a work area in the virtual drawing space, the non-drawing area of the virtual drawing space is used.

Next, in this operation cycle, the drawing circuit 76 defines where to draw the drawing content to be drawn based on the display list DL to be completed (L13). Specifically, for the frame buffer FBa of the display device DS1 having a double buffer configuration, the index space IDX which is the "write area" of the drawing contents based on the display list DL this time is specified (L13). Specifically, by the SETINDEX command, which is a texture setting command, (1) the frame buffer FBa is secured in an arbitrary area, and (2) the index space IDX _N that becomes the "write area" is arbitrary. The index number N on the area is specified.

When, for example, N = 255 is specified by this instruction command L13, the actual drawing area corresponding to the drawing area defined on the virtual drawing space is specifically in the frame buffer FBa having a double buffer structure. It is defined as the index space IDX ₂₅₅ .

In the case of this embodiment, the index number of the frame buffer FBa is 255 or 254 (FIG. 7 (a)), and either toggled switch is specified (L13). Note that this index number is an index number that is not the display area (0) / (1) specified in step ST6 of the main process. For example, in the process of step ST6, when the display area (0) is designated for the display circuit 74, the display area (1) becomes the “write area” for the drawing circuit 76.

As described above, after the correspondence between the actual drawing area (W × H logical space) and the drawing area (W × H virtual space) is generally defined by the instruction command L11 and the instruction command L12, By the instruction command L13 (SETINDEX) that specifically specifies the index space IDX, the virtual space of W × H is associated with the logical space of W × H in the specific index space IDX.

In other words, in the future, the content virtually drawn in the W × H virtual space based on a series of instruction commands will be inside the VDP that defines the correspondence between the virtual space and the real address of the built-in VRAM 71. Based on the conversion table, it becomes the image data of the built-in VRAM 71 (frame buffer).

Subsequently, as a "write area", an instruction command for executing a frame buffer clear process for filling the specified index space IDX with black, for example, is described (ST14, ST15). This is nothing but the erasing process of the image data written in the frame buffer FBa before the two operation periods.

Specifically, the SETFCOLOR command, which is a type of environment setting command, selects black, for example, and the RECTANGLE command, which is a primitive drawing command, specifies that the rectangular area should be filled. In the RECTANGLE command, the XY coordinates of the upper left end point and the right lower end point of the drawing area (virtual space corresponding to the frame buffer FBa) set in the virtual drawing space are specified (see FIG. 7 (c)). ..

Since the drawing preparation process is completed by the above processing, next, instruction commands for drawing an appropriate texture such as a still image or a moving image frame in the virtual drawing space are listed. Typically, first, the index space IDX to which the texture is expanded is specified by the SETINDEX command of the texture setting system, and then the TXLOAD command, which is the instruction command of the texture load system, is described and read from the CGROM 55. The texture is described in the display list DL so as to expand into a predetermined index space IDX.

As described above, in this embodiment, the background moving image is composed of the IP stream moving image. Therefore, for example, for the background video, the index space IDX to be expanded is specified as the index space IDX ₀ in the page area (b) by the SETINDEX command of the texture setting system, and then the TXLOAD command of the texture load system is described. do. In the TXLOAD command, it is necessary to specify the start address (texture source address) of the CGROM 55 and the expanded data size (horizontal x vertical) for the video frame to be loaded this time.

When the above TXLOAD command is executed in the VDP circuit 52, one moving image frame (texture) of the background moving image is first acquired in the AAC area (a), and then the page area (page area (texture) is automatically activated by the GDEC75. b) Expands to index space IDX ₀ in. Next, this one moving image frame will be drawn in the virtual drawing space. In this case, the SETINDEX command (texture setting system) may be used to set "index space IDX ₀ in the page area (b) is the texture to be processed thereafter", but the TXLOAD command is continuously processed. If so, the description of this SET INDEX command can be omitted.

In any case, in the state where "the index space IDX ₀ in the page area (b) is the texture to be processed after that" is specified, then the parameters for the α blend processing are set, and so on. Describe the instruction command of the appropriate inter-drawing operation system. The α-blending process relates to a transparent / semi-transparent process between an image already described in the drawing area (frame buffer FBa) and an image to be overwritten. Therefore, it is not necessary to use the instruction command of the inter-drawing calculation system in the drawing operation of the first sheet as in the moving image frame of the background moving image.

Then, by using the SPRITE command, which is an instruction command for primitive drawing, "texture of index space IDX ₀ in page area (b) (one video frame of background video)" is set in place in the virtual drawing space (rectangular destination area). Describe the SPRITE command to draw in. For the SPRITE command, it is necessary to specify the upper left end point and the right lower end point of the Destination area of the virtual drawing space.

This Destination area is the whole or a part of the drawing area (virtual space defined on the virtual drawing space) associated with the actual drawing area (FBa) in advance by the instruction commands L11 and L12. However, since the background moving image is usually drawn on the entire display screen, the Destination area in such a case is the entire drawing area or more. The case where the Destination area is larger than the entire drawing area is, for example, the case where the background moving image is zoomed up.

Since the drawing of the video frame of the background video is completed by the above processing, the instruction commands such as the texture load system, the texture setting system, the inter-drawing calculation system, and the primitive drawing system commands are listed in an appropriate order. The display list DL is configured to draw various textures on the background moving image. As described above, a large number of moving images are required at the time of variable production. In that case, the index table control system is instructed to increase the index space IDX for the page area (b) of the built-in VRAM 71. The command (NEWPIX) will be described.

For example, for the second IP stream video, the NEWPIX command allocates an additional index space IDX ₁ in the page area (b), then specifies this index space IDX ₁ (SETINDEX), and then the second Instructs the expansion of one frame of the video (TXLOAD), and places the expanded texture in the appropriate place in the drawing area (SPRITE). Normally, the Destination area in this case becomes a part of the drawing area.

The same applies to the following. If the index space IDX _k is secured one after another by the NEWPIX command and then a plurality of IP streams are drawn in the drawing area while performing appropriate α-blending processing, the drawing contents in the drawing area will be the same. , It will be sequentially accumulated as image data in the frame buffer FBa which is the actual drawing area. When a plurality of N IP stream moving images are drawn, a plurality of N index spaces are functioning in the page area (b).

Then, when a series of fluctuation effects are completed, the DELPIX command is used to release the index space IDX that is considered unnecessary among the large number of index spaces IDX ₁ to IDX _k secured in the page area (b). The unnecessary index space IDX may be deleted.

When drawing a still image or I-stream movie, use the SETINDEX command to specify that the decoding destination of these textures is the AAC area (a), and then execute the TXLOAD command to execute the AAC area. The texture acquired in (a) is then expanded into the ACC area (a) by the automatically activated GDEC75. Then, the expanded texture may be drawn in a suitable place in the drawing area by the SPRITE command.

In the description so far, each texture is drawn directly in the drawing area of the DS1 for the main display device, but the operation is not necessarily limited to such an operation. For example, if an appropriate drawing area is provided (FIG. 7 (c)) in a state where it does not overlap with the drawing area already reserved for the display device DS1, and this drawing area is associated with the work area of the built-in VRAM 71, it is intermediate. It is possible to construct an appropriate drawing area and complete an appropriate staging image. Here, the reason why the drawing area does not overlap with the drawing area for the display device DS1 is that the later association setting is prioritized for the overlapping area and the drawing contents in the area are not reflected in the frame buffer FBa.

As shown in FIG. 7 (c), the work area of this embodiment is the index space IDX ₀ in the arbitrary area (c). Then, in the effect timing using this work area, an instruction command for associating the drawing area for the effect image (see FIG. 7C) with the work area (actual drawing area of index space IDX ₀ ) is preceded. Describe the columns (SETDAVR, SETDAVF, SETINDEX). As described above and shown in FIG. 7C, the drawing area for the effect image is secured in an area not included in the drawing area for the main display device DS1.

Then, after that, the same instruction command as the instruction command sequence L16 regarding the frame buffer FBa may be listed, and an appropriate effect image may be completed in the index space IDX ₀ . In the case of this embodiment, since the staging image is composed of a still image, an instruction command (SETINDEX) is described so that the decoded data is expanded in the AAC area (a), and then the drawing area of the index space IDX ₀ is described. The primitive drawing system instruction command (SPRITE) whose destination is the appropriate place of is used. It should be noted that such an operation is repeated once or a plurality of times depending on the content of the effect.

Then, after positioning the index space IDX ₀ that has completed the effect image as a texture (SETINDEX), the effect image (texture) of the index space IDX ₀ is drawn at an appropriate position in the drawing area of the DS1 for the main display device by the SPRITE command. Just do it. In such a case, it is conceivable to decompose the effect image of the index space IDX ₀ into triangular drawing primitives, rotate them at an appropriate angle, and then draw them in the drawing area. The rotation angle of the texture is associated with, for example, the reliability of the advance notice effect.

The instruction command sequence (L11 to L16) for completing one frame of the main display device DS1 has been described above, but the instruction command sequence (L17 to L12) for completing one frame of the sub display device DS2 has also been described. The same is true. That is, the start XY coordinates of the frame buffer FBb are specified (L17), defined (usually X = 0, Y = 0), and on the virtual drawing space shown in FIG. 7 (c), for the sub-display device DS2. A drawing area is defined (L18).

By the way, in this embodiment, after the generation of the image data for the main display device DS1 is completed, the process shifts to the generation process for the sub display device DS2, so that the drawing area for the sub display device DS2 is for the main display device DS1. There is no problem even if it overlaps with the drawing area of, and the drawing area can be set freely. Therefore, when developing a display list DL generation program, for example, when pasting an appropriate texture to a newly set drawing area with the SPRITE command, set the operation parameters (Destination area) of the SPRITE command and so on. It can be stylized to some extent.

After the definition of such an arbitrary drawing area is completed (L18), next, for the frame buffer FBb of the display device DS2 having a double buffer configuration, the index space becomes the "write area" of the drawing contents based on the display list DL this time. Identify the IDX (L19). The index number of the index space IDX is the index number of the frame buffer FBb that does not correspond to the display area (0) / (1) specified in step ST6 of the main process.

After that, the instruction command sequences L20 to L22 for the sub display device DS2 are listed in the same manner as the instruction command sequences L14 to L16 for the main display device DS1. It is also possible to use the effect image completed in the index space IDX ₀ .

As described above, all the instruction commands of L11 to L22 constituting the display list DL are limited to those having a command length that is an integral multiple of 32 bits in this embodiment. Then, as described above, the data volume value (total amount of data) of the display list DL of this embodiment is adjusted to a fixed length (256 bytes), and the required number of NOP commands (L23) as dummy commands are added. After that, it is terminated by the EODL command (L24). That is, in the embodiment of FIG. 11, the above-mentioned standard method (B) is adopted.

However, even when the standard method (B) is adopted, it is not always essential to fix the total amount of data in the display list DL to 256 bytes in all operation cycles. That is, in another embodiment, when the total amount of data in the display list DL excluding the NOP command exceeds 256 bytes (for example, during a special effect period), the total amount of data in the display list DL is added with the NOP command. Is adjusted to 512 bytes or more, N × 256 bytes. As described above, when the standard method (B) is adopted, the end of N × 256 bytes is terminated by the EODL command.

Although the configuration of the display list DL has been described in detail above, the staging control CPU 63 will issue the completed display list DL having a fixed byte length to the VDP circuit (ST7 to ST8). FIG. 12 is a flowchart illustrating a DL issuing process (ST8 in FIG. 10) in which the effect control CPU 63 directly writes and accesses the transfer port register TR_PORT of the transfer circuit 72 to issue a display list DL to the drawing circuit 76. The transfer port register TR_PORT is a type of data transfer register RGij that defines the operation content of the data transfer circuit 72.

In order to realize the DL issuance process, it is first necessary to set necessary setting values in a plurality of data transfer registers RGij that define the operation contents of the data transfer circuit 72. Specifically, the transfer operation mode of the data transfer circuit 72 and the transmission via the inside of the data transfer circuit 72 are specified in the predetermined data transfer register RGij. The setting contents are not particularly limited, but here, when the data transfer operation is executed while checking the remaining amount of the FIFO buffer with respect to the CPU IF unit 56 via the ChB control circuit 72b and the CPU bus control unit 72d. Set (ST20). In the following description, the ChB control circuit 72b may be abbreviated as "transfer circuit ChB" for convenience.

Next, the total transfer size is set in the predetermined data transfer register RGij. As described above, in this embodiment, the total amount of data in the display list DL is adjusted to an integral multiple of 256 bytes, so that value is set. The total amount of data = 256 × N is also an integer N times the minimum amount of data Dmin of the data transfer circuit 72. Normally, the multiple N is 1 or 2, but in the following description, it will be described as N = 1.

Here, since the transfer port register TR_PORT (hereinafter, may be abbreviated as a transfer port) is a 32-bit length register, the effect control CPU 63 executes a register write operation for the transfer port TR_PORT every 32 bits. It will be. Therefore, the value of the management counter CN that manages the number of register writes is initially set to 64 (ST21). When the non-adjustment method (C) is adopted, the data transfer amount that is an integral multiple of the minimum data amount Dmin is determined at this timing, and the management counter CN is set.

Since the initial setting is completed by the above processing, next, the data transfer operation via the transfer circuit ChB is set to the start state (ST22), and the setting to the predetermined drawing register RGij that regulates the operation of the drawing circuit 76 is set. The drawing operation is started based on the value (ST23). As a result, after that, the effect control CPU 63 guarantees a quick and smooth analysis process by the drawing circuit 76 (display list analyzer) for the instruction command sequence in which the register Write operation is performed on the transfer port TR_PORT.

It should be noted that the fact that the instruction commands listed in the display list DL are limited to the instruction commands having a command length of 32 bits, which is an integral multiple of the command length, also contributes effectively to the quick and smooth Analyze processing. The timings t1, t2, t3, and t4 in FIG. 18A indicate the operation timing of step ST23. Since the display list DL issuance process (ST8) is virtually completed instantly, the time width required for the issuance process is not described in FIGS. 18 to 19.

Then, it is confirmed whether or not the setting of step ST22 has worked (ST24). This is because the initial setting of each part of the data transfer circuit 72 takes more processing time than the register write operation (setting operation) by the effect control CPU 63, so that a subsequent instruction is given to the data transfer circuit 72 in an incomplete state. Because there is no such thing. Then, if the operation start state is not reached even after waiting for a predetermined time, the critical abnormality flag ABN is set and the DL issuance process is completed (ST25). As a result, after that, the watchdog timer 58 functions and the composite chip 50 is abnormally reset (ST10).

However, since the setting of step ST22 is normally completed quickly, it is subsequently confirmed that the FIFO buffer (32 bits x 130 stages) of the CPU bus control unit 72d is not full (ST26). , Write the instruction command to the transfer port TR_PORT line by line in order from the first line constituting the display list DL (ST28).

Then, while decrementing the management counter CN (ST29), the processes of steps ST26 to ST29 are repeated until the management counter CN becomes zero (ST30). In the case of this embodiment, since the minimum data amount Dmin is specified in the data transfer circuit 72, the data transfer operation is executed at the timing when the minimum data amount Dmin is accumulated in the FIFO buffer, which is intermittent. Transfer operation.

In any case, in this embodiment, the DL issuance process (ST28) is completed quickly, but if the settings to the VDP register RGIj are inconsistent due to the influence of noise or the like, step ST26 is performed. In the determination, the state of the FIFO buffer Full may not be resolved even after waiting for a predetermined time. Then, in such a case, the initialization data is set in the predetermined VDP register RGij, the drawing circuit 76 and the data transfer circuit 72 are initialized, and then the serious abnormality flag ABN is set and the DL issuance process is performed. Finish (ST27).

By the way, at this timing, the data transfer circuit 72 and the drawing circuit 76 have already started operation and have completed some processing. Therefore, in the initialization processing of the drawing circuit 76, (1) Display list DL Set all internal parameters that may be set by to the initial values, (2) set all internal control circuits to the initial state, (3) initialize the GDEC75, (4) AAC. It includes initializing the cache state of the area. Similarly, the initialization process of the data transfer circuit 72 includes the initialization process of the entire data transfer up to that point, such as clearing the FIFO buffer. As a result, the status information indicating the operating state of the data transfer circuit 72 changes to a predetermined value (a value indicating that the entire data transfer is being initialized).

In any case, as a result of setting the serious abnormality flag ABN, the watchdog timer 58 then functions and the composite chip 50 is abnormally reset (ST10), so that the drawing circuit 76 and the data transfer circuit 72 are initialized. Processing is not always required. On the other hand, when the drawing circuit 76 and the data transfer circuit 72 are initialized, as a result, abnormal recovery can be expected. Therefore, the DL issuance process is repeated by returning to the process of step ST20 without setting the serious error flag ABN. It is also suitable to carry out.

This point is the same in the process of step ST25, and it is preferable to initialize the data transfer circuit 72 and the drawing circuit 76 and then return to the process of step ST20 without setting the serious abnormality flag ABN. However, in such a case, the number of re-executions of the DL issuance process is counted, and if the number of re-executions exceeds the limit value, the serious abnormality flag ABN is set and the DL issuance process is completed.

FIG. 12B is a confirmatory illustration of a normal operating state. As shown in the figure, the issued display list DL is analyzed by the drawing circuit 76 (display list analyzer) in the order of the listed instruction commands, and the operation based on each instruction command is executed.

For example, when the instruction command (TXLOAD) is executed, the necessary texture is read from the CGROM 55 and acquired in the AAC area (a), and then the GDEC75 is automatically started to execute the decoding operation and decode. Later data is expanded into a given index space. Further, depending on the instruction command, the geometry engine 77 and others function, but in any case, the image data corresponding to the display list DL is completed in the frame buffers FBa and FBb by the cooperation of each part of the drawing circuit 76. Will be.

Subsequently, a case where the display list DL is issued via the DMAC circuit 60 will be described with reference to FIG. Although not limited in any way, the third DMA channel among the first to fourth DMA channels built in the DMAC circuit 60 will be used.

In the embodiment of FIG. 13, first, the data transfer circuit 72 and the drawing circuit 76 are initialized by setting clear values in the predetermined data transfer register RGij and the predetermined drawing register RGij, respectively (ST20). Also in the case of FIG. 12, such an initialization process may be executed first.

In the process of FIG. 13, next, it is confirmed by reading the predetermined status register RGij that specifies the operating state of the data transfer circuit 72 and the drawing circuit 76 that the initialization process is completed normally (ST21). If the initialization cannot be performed, the serious abnormality flag ABN is set and the process is completed (ST22). However, such a situation rarely occurs in reality.

Next, the transfer operation mode of the data transfer circuit 72 and the transmission via the inside of the data transfer circuit 72 are set in the predetermined data transfer register RGij. The setting content is not particularly limited, but here, it is set to follow the setting to the DMAC circuit 60 with respect to the transfer protocol from the CPUIF unit 56 to the CPU bus control unit 72d via the ChB control circuit 72b (ST23). ).

Next, the total transfer size is set in the predetermined data transfer register RGij. As in the case of FIG. 12, the total amount of data = 256. When the non-adjustment method (C) is adopted, the total transfer size that is an integral multiple of the minimum data amount Dmin is determined and set at this timing.
Next, the drawing operation of the drawing circuit 76 is started based on the set value in the predetermined drawing register RGij (ST25). The timings t1, t2, t3, and t4 in FIG. 18A are also the operation timings of step ST25. Then, after starting the operation of the DMAC circuit 60 (ST26), the data transfer operation of the data transfer circuit 72 is started (ST27).

The process of starting the operation of the DMAC circuit 60 is as shown in FIG. 13 (b). First, with the DMAC transfer prohibited, the transfer of one cycle of the data transfer unit (1 operand) is waited for to be completed (1). ST40). The detailed operation content is the same as the process shown in FIG. 14, and is classified into a process for prohibiting DMAC transfer (ST53) and a subsequent standby process (ST54).

Such processing is provided (1) in other embodiments, the DMAC circuit 60 (third DMA channel) may be used in the main processing and the timer interrupt processing (FIG. 10), and , (2) In another embodiment in which the process of step ST5 of FIG. 10 is not provided, the DMAC circuit 60 that has started issuing the display list DL may not be able to end the DL issuing operation within the operation cycle (δ). It is a consideration of what to obtain.

In the above exceptional situation, if a new setting value (inconsistent setting value, etc.) is additionally set for the DMAC circuit 60 in operation, normal DMA operation is not guaranteed at all, and serious trouble occurs. Although there is concern, by providing the process of step ST40, normal operation based on the subsequent set value is guaranteed. That is, even in the modified embodiment in which the present embodiment is partially modified, the subsequent normal DMA operation can be realized regardless of the preceding trouble.

After executing the process of step ST40 having the above significance, the operating conditions of the DMAC circuit 60 are next set (ST41). Specifically, as shown in FIG. 6, the cycle steal transfer mode is selected, and one operand transfer is set to 32 bit transfer × 2 times. Further, since the Source address is the address of the list buffer area (DL buffer) of the RAM 59, it should be recognized as increasing sequentially, while the Destination address should be a fixed value because it is the transfer port TR_PORT.

Next, the start address of the DL buffer of the RAM 59 is set in a predetermined operation control register that defines the operation of the DMAC circuit 60 (ST42), and the address of the transfer port TR_PORT, which is the transfer destination address, is set (ST43). Further, after setting the total transfer size, that is, the total amount of data in the display list DL to 256 bytes (ST44), the DMA operation of the DMAC circuit 60 is started (ST45).

By the way, the description so far is based on the premise that the actual bit lengths of the instruction commands are all integral multiples of 32 bits. However, since the configuration of the display list DL and the instruction command is not necessarily limited, such a case will be described below.

For example, when the total data amount X of the display list DL is an arbitrary value X that is not an integral multiple of 32 bits, including the case where the above-mentioned non-adjustment method (C) is adopted, the arbitrary value X is processed in step ST44. Is adjusted to an appropriate transfer amount MOD, and then the transfer total size setting process is executed. Here, the appropriate transfer amount MOD is defined based on the setting contents for one operand transfer and the minimum data amount Dmin (bytes) of the data transfer circuit 72.

Specifically, if one operand transfer setting is N bytes × M times, the transfer amount MOD is adjusted to an integer multiple of N × M (bytes) and an integral multiple of Dmin (bytes). Will be done. For example, if N × M = 8 × 4 and Dmin = 256, the arbitrary value X (= 300) bytes are adjusted to the transfer amount MOD (= 512) bytes.

As described above, the DMA operation of the DMAC circuit 60 has started the cycle steal transfer operation as shown in FIG. 6, and the display list DL is the embodiment without particularly disturbing the operation of the CPU. In this case, it is transferred to the transfer port TR_PORT every 32 bits. Then, the transferred data is transferred to the drawing circuit 76 via the transfer circuit ChB.

In order to realize such an operation, in this embodiment, following the process of step ST45, the transfer operation of the data transfer circuit 72 is started and the process is completed (ST27). After that, the data transfer circuit 72 receives the instruction command sequence of the display list DL from the DMAC circuit 60 with the minimum data amount Dmin as one unit, and transfers this to the drawing circuit 76. Then, the drawing circuit 76 executes the drawing operation based on the instruction command of the display list DL. Therefore, after the process of step ST27, the effect control CPU 63 can start the process of step ST11 of FIG. 10, and the sound effect is performed in parallel with the drawing operation by the VDP circuit 52 (DL issuance process by the DMAC circuit 60). It is possible to control the lamp effect and the motor effect.

FIG. 13 (c) illustrates this operation content. Prior to the DMA transfer, the operation of the drawing circuit is started (ST25), the display list analyzer of the drawing circuit 76 executes the Analyze process quickly and smoothly, and other operations such as the GDEC75 and the geometry engine 77 are performed. Based on this, in the frame buffers FBa and FBb, image data for each frame is generated for each display device DS1 and DS2.

By the way, the configuration of FIG. 13 in which the DL issuance process is completed by the process of step ST27 is not necessarily limited. For example, as shown in FIGS. 20 to 21, when another CPU controls the sound effect, the lamp effect, and the motor effect, the DMAC circuit 60 and the data transfer circuit 72 normally operate after the processing of step ST27. It is preferable to confirm. FIG. 14 is an operation following step ST27 in FIG. 13, and is a flowchart illustrating a confirmation process of normal operation.

First, it is confirmed that the transfer operation of the DMAC circuit 60 is normally completed by referring to a predetermined status register (ST50). Further, it is confirmed that the data transfer circuit 72 has finished the transfer operation (ST51). Normally, the DL issuance process of FIG. 13 is completed by such a route.

On the other hand, even if you wait for a predetermined time. If the operation of the DMAC circuit 60 is not completed, or if the data transfer circuit 72 has not completed the transfer operation, a clear value is set in the predetermined VDP register RGij for the drawing circuit 76 and the data transfer circuit 72. Then, the DL issuance process is initialized (ST52). This is an operation based on the fact that the display list DL issuance process has not been completed normally.

In this case as well, the drawing circuit 76 has already started operation and has completed some processing, so that the initialization processing of the drawing circuit 76 may be set by (1) the display list DL. Set all internal parameters to the initial values, (2) set all internal control circuits to the initial state, (3) initialize the GDEC75, (4) initialize the cache state of the AAC area. Is included.

Next, after prohibiting a new DMA transfer operation (ST53), it waits for the transfer operation of one operand being executed to end (ST54). As described above, in this embodiment, 32 bit transfer × 2 times is set as one operand, and this is to avoid sudden initialization of the DMAC circuit 60 in operation.

Then, when this preparatory work is completed, a clear value is set in a predetermined operation control register that defines the operation of the DMAC circuit 60, and the DMAC circuit 60 is initialized (ST52). Then, the serious abnormality flag ABN is set and the DL issuance process is completed. In this case, since abnormal recovery can be expected by the processing of steps ST52 and ST55, it is also preferable to return to step ST20 of FIG. 13 and re-execute the DL issuance processing without setting the serious abnormality flag ABN. be. However, it is necessary to count the number of re-executions of the DL issuance process (ST23 to ST27), and if the number of re-executions exceeds the limit value, set the serious abnormality flag ABN and finish the DL issuance process.

Subsequently, the main process when the preloader 73 is used will be described with reference to FIG. The process of FIG. 15 is similar to the process of FIG. 10, but first, the content of the start condition determination (ST5') is different. That is, in the embodiment using the preloader, the status information of the drawing circuit 76 and the preloader 73 is read-accessed at the start of each operation cycle to complete the drawing operation based on the display list DL1 and the display list DL2. Confirm that the preload operation based on is completed (ST5').

As shown in the time chart of FIG. 19A, for example, the preloader 76 has a look-ahead operation (preload operation) during the operation cycle (T1 to T1 + δ) based on the display list DL1 issued in the operation cycle (T1). Should have finished. Further, the drawing circuit 76 should have completed the drawing operation based on the display list DL1 during the operation cycle (T1 + δ to T1 + 2δ) based on the operation start command instructed in the operation cycle (T1 + δ), for example.

Therefore, in the start condition determination (ST5'), the status information of the VDP register RGij regarding the drawing circuit 76 and the preloader 73 is read-accessed to confirm the above-mentioned normal operation. FIG. 19A shows a state in which normal operation is confirmed at the determination timing of the operation cycle T1, T1 + δ, T1 + 2δ, T1 + 4δ, but the preload operation is not completed at the determination timing of the operation cycle T1 + 3δ. ..

Then, at the time of such an abnormality, the abnormality flag ER is incremented (ER = ER + 1), and then the process is shifted to the process of step ST9. Therefore, the frame is dropped as in the case of the embodiment of FIG. That is, since the display area switching process (ST6) is skipped, the same screen is redisplayed. The operating period (T1 + 3δ to T1 + 4δ) shown in FIG. 18A indicates the operating state.

Further, in the determination of step ST5', if the start condition is not satisfied, the drawing operation start instruction (PT10) based on the rewrite list DL'is not executed for the drawing circuit 76, so that the drawing circuit 76 does not operate. It is in a state and no new display list is generated. In FIG. 19A, the timings t0, t2, and t4 indicate the operation timing of the drawing operation start instruction (PT10), or more accurately, the timing of step ST26 in FIG.

The case where the determination in step ST5'is incompatible has been described above, but in a normal case, after switching the display areas of the frame buffers FBa and FBb in a toggle manner (ST6), the rewrite list DL is applied to the drawing circuit 76. 'The drawing operation based on'is started (PT10). The specific contents are as shown in FIG. 16, and the drawing circuit 76 is a rewrite list from the DL buffer of the external DRAM 54 via the data transfer circuit 72 (transfer circuit ChB) based on the control of the staging control CPU 63. DL'is acquired and the drawing operation is executed.

Prior to explaining the flowchart of FIG. 16 that realizes this operation, when the operation of the preloader 73 is confirmed, the preloader 73 preloads the CGROM 55 based on the display list DL acquired one operation cycle before. The pre-read data has already been stored in the preload area secured in the external DRAM 54. Further, for the texture loading command (TXLOAD) described in the display list DL, the source address is rewritten to the address of the preload area, and the rewriting list DL'is stored in the DL buffer of the external DRAM 54. ..

In this rewriting process, the total amount of data in the display list DL does not change, and the total amount of data in the rewriting list DL'is the same as that in the display list DL. Further, the display list DL is created by the standard method (B), and the end of the rewrite list DL'is an EODL command as in the case of the display list DL.

Based on the above, FIG. 16 will be described. First, the staging control CPU 63 sets clear values in the predetermined data transfer register RGij and the predetermined drawing register RGIj, respectively, and sets the data transfer circuit 72 and the drawing circuit 76. Initialize (ST20). Next, it is confirmed that this initialization process is completed normally (ST21), and if the initialization is not completed even after a predetermined time has elapsed, the serious abnormality flag ABN is set and the process is completed (ST21). ST22).

Normally, the initialization of the data transfer circuit 72 and the drawing circuit 76 is normally completed, so that the transmission route inside the data transfer circuit 72 is subsequently set in the predetermined data transfer register RGij (ST23). Specifically, it is set to transfer data from the external DRAM 54 to the drawing circuit 76 via the ChB control circuit 72b (ST23). Next, the start address of the DL buffer of the external DRAM 54 in which the rewrite list DL'is stored is set in the predetermined data transfer register RGij (ST24).

Further, for this rewrite list DL', the total transfer size is set in the predetermined data transfer register RGij (ST25). As described above, the total amount of data in the rewrite list DL'is the same as the total amount of data in the display list DL, and specifically, for example, 256 bytes.

Next, the drawing operation of the drawing circuit 76 is started based on the set value in the predetermined drawing register RGij (ST26). The timings t1, t2, t3, and t4 in FIG. 18A are also the operation timings of step ST26. Then, the operation of the data transfer circuit 60 is started and the process is completed based on the set value in the predetermined data transfer register RGij (ST27). After that, the staging control CPU 63 shifts to the display list generation process (ST7) that is effective in the next operation cycle without being particularly involved in the operation of the data transfer circuit 72 or the drawing circuit.

On the other hand, the drawing circuit 76, which starts the operation at the timing of step ST26, executes the drawing operation based on the rewrite list DL'and generates image data based on the rewrite list DL'in the frame buffers FBa and FBb. In this operation, the drawing circuit 76 exclusively reads and accesses the preload area without reading and accessing the CGROM 55, so that a series of drawing operations can be completed quickly.

Since the processing content of step PT10 has been described above, if the description is continued by returning to FIG. 15, in the embodiment in which the preloader 73 is utilized after the processing of step PT11, the display list DL to be activated in the next cycle is displayed. Created based on the standard method (B) (ST7). For example, in the operation cycle (T1) shown in FIG. 19A, the display list DL referred to by the drawing circuit 76 is created in the operation cycle (T1 + δ) which is the next cycle.

Next, the staging control CPU 63 issues the created display list DL to the preloader 73 instead of the drawing circuit 76 (PT11). The specific operation contents are as shown in FIG. First, regarding the embodiment (FIG. 10) in which the preloader 73 is not used, when the staging control CPU 63 directly issues the display list DL to the drawing circuit 76 (FIG. 12), the staging control CPU 63 directly issues the display list DL to the drawing circuit 76 (FIG. 12) and via the DMAC circuit 60. Although the case of issuing (FIG. 13) is shown, substantially the same operation is shown in FIGS. 17 (b) and 17 (c) except that the issuing destination is the preloader 73. ..

FIG. 17A is a flowchart illustrating the operation of FIG. 17B, which is almost the same as the flowchart of FIG. However, it is set that the data transfer operation is executed from the CPU IF unit 56 via the ChC control circuit 72c and the CPU bus control unit 72d while checking the remaining amount of the FIFO buffer (ST20). In the following description, the ChC control circuit 72c may be abbreviated as "transfer circuit ChC" for convenience.

Next, the total transfer size (for example, 256 bytes adjusted by the standard method (B)) is set to the predetermined data transfer register RGij, and the management counter CN is initially set to 64 (ST21). Next, the data transfer operation via the transfer circuit ChC is set to the start state (ST22), and the preload operation is started based on the set value in the preload register RGij that defines the operation of the preloader 73 (ST23).

As a result, after that, the preloader 73 executes necessary analysis (Analyze) processing for each instruction command written to the transfer port TR_PORT by the effect control CPU 63, and detects an instruction command (TXLOAD) to read-access the CGROM 55. , The texture is preloaded and stored in the preloaded area of the DRAM 54. Further, the rewrite list DL'with the source address of the texture changed is saved in the DL buffer area of the DRAM 54.

The timings t1, t3, and t5 in FIG. 19A substantially indicate the operation timing of step ST23 in FIG. However, also in this embodiment, if any abnormality occurs in the process of issuing the display list DL, the processes of step ST25 and step ST27 are executed. Specifically, the operations of the data transfer circuit 72 and the preloader 73 are initialized, and the display list DL issuance process (ST20 to ST30) is re-executed to the extent possible. The initialization process of the preloader 73 includes a process of erasing the rewrite list DL'in an unfinished state and a process of clearing the preload area in which the preload data is newly stored.

Although the case where the preloader 73 is used and the case where the preloader 73 is not used have been described in detail above, the specific operation content is not particularly limited. FIG. 18B shows an embodiment in which the display list generated by the staging control CPU 63 is issued to the drawing circuit 76 with a delay of one operation cycle δ instead of the generated operation cycle. In the case of such an embodiment, since the drawing circuit 76 can use almost the entire time of one operation cycle (δ), the possibility of frame dropping is reduced.

Further, FIG. 19B shows an embodiment in which the display list generated by the staging control CPU 63 is issued to the preloader 73 with a delay of one operation cycle instead of the generated operation cycle. In this case, since the preloader 73 can execute the pre-doed operation using almost the entire time of one operation cycle (δ), the possibility of frame dropping is reduced in this case as well.

In the description so far, the composite chip 50 is used, but it is not always necessary to integrate the staging control CPU 63 and the VDP circuit into one element. Furthermore, in the above embodiment, the entire effect control is controlled by a single CPU (effect control CPU 63), but the upstream CPU and the downstream effect control CPU 63 cooperate with each other to produce the effect. Control operations may be performed.

20 to 21 are block diagrams showing such an embodiment. As shown in the figure, in this embodiment, the effect control CPU on the upstream side controls the sound effect, the lamp effect, and the motor effect. On the other hand, the built-in CPU 50 on the downstream side controls only the image effect based on the control command CMD'received from the effect control CPU.

When such a configuration is adopted, the built-in CPU 50 does not need to execute the process of step ST12 in FIG. 10 (a) and the process of FIG. 10 (b), and it takes a sufficient amount of time to perform a complicated display list. DL can be generated, and more complicated and advanced image effects such as 3D (Dimension) can be realized. In such a case, the display list becomes large, but in that case, the total amount of data in the display list DL is adjusted to 512 bytes or more by adding a dummy command to N × 256 bytes. ..

Further, since the operation of the built-in CPU 50 on the downstream side is specialized in image effect control, it is possible to confirm that the drawing operation is completed after the display list DL is issued. The lower part of FIG. 12 shows an operation control example in this case, and if the drawing operation is not completed even after the time limit is exceeded, the serious abnormality flag ABN is set and the process is completed (ST32). Since the processing of the built-in CPU 50 on the downstream side is only the image effect control, the completion of the drawing operation may be simply waited in an infinite loop.

When such a configuration is adopted, the start condition determination (ST5) in FIG. 10A can be repeated for a predetermined time. Even with this configuration, if the delay in completing the drawing operation is not so long, only the problem that the switching between the display area (0) and the display area (1) is delayed occurs. That is, as in the operation cycle T1 + 3δ shown in FIG. 22A, in one operation cycle in which the display operation is repeated twice, the frame is dropped only in the first half, and the normal frame is displayed in the second half.

This point is the same when the preloader is used, and the start condition determination (ST5') in FIG. 15A can be repeated for a predetermined time. Then, if there is a slight delay, as shown in the operation cycle T1 + 3δ shown in FIG. 22B, the frame is dropped only in the first half, and a normal frame is displayed in the second half. However, if the completion of the drawing operation is significantly delayed, a complete frame drop will occur as in the operation cycle T1 + 3δ in FIG. 18A, and if such a situation continues, the watchdog timer 58 Will start. Therefore, after that, all or part of the effect control operation (only the image effect) may be abnormally reset based on the underflow signal UF. This point is the same even when the preloader is not used.

Further, when the control operation of the built-in CPU 50 is specialized for image effect control, in the embodiment in which DMA transfer is adopted, as shown in the lower part of FIG. 14, the drawing operation of the drawing circuit 76 is completed and the data transfer circuit 72 is completed. The completion of the operation and the completion of the operation of the DMAC circuit 60 are determined (ST50'to ST52'). If any of the operations is not completed normally, the operations of the data transfer circuit 72 and the drawing circuit 76 are initialized, and the same processing (ST55'to ST57') as the processing of steps ST53 to ST55 is executed. To. Also in this case, it is preferable to re-execute the DL issuance process a predetermined number of times.

Although various examples have been described in detail above, the specific description content does not limit the present invention in any way. Although the ball gaming machine has been described for convenience, the present invention can be suitably applied to other gaming machines such as a spinning machine.

GM gaming machine DL display list 51 CPU circuit 23 Image control means 52 Image generation means 77 Drawing circuit 77
72 Data transfer circuit 63 CPU
60 DMAC circuit ST42, ST43 1st means ST44 2nd means ST45 3rd means

Claims (1)

An image control means having a CPU circuit for issuing a display list for specifying a display screen of a display device, and an instruction command of an integer M (M ≧ 1) times a reference size described in the display list issued by the image control means. An image generation means having a drawing circuit that generates image data based on the above, and is configured to have.
The image control means has a DMAC circuit that repeats a DMA (Direct Memory Access) operation for each transfer unit data size based on an instruction from the CPU of the CPU circuit, and a control register in which a setting value that defines the operation of the DMAC circuit is set. And a list buffer for storing the display list created by the CPU.
The image control means is
With respect to the DMA operation, a first means for instructing the transfer unit data size defined as an integral multiple (> 0) of the reference size, the start address of the list buffer, and the transfer destination of the display list.
A second means of indicating the total data size of the display list to be transferred,
After the instruction operation of the first means and the second means, the drawing operation of the drawing circuit is started, and the third means for instructing the start of the operation of the DMAC circuit is provided.
The instruction operation of the first to third means is realized by writing the instruction value to the control register.
The display list is composed of an instruction command that is an integer M (M ≧ 1) times the reference size, and the total data size is set to an integer N times (N ≧ 1) the transfer unit data size. A game machine to play.

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