JP2008118063A - Semiconductor device, and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress increase in wiring resistance caused by use of catalyst metal and to hold better the coverage of an alloy metal layer on wiring groove. <P>SOLUTION: A first cobalt tungsten phosphide film 107 is formed on copper 106 formed on wiring groove 103 or formed on a portion of copper alloy area by means of an electroless plating method without catalyst metal. Subsequently, the electroless plating method using catalyst metal is used to form a second cobalt tungsten phosphide film 110 on portion 108 which is formed on the wiring groove 103 and is not covered by the first cobalt-tungsten-phosphor film 107. As a result, a palladium film 109 is formed on area having dense wiring, through the first cobalt-tungsten-phosphor film 107, so that metal alloy containing copper is not formed, thereby being capable of suppressing increase in wiring resistance; and the metal alloy layer can be formed on the wiring groove with coverage being good, so that low resistance and high reliable wring can be formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a cap film for preventing copper diffusion is formed on a metal wiring containing copper, and a method for manufacturing the same.

  In recent years, with the miniaturization and speeding up of semiconductor devices, a technique using copper having a lower specific resistance instead of an aluminum alloy conventionally used as a wiring material has begun to be adopted. Copper has a specific resistance of 1.8 μΩ · cm, which is lower than that of aluminum, 2.7 μΩ · cm, which is advantageous for speeding up, and has higher electromigration resistance than aluminum alloys. Is also advantageous.

  Copper wiring is generally used in multiple layers. At that time, in order to prevent copper in the lower layer wiring from diffusing into the upper insulating film, a barrier film made of a silicon nitride film functioning as a copper diffusion preventing film is formed on the lower layer wiring. However, since the silicon nitride film has poor adhesion to copper, when the density of the current flowing through the wiring increases, there is a concern that copper diffuses along the interface and causes wiring defects due to voids. As the process rule becomes finer and the design rule becomes smaller than 45 nm node, the current density flowing through the wiring further increases. Therefore, there is a high possibility that such a void occurs and the reliability of the wiring deteriorates. . In order to prevent such reliability deterioration of the wiring, a cap film made of an alloy having high adhesion to copper, for example, a Co alloy film to which W or P is added (hereinafter referred to as a cobalt tungsten phosphorous film) is formed on the copper wiring. The method of coating is being studied. As a method of forming this cap film, electroless plating is mainly used, and two methods are known: a method using a catalyst metal such as palladium and a method not using a catalyst metal.

First, a method for forming a cap film in the prior art 1 will be described with reference to FIG.
FIG. 2 is a process cross-sectional view illustrating a method of forming a cap film in the semiconductor device of the prior art 1.

  As shown in FIG. 2, first, a silicon nitride film 201 having a thickness of 50 nm is formed on a semiconductor substrate 200 on which elements such as transistors and lower wirings are formed using a plasma CVD method.

Next, a 150 nm-thickness silicon oxide film 202 is formed on the silicon nitride film 201 (FIG. 2A).
Next, a wiring groove pattern is formed on the silicon oxide film 202 using a photoresist, and the wiring groove 203 is formed by removing the silicon oxide film 202 and the silicon nitride film 201 by a dry etching method (FIG. 2 ( b)).

Next, for example, a 20 nm Ta film 204 is formed as a barrier film on the inner wall of the wiring trench 203 using a sputtering method.
Next, a Cu film 205 of, eg, 30 nm is formed using a sputtering method (FIG. 2C).

Next, copper 206 is embedded in the wiring trench 203 using an electrolytic plating method. The film thickness of the copper 206 formed by electrolytic plating is 600 nm in the wiring groove 203 (FIG. 2D).
Next, the copper 206 and the Ta film 204 on the wiring trench 203 are removed and planarized by CMP to form a metal wiring in the wiring trench 203 (FIG. 2E).

  Next, the semiconductor substrate 200 is immersed in a palladium chloride solution. Since palladium has a smaller ionization tendency than copper, a displacement plating reaction of copper 206 exposed on the surface of the wiring groove 203 and palladium ions in the solution occurs, and a palladium film 207 is formed on the surface of the copper 206 in the wiring groove 203. (FIG. 2 (f)).

  Next, a cobalt tungsten phosphorous film 208 as a cap film is deposited on the palladium film 207 by electroless plating. The film thickness of the cobalt tungsten phosphorous film 208 is 1 to 10 nm (FIG. 2 (g)).

Through the above steps, a semiconductor device in which a cap film is formed on the metal wiring using the conventional technique 1 is completed (see, for example, Patent Document 1).
Next, a method for forming a cap film in the prior art 2 will be described with reference to FIG.

FIG. 3 is a process cross-sectional view illustrating a method of forming a cap film in the semiconductor device of the prior art 2.
As shown in FIG. 3, first, a silicon nitride film 301 having a thickness of 50 nm is formed on a semiconductor substrate 300 on which elements such as transistors and lower wirings are formed using a plasma CVD method.

Next, a 150 nm-thickness silicon oxide film 302 is formed on the silicon nitride film 301 (FIG. 3A).
Next, a wiring groove pattern is formed on the silicon oxide film 302 using a photoresist, and the silicon oxide film 302 and the silicon nitride film 301 are removed by a dry etching method to form a wiring groove 303 (FIG. 3 ( b)).

Next, for example, a 20 nm Ta film 304 is formed on the inner wall of the wiring trench 303 as a barrier film by sputtering.
Next, a Cu film 305 of 30 nm, for example, is formed by sputtering (FIG. 3C).

Next, copper 306 is embedded in the wiring groove 303 using an electrolytic plating method. The film thickness of the copper 306 formed by electrolytic plating is 600 nm in the wiring groove 303 (FIG. 3D).
Next, the copper 306 and the Ta film 304 on the upper part of the wiring groove 303 are removed and planarized by CMP, thereby forming a metal wiring in the wiring groove 303 (FIG. 3E).

  Next, a cobalt tungsten phosphorous film 307 as a cap film is deposited in the wiring trench 303 by electroless plating (FIG. 3F). The film thickness of the cobalt tungsten phosphorous film 307 is 1 to 10 nm.

Through the above steps, a semiconductor device in which a cap film is formed on the metal wiring using the conventional technique 2 is completed (see, for example, Patent Document 2).
JP 2001-230220 A US Pat. No. 5,695,810

However, the cap film forming methods according to the prior art 1 and the prior art 2 described above have respective problems.
First, problems of prior art 1 will be described. For example, when palladium is used as the catalyst metal, the surface of the substrate is exposed to a pretreatment solution containing palladium ions, and palladium is deposited on the surface of the wiring groove by displacement plating, and then the cap film is formed using palladium as a nucleus by subsequent electroless plating. Precipitate. In such a method, there is a concern that an increase in wiring resistance is caused because copper is eluted during displacement plating. In addition, there is a problem in that palladium remaining on the wiring diffuses into copper, which is a wiring material, and causes an increase in wiring resistance due to alloying.

  Next, problems of the prior art 2 will be described. When no catalytic metal is used, the cap film is deposited by the catalytic action of copper on the surface of the wiring groove. Here, since the catalytic property of copper is lower than that of noble metals such as palladium, the density of active sites formed by the initial nuclei of the cap film is considered to be lower than that in the case of using a catalytic metal. As a result, a difference between patterns occurs in the growth of the cap metal. In a wiring pattern with a dense wiring pattern ratio (ratio of the surface area of the wiring groove to the total surface area), there is a high possibility that an active site exists on the surface of the wiring groove. It is considered that the entire surface is covered with the cap film. On the other hand, in an isolated wiring pattern with a pattern rate of about 10%, the possibility that an active site is present on the surface of the wiring groove is relatively low, so that the cap film is difficult to deposit, and the cap film is formed on the surface of the wiring groove. It is considered that a portion that is not coated occurs and the covering property is deteriorated. Thus, when the coverage of the surface of the wiring groove by the cap film is poor, the wiring groove surface not covered by the cap film is in contact with the silicon nitride film, so that sufficient wiring reliability cannot be obtained. was there.

  Accordingly, the present invention provides a semiconductor device having a low-resistance and high-reliability wiring by minimizing an increase in wiring resistance due to the use of a catalyst metal and forming a cap film with good coverage on the wiring groove, and It aims at providing the manufacturing method.

  In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device in which a copper trench wiring is formed on a semiconductor substrate on which a semiconductor element is formed, and an insulating film formed on the semiconductor substrate, A metal wiring made of copper or a copper alloy embedded in a groove formed in a predetermined position above the insulating film, a first alloy layer formed on a first region of the metal wiring, and the metal wiring A catalytic metal film formed on the second region outside the first region, and a second alloy film formed on the catalytic metal film.

Furthermore, the catalytic metal film and the second alloy layer are also formed on the first alloy layer.
Further, the first alloy layer is made of a cobalt alloy or a nickel alloy.

Furthermore, the cobalt alloy or the nickel alloy includes at least one of tungsten, phosphorus, and boron.
Furthermore, the catalytic metal film is made of at least one of gold, silver, platinum, palladium, rhodium, iridium, ruthenium, and osmium.

  The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a copper trench wiring is formed on a semiconductor substrate on which a semiconductor element is formed, the step of forming an insulating film on the semiconductor substrate, and the insulation A step of forming a groove at a predetermined position above the film, a step of forming a metal wiring by embedding copper or a copper alloy in the groove, and a first region by electroless plating on the first region of the metal wiring. A step of forming an alloy layer, a step of forming a catalytic metal film on a second region outside the first region on the metal wiring by a displacement plating method, and an electroless plating method on the catalytic metal film And a step of selectively forming the second alloy layer.

Further, in the step of forming the catalytic metal film, the catalytic metal film is also formed on the first alloy layer.
Further, the first alloy layer is made of a cobalt alloy or a nickel alloy.

Furthermore, the cobalt alloy or the nickel alloy includes at least one of tungsten, phosphorus, and boron.
Further, the catalytic metal film is made of at least one of gold, silver, platinum, palladium, rhodium, iridium, ruthenium, and osmium.

  As described above, the cap film can be formed on the surface of the wiring groove with good coverage while suppressing the increase in wiring resistance.

  As described above, the first cobalt tungsten phosphorous film is formed on the copper wiring, and further, the palladium wiring film is formed on the copper wiring portion not covered with the first cobalt tungsten phosphorous film and the first cobalt tungsten phosphorous film. Further, by forming the second cobalt tungsten phosphorous film, it is possible to form a cap film on the surface of the wiring groove with good coverage while suppressing an increase in wiring resistance.

A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to FIG.
FIG. 1 is a process sectional view showing a method for forming a cap film in a semiconductor device of the present invention.

  As shown in FIG. 1, first, a silicon nitride film 101 having a thickness of 50 nm is formed on a semiconductor substrate 100 formed with elements such as transistors and the underlying wiring by plasma CVD. Here, the silicon nitride film 101 may have a relative dielectric constant of 5.0 or less.

  Next, a silicon oxide film 102 having a thickness of 150 nm is formed on the silicon nitride film 101. Here, the insulating film including the silicon oxide film 102 may be a low dielectric constant film having a relative dielectric constant of 2.0 to 3.0 (FIG. 1A).

  Next, a wiring groove pattern having a width of 100 nm is formed on the silicon oxide film 102 using a photoresist, and the wiring groove 103 is formed by removing the silicon oxide film 102 and the silicon nitride film 101 by a dry etching method (see FIG. FIG. 1 (b)).

  Next, a Ta film 104 is formed as a barrier film on the inner wall of the wiring trench 103 by using a sputtering method. The Ta film formation conditions at this time are DC power = 30 kW, AC bias power = 350 W, and the film thickness of the Ta film 104 is desirably 20 nm or less. The barrier film is not limited to the Ta film 104, and may be Ta, Ti, W, or a compound thereof. The film forming method is not limited to the sputtering method, and a CVD method or the like may be used.

  Next, a Cu film 105 is formed on the entire surface of the Ta film 104 by using a sputtering method (FIG. 1C). At this time, the Cu film forming conditions are DC power = 30 kW, AC bias power = 600 W, and the film thickness of the Cu film 105 is desirably 30 nm or less. The Cu film 105 may be a Cu alloy film containing Sn, Ti, Al, and Ag.

Next, copper 106 is embedded on the Cu film 105 in the wiring groove 103 by using an electrolytic plating method. The electrolytic plating deposition conditions at this time are current density = 15 mA / cm ² and rotation speed = 20 rpm, and a copper sulfate solution is used as the electrolytic plating solution. And the film thickness of the copper 106 formed into a film by electroplating is 600 nm. The method for embedding the copper 106 is not limited to the electrolytic plating method, and an electroless plating method or the like may be used (FIG. 1 (d)).

  Next, the copper 106 above the wiring groove 103 and the Ta film 104 outside the wiring groove 103 are removed and planarized by CMP, thereby forming a metal wiring in the wiring groove 103 (FIG. 1E). . Planarization by the CMP method includes two steps: a step of removing the copper 106 and a step of removing the Ta film 104 and the excess silicon oxide film 102. The CMP process conditions for removing the copper 106 are a platen speed of 100 rpm and a pressure of 0.8 psi. The CMP process conditions for removing the Ta film (104) and the silicon oxide film (102) are a platen rotation speed of 80 rpm and a pressure of 1.5 psi.

  Next, a first cobalt tungsten phosphorous film 107 is deposited in the wiring trench 103 by electroless plating (FIG. 1F). The composition of the electroless plating solution is composed of cobalt chloride, ammonium tungstate, ammonium hypophosphite, and ammonium oxalate, and the pH of the electroless plating solution is 10. Moreover, the process temperature of electroless plating is 50-90 degreeC. By this method, by the catalytic action of copper on the surface of the wiring groove 103, a reduction reaction of cobalt ions and tungstate ions by hypophosphite ions proceeds selectively on the wiring groove 103, and the first cobalt. A tungsten phosphorous film 107 is deposited. The first cobalt tungsten phosphorous film 107 is formed in an island shape in the region of the wiring trench. The film thickness of the first cobalt tungsten phosphorous film 107 is desirably 1 to 10 nm at a location where the area ratio of the wiring pattern (the ratio of the surface area of the wiring groove 103 to the total surface area) is 50%. However, since the catalytic activity of copper is lower than that of noble metals such as palladium, a phenomenon that the first cobalt tungsten phosphorous film 107 is difficult to be deposited on the surface of the wiring groove 103 occurs when the area ratio of the wiring pattern is low. To do. Therefore, in an isolated wiring pattern in which the area ratio of the wiring pattern is about 10%, a portion 108 that is not covered with the first cobalt tungsten phosphorous film 107 is generated on the surface of the wiring groove 103.

  Next, the semiconductor substrate 100 is immersed in a palladium chloride solution adjusted to pH = 1 with hydrochloric acid. Since palladium has a smaller ionization tendency than copper and cobalt, a displacement plating reaction of copper and cobalt exposed on the surface of the wiring groove 103 and palladium ions in the solution occurs, and the surface of the first cobalt tungsten phosphorous film 107, and Then, the palladium film 109 is formed on the surface 108 of the wiring groove in the portion not covered with the first cobalt tungsten phosphorous film (FIG. 1G). At this time, the palladium film 109 was formed on both the surface of the first cobalt tungsten phosphorous film 107 and the surface 108 of the wiring trench that was not covered with the first cobalt tungsten phosphorous film. What is necessary is just to form on the surface 108 of the wiring groove | channel of the part which was not coat | covered with the 1st cobalt tungsten phosphorus film | membrane by the method of immersing in a palladium chloride solution in the state which masked the tungsten phosphorus film | membrane.

  Next, a second cobalt tungsten phosphorous film 110 is deposited on the palladium film 109 by electroless plating. The composition of the electroless plating solution and the film forming conditions are the same as those used when the first cobalt tungsten phosphorous film 107 was deposited. The film thickness of the second cobalt tungsten phosphorous film 110 is 1 to 10 nm. Since the catalytic activity of palladium is higher than that of copper, the second cobalt tungsten phosphorus film 110 is uniformly formed on the palladium film 109, and a cap film can be formed on the wiring groove with good coverage (see FIG. FIG. 1 (h)). Further, in the dense wiring region, the palladium film 109 is formed via the first cobalt tungsten phosphorous film 107, so that an alloy with copper is not formed, and an increase in wiring resistance can be suppressed.

Through the above steps, a semiconductor device in which a cobalt tungsten phosphorous film, which is a cap film, is formed on the surface of the wiring groove with good coverage while suppressing an increase in wiring resistance is completed.
According to the embodiment of the present invention, an increase in wiring resistance of about 10 to 20% observed when a cobalt tungsten phosphorous film is formed using an electroless plating method using a conventional catalytic metal is suppressed to about several percent. And the same reliability as the electroless plating method using a conventional catalytic metal can be obtained.

  In the above embodiment, palladium is used as the catalyst metal. However, as the catalyst metal, a noble metal element such as gold, silver, platinum, palladium, rhodium, iridium, ruthenium, osmium, or an alloy thereof may be used. . Further, the cap film is not limited to the cobalt tungsten phosphorous film used in the above embodiment, and may be a cobalt alloy or nickel alloy containing at least one selected from tungsten, phosphorous, and boron.

  According to the present invention, a cap film can be formed on the surface of a wiring groove with good coverage while suppressing an increase in wiring resistance, and a cap film for preventing copper diffusion is formed on a metal wiring containing copper. This is useful for semiconductor devices and manufacturing methods thereof.

Process sectional drawing which shows the formation method of the cap film in the semiconductor device of this invention Process sectional drawing which shows the formation method of the cap film in the semiconductor device of prior art 1 Process sectional drawing which shows the formation method of the cap film in the semiconductor device of the prior art 2

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 101 Silicon nitride film 102 Silicon oxide film 103 Wiring groove 104 Ta film 105 Cu film 106 Copper 107 First cobalt tungsten phosphorus film 108 Part not covered with the first cobalt tungsten phosphorus film 109 Palladium film 110 Second cobalt Tungsten phosphorous film 200 Semiconductor substrate 201 Silicon nitride film 202 Silicon oxide film 203 Wiring groove 204 Ta film 205 Cu film 206 Copper 207 Palladium film 208 Cobalt tungsten phosphorous film 300 Semiconductor substrate 301 Silicon nitride film 302 Silicon oxide film 303 Wiring groove 304 Ta film 305 Cu film 306 Copper 307 Cobalt tungsten phosphorus film

Claims (10)

A semiconductor device in which a copper trench wiring is formed on a semiconductor substrate on which a semiconductor element is formed,
An insulating film formed on the semiconductor substrate;
A metal wiring made of copper or a copper alloy embedded in a groove formed in a predetermined position on the insulating film;
A first alloy layer formed on the first region of the metal wiring;
A catalytic metal film formed on a second region outside the first region on the metal wiring;
And a second alloy film formed on the catalyst metal film.   2. The semiconductor device according to claim 1, wherein the catalytic metal film and the second alloy layer are also formed on the first alloy layer.   The semiconductor device according to claim 1, wherein the first alloy layer is made of a cobalt alloy or a nickel alloy.   4. The semiconductor device according to claim 3, wherein the cobalt alloy or nickel alloy contains at least one of tungsten, phosphorus, and boron.   The catalyst metal film is made of at least one of gold, silver, platinum, palladium, rhodium, iridium, ruthenium, and osmium, according to claim 1, claim 2, claim 3, or claim 4. The semiconductor device according to any one of the above. A method of manufacturing a semiconductor device in which a copper trench wiring is formed on a semiconductor substrate on which a semiconductor element is formed,
Forming an insulating film on the semiconductor substrate;
Forming a groove at a predetermined position on the insulating film;
Forming a metal wiring by embedding copper or a copper alloy in the groove;
Forming a first alloy layer on the first region of the metal wiring by electroless plating;
Forming a catalytic metal film by displacement plating on a second region outside the first region on the metal wiring;
And a step of selectively forming a second alloy layer on the catalytic metal film by an electroless plating method.   7. The method of manufacturing a semiconductor device according to claim 6, wherein in the step of forming the catalytic metal film, the catalytic metal film is also formed on the first alloy layer.   The method for manufacturing a semiconductor device according to claim 6, wherein the first alloy layer is made of a cobalt alloy or a nickel alloy.   The method of manufacturing a semiconductor device according to claim 6, wherein the cobalt alloy or the nickel alloy includes at least one of tungsten, phosphorus, and boron.   The catalyst metal film is made of at least one of gold, silver, platinum, palladium, rhodium, iridium, ruthenium, and osmium, according to claim 6, claim 7, claim 8, or claim 9. The manufacturing method of the semiconductor device in any one.

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