JP2003179058A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve selectivity in the metal-system barrier film covering process with the electroless plating in order to eliminate operation failure by continuation among wirings. <P>SOLUTION: In forming a barrier film having the copper diffusion preventing function on a metal wiring including copper with the electroless plating method, the area where the metal wiring is not formed is etched before formation of the barrier film with the electroless plating method. As the etching process, the wet etching or dry etching using the hydrofluoric acid is performed. Otherwise, after the barrier film is formed with the electroless plating method, this barrier film is cleaned using an alkali chemical solution or weak acidic chemical solution including the chelating agent as the cleaning solution. An interfacial active agent may be mixed to the alkali chemical solution. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a metal wiring containing copper.

[0002]

2. Description of the Related Art Conventionally, an aluminum alloy has been used as a material for fine wiring of a high density integrated circuit (hereinafter referred to as a semiconductor device) formed on a semiconductor wafer. However, in order to further increase the speed of the semiconductor device, it is necessary to use copper or silver having a lower specific resistance as a wiring material. In particular, copper has a specific resistance of 1.8μ.
Since it is as low as Ωcm, which is advantageous for increasing the speed of a semiconductor device, and has an electromigration resistance higher than that of aluminum-based alloys by an order of magnitude, it is expected as a next-generation material.

In the wiring formation using copper, so-called damascene method is used because it is generally not easy to dry-etch copper. This is because, for example, a predetermined groove is formed in advance in an interlayer insulating film made of silicon oxide, a wiring material (copper) is embedded in the groove, and excess wiring material is chemically mechanically polished (hereinafter referred to as CMP). This is a method of forming a wiring by removing it. Further, after forming the connection hole (Via) and the wiring groove (Trench), the wiring material is embedded at once and the surplus wiring material is CMed.
A dual damascene method of removing by P is also known.

By the way, copper wiring is generally used in a multilayer structure. At that time, for the purpose of preventing the diffusion of copper into the insulating film, a barrier film made of silicon nitride, silicon carbide or the like is formed before forming the upper layer wiring.

However, silicon nitride and silicon carbide have a larger relative permittivity than silicon oxide, which causes an increase in wiring capacitance. There is also a problem that the interface between the copper wiring and the barrier film made of silicon nitride, silicon carbide or the like is poor in electromigration (EM) resistance.

In order to avoid the above disadvantages, a method of forming a metal-based copper diffusion preventing material on a copper wiring is also known. For example, TiN or the like is formed on the entire surface,
The method of leaving TiN etc. only on the copper wiring by CMP
A method of selectively forming a film on a copper wiring by the VD method has been proposed. However, these methods have manufacturing problems such as contamination of the vacuum device.

[0007]

Therefore, as an alternative technique, a method of forming a Co-based material on a copper wiring by an electroless plating method has been developed. With this technology,
Compared with the previous two technologies, it is possible to say that wiring can be formed at a low cost with a simple device, which is a very effective technology.

On the other hand, however, there remains a big problem in terms of selective formation on the copper wiring. That is, in the case of coating the copper wiring with the Co-based material by electroless plating, it is difficult to reliably and selectively form a film only on the copper wiring, and there is a technical barrier in this respect.

In the electroless plating, a film forming process is performed on the entire surface of the copper wiring portion and the field portion where the wiring is not formed. However, if something becomes a nucleus, the Co-based coating film is formed even on the field portion. Are formed and the selectivity is deteriorated. As design rules shrink,
Although the design rule between the wirings is also reduced, the deterioration of the selectivity of the Co-based coated metal process causes the conduction between the wirings and the malfunction of the semiconductor device.

The present invention has been proposed for the purpose of eliminating the disadvantages of the prior art. That is, the present invention provides a method of manufacturing a semiconductor device capable of improving the selectivity in a metal-based barrier film coating process by electroless plating and manufacturing a highly reliable semiconductor device without malfunction due to conduction between wirings. The purpose is to do.

[0011]

In order to achieve the above object, the first invention of the present application forms a barrier film having a copper diffusion preventing function on a metal wiring containing copper by an electroless plating method. A method of manufacturing a semiconductor device is characterized in that a portion where no metal wiring is formed is etched before the barrier film is formed by an electroless plating method.

In the electroless plating method, the barrier film made of a Co-based material or the like is exposed to the plating solution on the two kinds of surfaces on the copper wiring and the field portion. Of these, the barrier film is formed only on the copper wiring. It is necessary to prevent the film from being formed on the field portion by forming the film. In principle, when forming a film on a copper wiring, since copper is a metal, the barrier film can be formed without any problem, while there is no metal in the field part, so electrons can be supplied. Therefore, the barrier film should not be formed. However, the film formation process of the barrier film by electroless plating is a process performed after CMP, and the surface after CMP is often not an ideal surface for selectively forming the barrier film. .

In the present invention, before forming the barrier film by the electroless plating method, the surface state where the barrier film can be selectively formed by previously etching the portion where the metal wiring is not formed. To achieve the desired selectivity. As a result, the barrier film is selectively formed only on the metal wiring, and conduction between the wirings is eliminated.

A second invention of the present application is a method for manufacturing a semiconductor device, wherein a barrier film having a copper diffusion preventing function is formed on a metal wiring containing copper by electroless plating.
After the barrier film is formed by an electroless plating method, an alkaline chemical solution containing a chelating agent or a weakly acidic chemical solution is washed as a washing solution.

In the second aspect of the invention, the extra barrier film is removed by the chemical treatment (cleaning). Therefore, the barrier film is selectively formed only on the metal wiring, and conduction between the wirings is eliminated.

As described above, by using the inventions of the present application, it is possible to surely form the barrier film selectively, but this brings about the following effects. First, since it is not necessary to use an insulating film barrier such as SiC or SiN having a high dielectric constant which is widely used for copper wiring, the wiring capacitance can be reduced and the speed of the semiconductor device can be increased. Also, with the miniaturization of wiring, the wiring shape shrinks, and the EM resistance tends to deteriorate. One of the causes of deterioration of EM resistance is insulation film (SiC, SiN
Etc.) and the formation of voids at the interface between copper. When the barrier film is a metal film formed by electroless plating, the copper and the insulating film are not in contact with each other and the metals are in contact with each other, so that the EM resistance is significantly improved.

[0017]

DETAILED DESCRIPTION OF THE INVENTION A method of manufacturing a semiconductor device to which the present invention is applied will be described below in detail with reference to the drawings.

The semiconductor device targeted by the present invention has a metal wiring containing copper, and a barrier film having a copper diffusion preventing function is formed on the metal wiring. A cobalt alloy or a nickel alloy is used as the barrier film, and this is formed by an electroless plating method. Here, as the cobalt alloy, CoP, CoB, CoW, CoMo, CoWP,
CoWB, CoMoP, CoMoB, etc. can be mentioned. Further, as the nickel alloy, NiWP, NiW
B, NiMoP, NiMoB, etc. can be mentioned.
In addition, Co and Ni alloyed, W and M
A combination in which both o are alloyed can also be mentioned. By adding tungsten or molybdenum to cobalt or nickel, the effect of preventing copper diffusion is increased. Also,
Phosphorus and boron, which are secondarily mixed in by electroless plating, also form the deposited cobalt and nickel into a fine crystal structure and contribute to the copper diffusion preventing effect.

By forming the barrier film having the copper diffusion preventing function by the electroless plating method, the barrier film can be selectively formed only on the metal wiring, and the step of etching the barrier film can be omitted. To form a barrier film on a metal wiring containing copper by electroless plating,
The surface of the metal wiring layer must be subjected to a catalyst activation treatment using Pd or the like, which has a high catalytic property. The pretreatment method is as follows.

Degreasing treatment: The alkali degreasing improves the wettability of the surface. Acid treatment: Neutralize with 2-3% hydrochloric acid, etc., and at the same time, remove Cu that is oxidized on the surface. Pd substitution treatment: Using a hydrochloric acid solution of PdCl ₂ , the outermost surface of the metal wiring is substituted with Pd to form a catalytically active layer. This is the use of displacement plating, which utilizes the difference in ionization tendency of dissimilar metals. Since Cu is a metal that is electrochemically base compared to Pd, the electrons emitted by dissolution in the solution are transferred to Pd, which is the noble metal in the solution, and Pd is formed on the Cu surface of the base metal. To be done. Therefore, the oxide film,
For example, Pd is not replaced on TEOS. As a specific example of the treatment, for example, Pd having a pH of about 1 at 30 to 50 ° C.
The displacement plating treatment was performed in a hydrochloric acid solution of Cl ₂ . The metal to be replaced may be platinum, gold, rhodium or the like. Pure water rinse

In the above pretreatment, the degreasing treatment and the acid treatment may be carried out as necessary. Further, examples of the processing method in the above-mentioned degreasing treatment, acid treatment, and Pd substitution treatment include spin treatment using a spin coater, paddle treatment, and dipping treatment.

Next, a Co alloy film or N is formed on the surface to be plated which is catalytically activated by the Pd by electroless plating.
An i alloy film or the like is formed as a barrier film. As described above, Pd of the catalyst activation layer is replaced only on the surface of Cu, and electroless plating is formed only where Pd exists. Therefore, it is possible to selectively form a barrier film only on Cu (metal wiring). The composition of the electroless plating solution and examples of conditions are as follows.

<In the case of CoP> Composition Cobalt chloride: 10 to 100 g / l (cobalt sulfate, etc.) Glycine: 2 to 50 g / l (ammonium salts such as succinic acid, malic acid, citric acid, malonic acid, formic acid, or the like) Ammonium hypophosphite: 2-200 g / l (formalin, glyoxylic acid, hydrazine, ammonium borohydride, etc.) Ammonium hydroxide (TMAH, TMAC, KOH, etc.) Conditions 50-95 ° C., pH 7-12

When formalin, glyoxylic acid, hydrazine or the like is used in place of ammonium hypophosphite in the above electroless plating solution composition, the barrier film is a film containing no phosphorus (P). When ammonium borohydride or the like is used, a film containing boron (B) instead of phosphorus (P) is obtained. This also applies to the following electroless plating solution compositions.

<CoWP, CoMoP, NiWP, Ni
MoP> Composition cobalt chloride or nickel chloride: 10-100 g /
l (Cobalt sulfate, nickel sulfate, etc.) Glycine: 2 to 50 g / l (ammonium salt such as succinic acid, malic acid, citric acid, malonic acid, formic acid, or a mixture thereof) Ammonium tungstate: 3 to 30 g / l (Ammonium molybdate) Ammonium hypophosphite: 2-200 g / l (formalin, glyoxylic acid, hydrazine, ammonium borohydride, etc.) Ammonium hydroxide (TMAH, TMAC, KOH, etc.) Conditions 50-95 ° C., pH 8-12

As for the electroless plating, it is possible to form a film by a spin process using a spin coater, a puddle process, or a dipping process as in the Pd replacement process.

The above is a schematic method of electroless plating for forming a barrier film. However, in coating copper wiring with electroless plating of a Co-based material or the like, it is possible to ensure that selective etching is performed only on the copper wiring. It is difficult to form a film, and there is a technical barrier in this respect. Therefore, in the present invention, the barrier film is selectively formed only on the copper wiring by performing the pretreatment or the posttreatment of the electroless plating.

First, as a pretreatment for electroless plating, a method of etching a portion where no metal wiring is formed can be mentioned. By pre-etching the portion where the metal wiring is not formed, a surface state in which a barrier film can be selectively formed is obtained, and desired selectivity is achieved.

Examples of the above etching include a method of etching the insulating film on the field by 2 to 50 nm by a wet method. At this time, it is not allowed to etch the copper that will be the wiring. One effective method is etching with hydrofluoric acid (HF). At this time, the concentration of hydrofluoric acid is preferably set to 10% or less in consideration of the process margin and the like.

As the etching method, the insulating film on the field is dry-etched by 2 to 50 n.
The method of removing m can also be mentioned. Also in the dry etching, similarly to the above, it is not allowed to largely etch the copper of the wiring. Therefore, as the dry etching method, plasma etching using a gas system such as CF _x , CH _x F _y, or a back sputtering method in which an inert gas such as Ar is ionized and collided with the insulating film on the field to be removed is used. Is preferred.

Next, the post-treatment of electroless plating is a cleaning treatment using a chemical solution. This cleaning process removes the extra barrier film, and as a result, the barrier film is selectively formed only on the metal wiring.

First of all, the cleaning process using the chemical solution is first.
Another example is a treatment of washing with an alkaline chemical solution. As the alkaline chemical solution, a solution containing a chelating agent is used, and the chelating effect is used to remove the coating metal left on the field and the conductive chemical solution residue used when forming the coating metal. . Chelating agents mixed in alkaline chemicals include EDTA and HED
A carboxylic acid type chelating agent such as TA and a phosphonic acid type chelating agent can be used.

Secondly, in order to easily remove the coated metal left on the field, the above alkaline chemical liquid mixed with a surfactant is applied. Thirdly, the coated metal left on the field is strongly removed physically by ultrasonic cleaning, and then an alkaline chemical solution containing a chelating agent or an alkaline chemical solution containing a chelating agent and a surfactant is used. And wash. Fourth, the coated metal left on the field is etched with a weakly acidic chemical solution. However, at this time, the etching amount of the coating metal formed on the metal wiring is controlled to be 10 nm or less.
In each of the above methods, the cleaning method may be either dip-type cleaning or single-wafer cleaning.

The above is the basic forming process for forming the barrier film, but the above-mentioned pretreatment (etching) and post-treatment (chemical treatment) may be carried out individually or in combination. It is also possible to do so.

Next, a specific example of wiring formation to which these pre-treatments or post-treatments are applied will be described. In this example, for the sake of simplification of description, the structure having only the wiring groove is used, but a dual damascene structure in which the wiring groove and the hole are simultaneously processed or a single damascene structure having only the hole may be used.

When forming the wiring, first, as shown in FIG. 1A, a groove (wiring groove) 2 for forming a wiring in the insulating film 1 is formed.
To form. As the insulating film 1 that electrically insulates the wires from each other, any known insulating material can be used, and for example, an oxide film or a low dielectric constant material film can be used.

FIG. 1B shows a film forming process of a wiring material. The wiring material is formed by a barrier metal and a seed C.
It comprises a u film forming step and a Cu burying step. As a result, the barrier metal layer 3, the seed Cu film (not shown) and the wiring layer 4 are formed. The barrier metal layer 3 can be made of a material such as Ta, TaN, TiN, or WN that has an excellent barrier property against Cu. Seed Cu
The film is Cu-plated by electrolytic plating in the next Cu embedding step.
Is to be a conductive layer when the film is formed. The barrier metal layer 3 and the seed Cu film are formed by PVD or CVD.
The law etc. can be mentioned. The film thickness of each depends on the design rule, but is 50 nm or less for the barrier metal layer 3 and 200 n for the seed Cu film.
m or less is desirable. Although the electrolytic plating method is widely adopted in the Cu embedding step, the present invention is not limited to this, and for example, CV may be used.
There is no problem with method D. The film thickness varies depending on the depth of the wiring groove 2, but as a guide, it is preferably 2.0 μm or less.

FIG. 1C shows a wiring forming process in which Cu is left only in the wiring groove 2. A commonly applied technique is polishing by CMP. In this step, it is necessary to control the polishing at the insulating film 1 so that the wiring material remains only in the groove, and to control the wiring material so that the wiring material does not remain on the insulating film 1. In the polishing process by CMP, two or more kinds of materials, Cu and barrier metal, must be removed by polishing, so it is necessary to control the polishing liquid (slurry), polishing conditions, etc. depending on the material to be polished. Therefore, polishing in multiple steps may be necessary.

After the above polishing, the barrier film is usually formed immediately by electroless plating, but here, as shown in FIG.
As shown in FIG. 1, after the surface of the insulating film 1 on which the wiring layer 4 is not formed is etched by 2 to 50 nm, the barrier film 5 is formed by electroless plating as shown in FIG. The etching in FIG. 1D and the formation of the barrier film by electroless plating in FIG. 1E are as described above. In this example, 0.5% HF was used for etching.

FIG. 2 shows the inter-wiring leak characteristics when no pretreatment was performed prior to electroless plating. Since there is a possibility that the inter-wiring leak characteristic is deteriorated due to some nucleus existing inside the field, over-polishing by CMP was changed as a parameter to measure the characteristic. In FIG. 2, “initial” is the inter-wiring leak characteristic before the coating metal film is formed, and shows a good leak characteristic before the coating metal film is formed under any condition. However, as can be seen from these results, even if over-polishing is performed, the inter-wiring leakage characteristics after the formation of the coated metal should return to the characteristics before the formation of the coated metal, especially in the case where the inter-wiring space width is small. It was demonstrated that the selectivity was poor. It is considered that this is a result of rubbing factors that deteriorate the selectivity on the field by polishing by CMP in the wiring forming process.

FIG. 3 shows inter-wiring leakage characteristics when pretreatment (etching) is performed prior to electroless plating. In this case, even if the wiring width is narrow, the inter-wiring leakage characteristics after the coating metal film formation are equivalent to the inter-wiring leakage characteristics before the film formation. That is, it means that there is an effect of the pretreatment before forming the coated metal film, and that the characteristics enough to be used as the wiring of the semiconductor are obtained.

Next, the measurement results when the post-treatment (chemical solution cleaning) is performed instead of the above-mentioned pre-treatment will be described. The wiring forming process is as shown in FIG. 1 like the previous example, but here, instead of the etching process shown in FIG. 1D, a chemical solution is used after the barrier film forming process of FIG. 1E. A washing process was performed.

The results showing the coverage metal selectivity when the above-mentioned post-treatment is applied are shown below using the inter-wiring leak characteristic which is an electrical characteristic. In addition, although the chemical solution in which the chelating agent is mixed with the above-mentioned alkaline chemical solution is applied to the treatment after forming the coated metal film here, similar results can be obtained by applying other chemical solutions. It was Further, although the single-wafer cleaning method is used as the cleaning method, the cleaning method is not limited to this and, for example, a dip method can also be adopted.

FIGS. 4 and 5 show the results of the inter-wiring leak measurement, and the post-treatment time after the coating metal treatment was 60 times, respectively.
Seconds and 120 seconds. Moreover, since the focus is on the selectivity of the coating metal, the dependence of the wiring width is used as a parameter. In FIG. 4 and FIG. 5, “initial” means the inter-wiring leak characteristic before the coating metal film is formed, and “after the coating metal film is formed” means that the coating metal film is washed only with pure water. "Post-processing (60 sec)" means the processing according to the present invention, and the processing in parentheses indicates the processing time.

In any leak characteristic between wirings, “in
The leak characteristics of "itial" were good, but when post-treatment was not performed, the leak characteristics after forming the coating metal were worse than those of "initial". 2 to 10 times the current was flowing between the wirings. Then, by applying the cleaning according to the present invention to treat the coated metal, the increased leakage current is reduced,
A value close to the "initial" leak current value was obtained. Therefore, it has been proved that the cleaning after the coating metal film formation in the present invention has a sufficient effect of improving the selectivity.

[0046]

As is apparent from the above description, according to the present invention, it is possible to improve the selectivity in the metal-based barrier film coating process by electroless plating, and to prevent malfunction due to conduction between wirings. It is possible to solve the above problem and manufacture a highly reliable semiconductor device.

Further, the following effects can be expected by applying the present invention. That is, first, by forming the coating metal on the Cu wiring, the barrier insulating film such as SiN or SiC having a high dielectric constant, which is indispensable in the conventional technique, is unnecessary. Therefore, the effective dielectric constant of the interlayer insulating film of the semiconductor is reduced, and the wiring capacitance is also reduced. Therefore, an improvement in wiring speed can be expected. Also,
Since SiN, SiC, etc. having a high dielectric constant are not necessary, the number of laminated layers and the number of laminated layers of the interlayer insulating film of the semiconductor are reduced. Therefore, it becomes easy to process holes and trenches in the interlayer insulating film, and a stable processing process can be applied. Then, the stable processing process contributes to the improvement of the yield of semiconductors.

Further, since the adhesiveness at the interface between the Cu wiring and the insulating film is weak, it becomes a base point for inducing electromigration (EM) and deteriorates EM resistance.
By applying the coating metal on the wiring, the interface between the Cu wiring and the insulating film does not exist, so that improvement in EM resistance can be expected. Further, the barrier insulating films SiN, SiC and the like are films having a high compressive stress, which is a factor that deteriorates stress migration (SM) and EM resistance. However, in the present invention, these barrier insulating films are not necessary.
Improvement in M and EM resistance can be expected.

[Brief description of drawings]

1A and 1B show an example of a wiring forming process in a semiconductor device, in which FIG. 1A is a schematic sectional view showing a wiring groove forming step in an insulating layer, and FIG. 1B is a schematic sectional view showing a wiring material embedding step; (C) is a schematic sectional view showing a CMP polishing step, (d) is a schematic sectional view showing an etching step, and (e).
FIG. 6 is a schematic cross-sectional view showing a barrier film forming step.

FIG. 2 is a characteristic diagram showing inter-wiring leakage characteristics when no pretreatment (etching) is performed.

FIG. 3 is a characteristic diagram showing inter-wiring leakage characteristics when pretreatment (etching) is performed.

FIG. 4 is a characteristic diagram showing inter-wiring leak characteristics when post-treatment (chemical solution treatment for 60 seconds) is performed.

FIG. 5 is a characteristic diagram showing inter-wiring leak characteristics when post-treatment (chemical solution treatment for 120 seconds) is performed.

[Explanation of symbols]

1 insulating film, 2 wiring groove, 3 barrier metal layer, 4 wiring layer, 5 barrier film

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) C23F 1/18 C23F 4/00 A 4/00 H01L 21/288 Z H01L 21/288 21/88 B (72 ) Inventor Otorii Hide 7-6, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Inventor Takeshi Nogami 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo F-term (Reference) ) 4K022 AA02 AA42 BA04 BA06 BA12 BA14 BA16 BA24 BA32 CA06 DA01 DB02 DB03 4K057 DA11 DA16 DB04 DD01 DD02 DG20 DN01 WA11 WB04 WE01 WN01 4M104 BB04 BB05 BB16 BB17 BB18 BB30 BB32 BB33 DD22 DD33 DD43 DD52 DD53 DD75 DD89 FF17 FF18 FF22 HH01 HH02 HH20 5F033 HH07 HH11 HH15 HH21 HH22 HH32 HH33 HH34 MM01 MM02 MM08 MM11 MM12 MM13 PP06 PP14 PP27 PP28 PP35 QQ11 QQ14 QQ19 QQ48 QQ91 WW02 XX01 XX05 XX06 XX24 XX31

Claims (18)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a barrier film having a copper diffusion preventing function is formed on a metal wiring containing copper by electroless plating before the barrier film is formed by electroless plating. A method for manufacturing a semiconductor device, which comprises etching a portion where a metal wiring is not formed. 2. In the above etching, 2 to 50 n
The method of manufacturing a semiconductor device according to claim 1, wherein the etching is performed by m etching. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the etching is performed by wet etching. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the wet etching is performed using hydrofluoric acid. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the etching is performed by dry etching. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the dry etching is performed by plasma etching or back sputtering. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the barrier film is formed of at least one selected from a cobalt alloy and a nickel alloy. 8. The cobalt alloy or nickel alloy,
8. The method of manufacturing a semiconductor device according to claim 7, further comprising at least one selected from tungsten, molybdenum, phosphorus and boron. 9. The method of manufacturing a semiconductor device according to claim 1, wherein a catalyst layer is formed on the metal wiring, and then a barrier film is formed by an electroless plating method. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the catalyst layer is selectively formed on the metal wiring by utilizing a difference in ionization tendency of different metals. 11. A method of manufacturing a semiconductor device, wherein a barrier film having a copper diffusion preventing function is formed on a metal wiring containing copper by an electroless plating method, after the barrier film is formed by an electroless plating method, A method of manufacturing a semiconductor device, which comprises cleaning an alkaline chemical solution or a weakly acidic chemical solution containing a chelating agent as a cleaning solution. 12. The method of manufacturing a semiconductor device according to claim 11, wherein an alkaline chemical liquid containing a chelating agent mixed with a surfactant is used as the cleaning liquid. 13. The method for manufacturing a semiconductor device according to claim 11, wherein at least one selected from a carboxylic acid chelating agent and a phosphonic acid chelating agent is used as the chelating agent. 14. The method of manufacturing a semiconductor device according to claim 11, wherein cleaning with the cleaning liquid is performed after ultrasonic cleaning. 15. The method of manufacturing a semiconductor device according to claim 11, wherein the barrier film is formed of at least one selected from a cobalt alloy and a nickel alloy. 16. The cobalt alloy or the nickel alloy contains at least one selected from tungsten, molybdenum, phosphorus, and boron.
A method for manufacturing a semiconductor device as described above. 17. The method of manufacturing a semiconductor device according to claim 11, wherein a catalyst layer is formed on the metal wiring, and then a barrier film is formed by an electroless plating method. 18. The method of manufacturing a semiconductor device according to claim 17, wherein the catalyst layer is selectively formed on the metal wiring by utilizing a difference in ionization tendency of different metals.